1 /**********************************************************************
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2 * $Id$ lpc18xx_qei.h 2011-06-02
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4 * @file lpc18xx_qei.h
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5 * @brief Contains all macro definitions and function prototypes
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6 * support for QEI firmware library on LPC18xx
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @defgroup QEI QEI (Quadrature Encoder Interface)
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29 * @ingroup LPC1800CMSIS_FwLib_Drivers
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33 #ifndef LPC18XX_QEI_H_
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34 #define LPC18XX_QEI_H_
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36 /* Includes ------------------------------------------------------------------- */
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37 #include "LPC18xx.h"
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38 #include "lpc_types.h"
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46 /* Public Macros -------------------------------------------------------------- */
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47 /** @defgroup QEI_Private_Macros QEI Private Macros
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51 /** QEI peripheral numver definition */
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52 #define QEI_0 (0) /** Always 0 - because we just have only one QEI peripheral */
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54 /** QEI Reset types */
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55 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
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56 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
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57 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
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58 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
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60 /** QEI Direction Invert Type Option */
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61 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
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62 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
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64 /** QEI Signal Mode Option */
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65 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
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66 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
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68 /** QEI Capture Mode Option */
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69 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
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70 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
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72 /** QEI Invert Index Signal Option */
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73 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
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74 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
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76 /** QEI timer reload option */
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77 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
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78 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
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80 /** QEI Flag Status type */
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81 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
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83 /** QEI Compare Position channel option */
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84 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
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85 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
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86 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
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88 /** QEI interrupt flag type */
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89 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
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90 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
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91 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
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92 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
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93 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
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94 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
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95 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
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96 current position interrupt */
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97 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
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98 current position interrupt */
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99 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
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100 current position interrupt */
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101 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
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102 index count interrupt */
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103 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
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104 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
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105 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
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108 /* --------------------- BIT DEFINITIONS -------------------------------------- */
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109 /* Quadrature Encoder Interface Control Register Definition --------------------- */
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110 /*********************************************************************//**
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111 * Macro defines for QEI Control register
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112 **********************************************************************/
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113 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
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114 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
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115 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
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116 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
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117 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
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119 /*********************************************************************//**
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120 * Macro defines for QEI Configuration register
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121 **********************************************************************/
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122 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
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123 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
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124 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
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125 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
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126 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
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128 /*********************************************************************//**
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129 * Macro defines for QEI Status register
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130 **********************************************************************/
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131 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
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132 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
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134 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
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135 /*********************************************************************//**
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136 * Macro defines for QEI Interrupt Status register
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137 **********************************************************************/
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138 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
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139 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
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140 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
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141 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
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142 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
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143 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
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144 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
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145 current position */
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146 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
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147 current position */
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148 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
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149 current position */
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150 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
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152 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
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153 both the POS0_Int bit is set and the REV_Int is set */
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154 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
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155 both the POS1_Int bit is set and the REV_Int is set */
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156 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
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157 both the POS2_Int bit is set and the REV_Int is set */
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158 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
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160 /*********************************************************************//**
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161 * Macro defines for QEI Interrupt Set register
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162 **********************************************************************/
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163 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
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164 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
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165 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
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166 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
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167 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
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168 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
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169 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
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170 current position */
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171 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
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172 current position */
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173 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
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174 current position */
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175 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
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177 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
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178 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
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179 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
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180 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
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182 /*********************************************************************//**
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183 * Macro defines for QEI Interrupt Clear register
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184 **********************************************************************/
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185 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
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186 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
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187 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
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188 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
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189 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
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190 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
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191 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
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192 current position */
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193 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
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194 current position */
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195 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
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196 current position */
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197 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
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199 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
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200 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
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201 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
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202 #define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Clear register bit-mask */
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204 /*********************************************************************//**
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205 * Macro defines for QEI Interrupt Enable register
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206 **********************************************************************/
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207 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
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208 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
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209 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
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210 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
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211 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
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212 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
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213 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
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214 current position */
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215 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
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216 current position */
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217 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
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218 current position */
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219 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
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221 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
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222 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
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223 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
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224 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
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226 /*********************************************************************//**
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227 * Macro defines for QEI Interrupt Enable Set register
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228 **********************************************************************/
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229 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
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230 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
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231 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
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232 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
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233 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
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234 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
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235 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
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236 current position */
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237 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
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238 current position */
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239 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
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240 current position */
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241 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
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243 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
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244 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
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245 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
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246 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
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248 /*********************************************************************//**
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249 * Macro defines for QEI Interrupt Enable Clear register
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250 **********************************************************************/
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251 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
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252 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
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253 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
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254 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
\r
255 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
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256 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
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257 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
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258 current position */
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259 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
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260 current position */
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261 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
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262 current position */
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263 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
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265 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
\r
266 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
\r
267 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
\r
268 #define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Enable Clear register bit-mask */
\r
271 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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272 /* Macro check QEI peripheral */
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273 #define PARAM_QEIx(n) ((n==LPC_QEI))
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275 /* Macro check QEI reset type */
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276 #define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
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277 || (n==QEI_RESET_POSOnIDX) \
\r
278 || (n==QEI_RESET_VEL) \
\r
279 || (n==QEI_RESET_IDX))
\r
281 /* Macro check QEI Direction invert mode */
\r
282 #define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
\r
284 /* Macro check QEI signal mode */
\r
285 #define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
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287 /* Macro check QEI Capture mode */
\r
288 #define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
\r
290 /* Macro check QEI Invert index mode */
\r
291 #define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
\r
293 /* Macro check QEI Direction invert mode */
\r
294 #define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
\r
296 /* Macro check QEI status type */
\r
297 #define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
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299 /* Macro check QEI combine position type */
\r
300 #define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
\r
302 /* Macro check QEI interrupt flag type */
\r
303 #define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
\r
304 || (n==QEI_INTFLAG_TIM_Int) \
\r
305 || (n==QEI_INTFLAG_VELC_Int) \
\r
306 || (n==QEI_INTFLAG_DIR_Int) \
\r
307 || (n==QEI_INTFLAG_ERR_Int) \
\r
308 || (n==QEI_INTFLAG_ENCLK_Int) \
\r
309 || (n==QEI_INTFLAG_POS0_Int) \
\r
310 || (n==QEI_INTFLAG_POS1_Int) \
\r
311 || (n==QEI_INTFLAG_POS2_Int) \
\r
312 || (n==QEI_INTFLAG_REV_Int) \
\r
313 || (n==QEI_INTFLAG_POS0REV_Int) \
\r
314 || (n==QEI_INTFLAG_POS1REV_Int) \
\r
315 || (n==QEI_INTFLAG_POS2REV_Int))
\r
320 /* Public Types --------------------------------------------------------------- */
\r
321 /** @defgroup QEI_Public_Types QEI Public Types
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325 /*********************************************************************//**
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326 * @brief QEI structure definitions
\r
327 **********************************************************************/
\r
329 * @brief QEI Configuration structure type definition
\r
332 uint32_t DirectionInvert :1; /**< Direction invert option:
\r
333 - QEI_DIRINV_NONE: QEI Direction is normal
\r
334 - QEI_DIRINV_CMPL: QEI Direction is complemented
\r
336 uint32_t SignalMode :1; /**< Signal mode Option:
\r
337 - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
\r
338 - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
\r
340 uint32_t CaptureMode :1; /**< Capture Mode Option:
\r
341 - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
\r
342 - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
\r
344 uint32_t InvertIndex :1; /**< Invert Index Option:
\r
345 - QEI_INVINX_NONE: the sense of the index input is normal
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346 - QEI_INVINX_EN: inverts the sense of the index input
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351 * @brief Timer Reload Configuration structure type definition
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355 uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
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356 - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
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357 - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
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359 uint8_t Reserved[3];
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360 uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
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361 with Velocity Timer Reload Option
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363 } QEI_RELOADCFG_Type;
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367 uint32_t PHA_FilterVal; /**< FILTERPHA register input */
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368 uint32_t PHB_FilterVal; /**< FILTERPHB register input */
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369 uint32_t INX_FilterVal; /**< FILTERINX register input */
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370 } st_Qei_FilterCfg;
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381 /* Public Functions ----------------------------------------------------------- */
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382 /** @defgroup QEI_Public_Functions QEI Public Functions
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386 void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
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387 void QEI_DeInit(uint8_t qeiId);
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389 void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
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390 void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
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391 FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
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392 uint32_t QEI_GetPosition(uint8_t qeiId);
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393 void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
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394 void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
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395 uint32_t QEI_GetIndex(uint8_t qeiId);
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396 void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
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397 void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
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398 uint32_t QEI_GetTimer(uint8_t qeiId);
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399 uint32_t QEI_GetVelocity(uint8_t qeiId);
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400 uint32_t QEI_GetVelocityCap(uint8_t qeiId);
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401 void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
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402 void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
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403 uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
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405 FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
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406 void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
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407 void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
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408 void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
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420 #endif /* LPC18XX_QEI_H_ */
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426 /* --------------------------------- End Of File ------------------------------ */
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projects / freertos / blob