1 /**********************************************************************
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2 * $Id$ lpc18xx_uart.h 2011-06-02
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4 * @file lpc18xx_uart.h
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5 * @brief Contains all macro definitions and function prototypes
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6 * support for UART firmware library on LPC18xx
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @defgroup UART UART
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29 * @ingroup LPC1800CMSIS_FwLib_Drivers
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33 #ifndef __LPC18XX_UART_H
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34 #define __LPC18XX_UART_H
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36 /* Includes ------------------------------------------------------------------- */
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37 #include "LPC18xx.h"
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38 #include "lpc_types.h"
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46 /* Public Macros -------------------------------------------------------------- */
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47 /** @defgroup UART_Public_Macros UART Public Macros
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51 /** UART time-out definitions in case of using Read() and Write function
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52 * with Blocking Flag mode
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54 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
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60 /* Private Macros ------------------------------------------------------------- */
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61 /** @defgroup UART_Private_Macros UART Private Macros
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65 /* Accepted Error baud rate value (in percent unit) */
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66 #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
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69 /* --------------------- BIT DEFINITIONS -------------------------------------- */
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70 /*********************************************************************//**
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71 * Macro defines for Macro defines for UARTn Receiver Buffer Register
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72 **********************************************************************/
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73 #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
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75 /*********************************************************************//**
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76 * Macro defines for Macro defines for UARTn Transmit Holding Register
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77 **********************************************************************/
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78 #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
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80 /*********************************************************************//**
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81 * Macro defines for Macro defines for UARTn Divisor Latch LSB register
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82 **********************************************************************/
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83 #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
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84 #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
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86 /*********************************************************************//**
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87 * Macro defines for Macro defines for UARTn Divisor Latch MSB register
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88 **********************************************************************/
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89 #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
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90 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
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92 /*********************************************************************//**
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93 * Macro defines for Macro defines for UART interrupt enable register
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94 **********************************************************************/
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95 #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
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96 #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
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97 #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
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98 #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
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99 #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
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100 #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
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101 #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
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102 #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
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103 #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
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105 /*********************************************************************//**
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106 * Macro defines for Macro defines for UART interrupt identification register
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107 **********************************************************************/
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108 #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
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109 #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
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110 #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
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111 #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
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112 #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
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113 #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
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114 #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
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115 #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
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116 #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
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117 #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
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118 #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
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120 /*********************************************************************//**
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121 * Macro defines for Macro defines for UART FIFO control register
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122 **********************************************************************/
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123 #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
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124 #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
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125 #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
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126 #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
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127 #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
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128 #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
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129 #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
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130 #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
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131 #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
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132 #define UART_TX_FIFO_SIZE (16)
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134 /*********************************************************************//**
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135 * Macro defines for Macro defines for UART line control register
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136 **********************************************************************/
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137 #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
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138 #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
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139 #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
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140 #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
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141 #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
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142 #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
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143 #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
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144 #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
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145 #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
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146 #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
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147 #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
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148 #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
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149 #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
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151 /*********************************************************************//**
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152 * Macro defines for Macro defines for UART1 Modem Control Register
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153 **********************************************************************/
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154 #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
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155 #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
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156 #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
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157 #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
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158 #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
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159 #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
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161 /*********************************************************************//**
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162 * Macro defines for Macro defines for UART line status register
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163 **********************************************************************/
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164 #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
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165 #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
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166 #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
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167 #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
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168 #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
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169 #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
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170 #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
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171 #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
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172 #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
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174 /*********************************************************************//**
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175 * Macro defines for Macro defines for UART Modem (UART1 only) status register
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176 **********************************************************************/
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177 #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
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178 #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
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179 #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
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180 #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
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181 #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
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182 #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
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183 #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
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184 #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
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185 #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
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187 /*********************************************************************//**
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188 * Macro defines for Macro defines for UART Scratch Pad Register
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189 **********************************************************************/
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190 #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
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192 /*********************************************************************//**
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193 * Macro defines for Macro defines for UART Auto baudrate control register
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194 **********************************************************************/
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195 #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
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196 #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
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197 #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
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198 #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
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199 #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
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200 #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
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202 /*********************************************************************//**
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203 * Macro defines for Macro defines for UART IrDA control register
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204 **********************************************************************/
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205 #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
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206 #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
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207 #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
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208 #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
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209 #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
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211 /*********************************************************************//**
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212 * Macro defines for Macro defines for UART half duplex register
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213 **********************************************************************/
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214 #define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/
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216 /*********************************************************************//**
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217 * Macro defines for Macro defines for UART smart card interface control register
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218 **********************************************************************/
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219 #define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/
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220 #define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/
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221 #define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/
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222 #define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/
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223 #define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/
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225 /*********************************************************************//**
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226 * Macro defines for Macro defines for UART synchronous control register
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227 **********************************************************************/
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228 #define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/
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229 #define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/
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230 #define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/
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231 #define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/
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232 #define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/
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233 #define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/
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234 #define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/
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236 /*********************************************************************//**
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237 * Macro defines for Macro defines for UART Fractional divider register
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238 **********************************************************************/
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239 #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
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240 #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
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241 #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
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243 /*********************************************************************//**
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244 * Macro defines for Macro defines for UART Tx Enable register
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245 **********************************************************************/
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246 #define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
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247 #define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
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248 #define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */
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249 #define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */
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251 /*********************************************************************//**
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252 * Macro defines for Macro defines for UART1 RS485 Control register
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253 **********************************************************************/
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254 #define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
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256 #define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
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257 #define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
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258 #define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
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259 (bit DCTRL = 1), pin DTR is used for direction control */
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260 #define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
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261 #define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
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262 control signal on the RTS (or DTR) pin. The direction control pin
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263 will be driven to logic "1" when the transmitter has data to be sent */
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264 #define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
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266 /*********************************************************************//**
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267 * Macro defines for Macro defines for UART1 RS-485 Address Match register
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268 **********************************************************************/
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269 #define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
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271 /*********************************************************************//**
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272 * Macro defines for Macro defines for UART1 RS-485 Delay value register
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273 **********************************************************************/
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274 /* Macro defines for UART1 RS-485 Delay value register */
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275 #define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
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277 /*********************************************************************//**
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278 * Macro defines for Macro defines for UART FIFO Level register
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279 **********************************************************************/
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280 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
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281 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
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282 #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
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285 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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287 /** Macro to check the input UART_DATABIT parameters */
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288 #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
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289 || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
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291 /** Macro to check the input UART_STOPBIT parameters */
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292 #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
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294 /** Macro to check the input UART_PARITY parameters */
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295 #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
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296 || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
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297 || (parity==UART_PARITY_SP_0))
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299 /** Macro to check the input UART_FIFO parameters */
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300 #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
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301 || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
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302 || (fifo==UART_FIFO_TRGLEV3))
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304 /** Macro to check the input UART_INTCFG parameters */
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305 #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
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306 || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
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307 || (IntCfg==UART_INTCFG_ABTO))
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309 /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
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310 #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
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312 /** Macro to check the input UART_AUTOBAUD_MODE parameters */
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313 #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
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315 /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
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316 #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
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317 (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
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319 /** Macro to check the input UART_IrDA_PULSEDIV parameters */
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320 #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
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321 || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
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322 || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
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323 || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
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325 /* Macro to check the input UART1_SignalState parameters */
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326 #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
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328 /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
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329 #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
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331 /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
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332 #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
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333 || (x==UART1_MODEM_MODE_AUTO_CTS))
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335 /** Macro to check the direction control pin type */
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336 #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR))
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338 /* Macro to determine if it is valid UART port number */
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339 #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \
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340 || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
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341 || (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \
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342 || (((uint32_t *)x)==((uint32_t *)LPC_USART3)))
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343 #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3))
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344 #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
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346 /** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */
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347 #define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
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349 /** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */
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350 #define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
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357 /* Public Types --------------------------------------------------------------- */
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358 /** @defgroup UART_Public_Types UART Public Types
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362 /***********************************************************************
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363 * @brief UART enumeration
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364 **********************************************************************/
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366 * @brief UART Databit type definitions
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369 UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
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370 UART_DATABIT_6, /*!< UART 6 bit data mode */
\r
371 UART_DATABIT_7, /*!< UART 7 bit data mode */
\r
372 UART_DATABIT_8 /*!< UART 8 bit data mode */
\r
373 } UART_DATABIT_Type;
\r
376 * @brief UART Stop bit type definitions
\r
379 UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
\r
380 UART_STOPBIT_2 /*!< UART Two Stop Bits Select */
\r
381 } UART_STOPBIT_Type;
\r
384 * @brief UART Parity type definitions
\r
387 UART_PARITY_NONE = 0, /*!< No parity */
\r
388 UART_PARITY_ODD, /*!< Odd parity */
\r
389 UART_PARITY_EVEN, /*!< Even parity */
\r
390 UART_PARITY_SP_1, /*!< Forced "1" stick parity */
\r
391 UART_PARITY_SP_0 /*!< Forced "0" stick parity */
\r
392 } UART_PARITY_Type;
\r
395 * @brief FIFO Level type definitions
\r
398 UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
\r
399 UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
\r
400 UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
\r
401 UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
\r
402 } UART_FITO_LEVEL_Type;
\r
405 /********************************************************************//**
\r
406 * @brief UART Interrupt Type definitions
\r
407 **********************************************************************/
\r
409 UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
\r
410 UART_INTCFG_THRE, /*!< THR Interrupt enable*/
\r
411 UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
\r
412 UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
\r
413 UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
\r
414 UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
\r
415 UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
\r
419 * @brief UART Line Status Type definition
\r
422 UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
\r
423 UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
\r
424 UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
\r
425 UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
\r
426 UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
\r
427 UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
\r
428 UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
\r
429 UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
\r
433 * @brief UART Auto-baudrate mode type definition
\r
436 UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
\r
437 UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */
\r
438 } UART_AB_MODE_Type;
\r
441 * @brief Auto Baudrate mode configuration type definition
\r
444 UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
\r
445 FunctionalState AutoRestart; /**< Auto Restart state */
\r
446 } UART_AB_CFG_Type;
\r
449 * @brief UART End of Auto-baudrate type definition
\r
452 UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
\r
453 UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
\r
457 * UART IrDA Control type Definition
\r
460 UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
\r
461 - Configures the pulse when FixPulseEn = 1 */
\r
462 UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
\r
463 - Configures the pulse when FixPulseEn = 1 */
\r
464 UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
\r
465 - Configures the pulse when FixPulseEn = 1 */
\r
466 UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
\r
467 - Configures the pulse when FixPulseEn = 1 */
\r
468 UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
\r
469 - Configures the pulse when FixPulseEn = 1 */
\r
470 UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
\r
471 - Configures the pulse when FixPulseEn = 1 */
\r
472 UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
\r
473 - Configures the pulse when FixPulseEn = 1 */
\r
474 UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
\r
475 - Configures the pulse when FixPulseEn = 1 */
\r
476 } UART_IrDA_PULSE_Type;
\r
478 /********************************************************************//**
\r
479 * @brief UART1 Full modem - Signal states definition
\r
480 **********************************************************************/
\r
482 INACTIVE = 0, /* In-active state */
\r
483 ACTIVE = !INACTIVE /* Active state */
\r
484 }UART1_SignalState;
\r
487 * @brief UART modem status type definition
\r
490 UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
\r
491 UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
\r
492 UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
\r
493 UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
\r
494 UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
\r
495 UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
\r
496 UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
\r
497 UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
\r
498 } UART_MODEM_STAT_type;
\r
501 * @brief Modem output pin type definition
\r
504 UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
\r
505 UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
\r
506 } UART_MODEM_PIN_Type;
\r
509 * @brief UART Modem mode type definition
\r
512 UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
\r
513 UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
\r
514 UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
\r
515 } UART_MODEM_MODE_Type;
\r
518 * @brief UART Direction Control Pin type definition
\r
521 UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
\r
522 UART_RS485_DIRCTRL_DTR, /**< Pin DTR is used for direction control */
\r
523 UART_RS485_DIRCTRL_DIR /**< Pin DIR is used for direction control */
\r
524 } UART_RS485_DIRCTRL_PIN_Type;
\r
527 /********************************************************************//**
\r
528 * @brief UART Configuration Structure definition
\r
529 **********************************************************************/
\r
531 uint32_t Baud_rate; /**< UART baud rate */
\r
532 UART_PARITY_Type Parity; /**< Parity selection, should be:
\r
533 - UART_PARITY_NONE: No parity
\r
534 - UART_PARITY_ODD: Odd parity
\r
535 - UART_PARITY_EVEN: Even parity
\r
536 - UART_PARITY_SP_1: Forced "1" stick parity
\r
537 - UART_PARITY_SP_0: Forced "0" stick parity
\r
539 UART_DATABIT_Type Databits; /**< Number of data bits, should be:
\r
540 - UART_DATABIT_5: UART 5 bit data mode
\r
541 - UART_DATABIT_6: UART 6 bit data mode
\r
542 - UART_DATABIT_7: UART 7 bit data mode
\r
543 - UART_DATABIT_8: UART 8 bit data mode
\r
545 UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
\r
546 - UART_STOPBIT_1: UART 1 Stop Bits Select
\r
547 - UART_STOPBIT_2: UART 2 Stop Bits Select
\r
551 /********************************************************************//**
\r
552 * @brief UART FIFO Configuration Structure definition
\r
553 **********************************************************************/
\r
556 FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
\r
557 - ENABLE: Reset Rx FIFO in UART
\r
558 - DISABLE: Do not reset Rx FIFO in UART
\r
560 FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
\r
561 - ENABLE: Reset Tx FIFO in UART
\r
562 - DISABLE: Do not reset Tx FIFO in UART
\r
564 FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
\r
565 - ENABLE: Enable DMA mode in UART
\r
566 - DISABLE: Disable DMA mode in UART
\r
568 UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
\r
569 - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
\r
570 - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
\r
571 - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
\r
572 - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
\r
574 } UART_FIFO_CFG_Type;
\r
576 /********************************************************************//**
\r
577 * @brief UART1 Full modem - RS485 Control configuration type
\r
578 **********************************************************************/
\r
580 FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
\r
581 - ENABLE: Enable this function.
\r
582 - DISABLE: Disable this function. */
\r
583 FunctionalState Rx_State; /*!< Receiver State:
\r
584 - ENABLE: Enable Receiver.
\r
585 - DISABLE: Disable Receiver. */
\r
586 FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
\r
587 - ENABLE: ENABLE this function.
\r
588 - DISABLE: Disable this function. */
\r
589 FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
\r
590 - ENABLE: Enable this function.
\r
591 - DISABLE: Disable this function. */
\r
592 UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
\r
593 - UART1_RS485_DIRCTRL_RTS:
\r
594 pin RTS is used for direction control.
\r
595 - UART1_RS485_DIRCTRL_DTR:
\r
596 pin DTR is used for direction control. */
\r
597 SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
\r
598 the RTS (or DTR) pin:
\r
599 - RESET: The direction control pin will be driven
\r
600 to logic "0" when the transmitter has data to be sent.
\r
601 - SET: The direction control pin will be driven
\r
602 to logic "1" when the transmitter has data to be sent. */
\r
603 uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
\r
604 uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
\r
605 } UART_RS485_CTRLCFG_Type;
\r
612 /* Public Functions ----------------------------------------------------------- */
\r
613 /** @defgroup UART_Public_Functions UART Public Functions
\r
616 /* UART Init/DeInit functions --------------------------------------------------*/
\r
617 void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct);
\r
618 void UART_DeInit(LPC_USARTn_Type* UARTx);
\r
619 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
\r
621 /* UART Send/Receive functions -------------------------------------------------*/
\r
622 void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data);
\r
623 uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx);
\r
624 uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,
\r
625 uint32_t buflen, TRANSFER_BLOCK_Type flag);
\r
626 uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \
\r
627 uint32_t buflen, TRANSFER_BLOCK_Type flag);
\r
629 /* UART FIFO functions ----------------------------------------------------------*/
\r
630 void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
\r
631 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
\r
633 /* UART operate functions -------------------------------------------------------*/
\r
634 void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, \
\r
635 FunctionalState NewState);
\r
636 void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
\r
637 FunctionalState NewState);
\r
638 void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
\r
639 uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx);
\r
640 FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx);
\r
641 void UART_ForceBreak(LPC_USARTn_Type* UARTx);
\r
643 /* UART1 FullModem functions ----------------------------------------------------*/
\r
644 void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \
\r
645 UART1_SignalState NewState);
\r
646 void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \
\r
647 FunctionalState NewState);
\r
648 uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx);
\r
650 /* UART RS485 functions ----------------------------------------------------------*/
\r
651 void UART_RS485Config(LPC_USARTn_Type *UARTx, \
\r
652 UART_RS485_CTRLCFG_Type *RS485ConfigStruct);
\r
653 void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
\r
654 void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr);
\r
655 uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size);
\r
657 /* UART IrDA functions-------------------------------------------------------------*/
\r
658 void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
\r
659 void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
\r
660 void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv);
\r
671 #endif /* __LPC18XX_UART_H */
\r
677 /* --------------------------------- End Of File ------------------------------ */
\r
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