2 * @brief Ethernet control functions
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5 * Copyright(C) NXP Semiconductors, 2012
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6 * All rights reserved.
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * LPC products. This software is supplied "AS IS" without any warranties of
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12 * any kind, and NXP Semiconductors and its licensor disclaim any and
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13 * all warranties, express or implied, including all implied warranties of
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14 * merchantability, fitness for a particular purpose and non-infringement of
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15 * intellectual property rights. NXP Semiconductors assumes no responsibility
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16 * or liability for the use of the software, conveys no license or rights under any
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17 * patent, copyright, mask work right, or any other intellectual property rights in
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18 * or to any products. NXP Semiconductors reserves the right to make changes
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19 * in the software without notification. NXP Semiconductors also makes no
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20 * representation or warranty that such application will be suitable for the
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21 * specified use without further testing or modification.
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24 * Permission to use, copy, modify, and distribute this software and its
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25 * documentation is hereby granted, under NXP Semiconductors' and its
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26 * licensor's relevant copyrights in the software, without fee, provided that it
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27 * is used in conjunction with NXP Semiconductors microcontrollers. This
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28 * copyright, permission, and disclaimer notice must appear in all copies of
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32 #ifndef __ENET_001_H_
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33 #define __ENET_001_H_
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35 #include "sys_config.h"
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42 /** @defgroup IP_ENET_001 IP: Ethernet register block and driver
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43 * @ingroup IP_Drivers
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48 * @brief 10/100 MII & RMII Ethernet with timestamping register block structure
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50 typedef struct { /*!< ETHERNET Structure */
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51 __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */
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52 __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */
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53 __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */
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54 __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */
\r
55 __IO uint32_t MAC_MII_ADDR; /*!< MII address register */
\r
56 __IO uint32_t MAC_MII_DATA; /*!< MII data register */
\r
57 __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */
\r
58 __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */
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59 __I uint32_t RESERVED0;
\r
60 __I uint32_t MAC_DEBUG; /*!< Debug register */
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61 __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */
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62 __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */
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63 __I uint32_t RESERVED1[2];
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64 __I uint32_t MAC_INTR; /*!< Interrupt status register */
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65 __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */
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66 __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */
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67 __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */
\r
68 __I uint32_t RESERVED2[430];
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69 __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */
\r
70 __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */
\r
71 __I uint32_t SECONDS; /*!< System time seconds register */
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72 __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */
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73 __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */
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74 __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */
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75 __IO uint32_t ADDEND; /*!< Time stamp addend register */
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76 __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */
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77 __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */
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78 __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */
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79 __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */
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80 __IO uint32_t PPSCTRL; /*!< PPS control register */
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81 __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */
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82 __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */
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83 __I uint32_t RESERVED3[562];
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84 __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */
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85 __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */
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86 __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */
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87 __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */
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88 __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */
\r
89 __IO uint32_t DMA_STAT; /*!< Status register */
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90 __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */
\r
91 __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */
\r
92 __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */
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93 __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */
\r
94 __I uint32_t RESERVED4[8];
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95 __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */
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96 __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */
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97 __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */
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98 __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */
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102 * @brief MAC_CONFIG register bit defines
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104 #define MAC_CFG_RE (1 << 2) /*!< Receiver enable */
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105 #define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */
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106 #define MAC_CFG_DF (1 << 4) /*!< Deferral Check */
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107 #define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */
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108 #define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */
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109 #define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */
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110 #define MAC_CFG_DR (1 << 9) /*!< Disable Retry */
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111 #define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */
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112 #define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */
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113 #define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */
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114 #define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */
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115 #define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */
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116 #define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */
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117 #define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */
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118 #define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */
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119 #define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */
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120 #define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */
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121 #define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */
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124 * @brief MAC_FRAME_FILTER register bit defines
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126 #define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */
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127 #define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */
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128 #define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */
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129 #define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */
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130 #define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */
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131 #define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */
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132 #define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */
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133 #define MAC_FF_RA (1UL << 31) /*!< Receive all */
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136 * @brief MAC_MII_ADDR register bit defines
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138 #define MAC_MIIA_GB (1 << 0) /*!< MII busy */
\r
139 #define MAC_MIIA_W (1 << 1) /*!< MII write */
\r
140 #define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */
\r
141 #define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */
\r
142 #define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */
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145 * @brief MAC_MII_DATA register bit defines
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147 #define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */
\r
150 * @brief MAC_FLOW_CONTROL register bit defines
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152 #define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */
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153 #define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */
\r
154 #define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */
\r
155 #define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */
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156 #define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */
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157 #define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */
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158 #define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */
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161 * @brief MAC_VLAN_TAG register bit defines
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163 #define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */
\r
164 #define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */
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167 * @brief MAC_PMT_CTRL_STAT register bit defines
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169 #define MAC_PMT_PD (1 << 0) /*!< Power-down */
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170 #define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */
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171 #define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */
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172 #define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */
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173 #define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */
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174 #define MAC_PMT_GU (1 << 9) /*!< Global Unicast */
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175 #define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */
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178 * @brief MAC_INTR_MASK register bit defines
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180 #define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */
\r
183 * @brief MAC_ADDR0_HIGH register bit defines
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185 #define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
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188 * @brief MAC_ADDR0_HIGH register bit defines
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190 #define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
\r
193 * @brief MAC_TIMESTAMP register bit defines
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195 #define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */
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196 #define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */
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197 #define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */
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198 #define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */
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199 #define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */
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200 #define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */
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201 #define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */
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202 #define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */
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203 #define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */
\r
204 #define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */
\r
205 #define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */
\r
206 #define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */
\r
207 #define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */
\r
208 #define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */
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209 #define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */
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210 #define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */
\r
213 * @brief DMA_BUS_MODE register bit defines
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215 #define DMA_BM_SWR (1 << 0) /*!< Software reset */
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216 #define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */
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217 #define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */
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218 #define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */
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219 #define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */
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220 #define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */
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221 #define DMA_BM_FB (1 << 16) /*!< Fixed burst */
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222 #define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */
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223 #define DMA_BM_USP (1 << 23) /*!< Use separate PBL */
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224 #define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */
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225 #define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */
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226 #define DMA_BM_MB (1 << 26) /*!< Mixed burst */
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227 #define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */
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230 * @brief DMA_STAT register bit defines
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232 #define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */
\r
233 #define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */
\r
234 #define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */
\r
235 #define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */
\r
236 #define DMA_ST_OVF (1 << 4) /*!< Receive overflow */
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237 #define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */
\r
238 #define DMA_ST_RI (1 << 6) /*!< Receive interrupt */
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239 #define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */
\r
240 #define DMA_ST_RPS (1 << 8) /*!< Received process stopped */
\r
241 #define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */
\r
242 #define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */
\r
243 #define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */
\r
244 #define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */
\r
245 #define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */
\r
246 #define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */
\r
247 #define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */
\r
250 * @brief DMA_OP_MODE register bit defines
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252 #define DMA_OM_SR (1 << 1) /*!< Start/stop receive */
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253 #define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */
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254 #define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */
\r
255 #define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */
\r
256 #define DMA_OM_FEF (1 << 7) /*!< Forward error frames */
\r
257 #define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */
\r
258 #define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */
\r
259 #define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */
\r
260 #define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */
\r
261 #define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */
\r
262 #define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */
\r
263 #define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */
\r
266 * @brief DMA_INT_EN register bit defines
\r
268 #define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */
\r
269 #define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */
\r
270 #define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */
\r
271 #define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */
\r
272 #define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */
\r
273 #define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */
\r
274 #define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */
\r
275 #define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */
\r
276 #define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */
\r
277 #define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */
\r
278 #define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */
\r
279 #define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */
\r
280 #define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */
\r
281 #define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */
\r
282 #define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */
\r
285 * @brief DMA_MFRM_BUFOF register bit defines
\r
287 #define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */
\r
288 #define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */
\r
289 #define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */
\r
290 #define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */
\r
293 * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines
\r
295 #define TDES_DB (1 << 0) /*!< Deferred Bit */
\r
296 #define TDES_UF (1 << 1) /*!< Underflow Error */
\r
297 #define TDES_ED (1 << 2) /*!< Excessive Deferral */
\r
298 #define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */
\r
299 #define TDES_VF (1 << 7) /*!< VLAN Frame */
\r
300 #define TDES_EC (1 << 8) /*!< Excessive Collision */
\r
301 #define TDES_LC (1 << 9) /*!< Late Collision */
\r
302 #define TDES_NC (1 << 10) /*!< No Carrier */
\r
303 #define TDES_LCAR (1 << 11) /*!< Loss of Carrier */
\r
304 #define TDES_IPE (1 << 12) /*!< IP Payload Error */
\r
305 #define TDES_FF (1 << 13) /*!< Frame Flushed */
\r
306 #define TDES_JT (1 << 14) /*!< Jabber Timeout */
\r
307 #define TDES_ES (1 << 15) /*!< Error Summary */
\r
308 #define TDES_IHE (1 << 16) /*!< IP Header Error */
\r
309 #define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */
\r
310 #define TDES_OWN (1UL << 31) /*!< Own Bit */
\r
313 * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines
\r
315 #define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */
\r
316 #define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */
\r
317 #define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */
\r
318 #define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */
\r
319 #define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */
\r
320 #define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */
\r
321 #define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */
\r
322 #define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */
\r
323 #define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */
\r
326 * @brief TRAN_DESC_T only BSIZE field bit defines
\r
328 #define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */
\r
329 #define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */
\r
330 #define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */
\r
331 #define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */
\r
332 #define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */
\r
333 #define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */
\r
334 #define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */
\r
335 #define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */
\r
336 #define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */
\r
337 #define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
\r
338 #define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
\r
341 * @brief TRAN_DESC_ENH_T only BSIZE field bit defines
\r
343 #define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
\r
344 #define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
\r
347 * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines
\r
349 #define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */
\r
350 #define RDES_CE (1 << 1) /*!< CRC Error */
\r
351 #define RDES_DRE (1 << 2) /*!< Dribble Bit Error */
\r
352 #define RDES_RE (1 << 3) /*!< Receive Error */
\r
353 #define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */
\r
354 #define RDES_FT (1 << 5) /*!< Frame Type */
\r
355 #define RDES_LC (1 << 6) /*!< Late Collision */
\r
356 #define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */
\r
357 #define RDES_LS (1 << 8) /*!< Last Descriptor */
\r
358 #define RDES_FS (1 << 9) /*!< First Descriptor */
\r
359 #define RDES_VLAN (1 << 10) /*!< VLAN Tag */
\r
360 #define RDES_OE (1 << 11) /*!< Overflow Error */
\r
361 #define RDES_LE (1 << 12) /*!< Length Error */
\r
362 #define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */
\r
363 #define RDES_DE (1 << 14) /*!< Descriptor Error */
\r
364 #define RDES_ES (1 << 15) /*!< ES: Error Summary */
\r
365 #define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */
\r
366 #define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */
\r
367 #define RDES_OWN (1UL << 31) /*!< Own Bit */
\r
370 * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines
\r
372 #define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */
\r
375 * @brief REC_DESC_T pnly CTRL field bit defines
\r
377 #define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */
\r
378 #define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */
\r
379 #define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
\r
380 #define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
\r
383 * @brief REC_DESC_ENH_T only CTRL field bit defines
\r
385 #define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */
\r
386 #define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */
\r
387 #define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
\r
388 #define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
\r
391 * @brief REC_DESC_ENH_T only EXTSTAT field bit defines
\r
393 #define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */
\r
394 #define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */
\r
395 #define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */
\r
396 #define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */
\r
397 #define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */
\r
398 #define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */
\r
399 #define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */
\r
402 * @brief Maximum size of an ethernet buffer
\r
404 #define EMAC_ETH_MAX_FLEN (1536)
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407 * @brief Structure of a transmit descriptor (without timestamp)
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410 __IO uint32_t CTRLSTAT; /*!< TDES control and status word */
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411 __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
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412 __IO uint32_t B1ADD; /*!< Buffer 1 address */
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413 __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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414 } IP_ENET_001_TXDESC_T;
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417 * @brief Structure of a enhanced transmit descriptor (with timestamp)
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420 __IO uint32_t CTRLSTAT; /*!< TDES control and status word */
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421 __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
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422 __IO uint32_t B1ADD; /*!< Buffer 1 address */
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423 __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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424 __IO uint32_t TDES4; /*!< Reserved */
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425 __IO uint32_t TDES5; /*!< Reserved */
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426 __IO uint32_t TTSL; /*!< Timestamp value low */
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427 __IO uint32_t TTSH; /*!< Timestamp value high */
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428 } IP_ENET_001_ENHTXDESC_T;
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431 * @brief Structure of a receive descriptor (without timestamp)
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434 __IO uint32_t STATUS; /*!< RDES status word */
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435 __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */
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436 __IO uint32_t B1ADD; /*!< Buffer 1 address */
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437 __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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438 } IP_ENET_001_RXDESC_T;
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441 * @brief Structure of a enhanced receive descriptor (with timestamp)
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444 __IO uint32_t STATUS; /*!< RDES status word */
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445 __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */
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446 __IO uint32_t B1ADD; /*!< Buffer 1 address */
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447 __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
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448 __IO uint32_t EXTSTAT; /*!< Extended Status */
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449 __IO uint32_t RDES5; /*!< Reserved */
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450 __IO uint32_t RTSL; /*!< Timestamp value low */
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451 __IO uint32_t RTSH; /*!< Timestamp value high */
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452 } IP_ENET_001_ENHRXDESC_T;
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455 * @brief Resets the ethernet interface
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456 * @param pENET : Pointer to selected ENET peripheral
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458 * @note Resets the ethernet interface. This should be called prior to
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459 * IP_ENET_Init with a small delay after this call.
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461 void IP_ENET_Reset(IP_ENET_001_T *pENET);
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464 * @brief Sets the address of the interface
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465 * @param pENET : Pointer to selected ENET peripheral
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466 * @param macAddr : Pointer to the 6 bytes used for the MAC address
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469 void IP_ENET_SetADDR(IP_ENET_001_T *pENET, const uint8_t *macAddr);
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472 * @brief Initialize ethernet interface
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473 * @param pENET : Pointer to selected ENET peripheral
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475 * @note Performs basic initialization of the ethernet interface in a default
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476 * state. This is enough to place the interface in a usable state, but
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477 * may require more setup outside this function.
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479 void IP_ENET_Init(IP_ENET_001_T *pENET);
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482 * @brief Sets up the PHY link clock divider and PHY address
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483 * @param pENET : Pointer to selected ENET peripheral
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484 * @param div : Divider value, may vary per chip
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485 * @param addr : PHY address, used with MII read and write
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488 void IP_ENET_SetupMII(IP_ENET_001_T *pENET, uint32_t div, uint8_t addr);
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491 * @brief De-initialize the ethernet interface
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492 * @param pENET : Pointer to selected ENET peripheral
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495 void IP_ENET_DeInit(IP_ENET_001_T *pENET);
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498 * @brief Starts a PHY write via the MII
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499 * @param pENET : Pointer to selected ENET peripheral
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500 * @param reg : PHY register to write
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501 * @param data : Data to write to PHY register
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503 * @note Start a PHY write operation. Does not block, requires calling
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504 * IP_ENET_IsMIIBusy to determine when write is complete.
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506 void IP_ENET_StartMIIWrite(IP_ENET_001_T *pENET, uint8_t reg, uint16_t data);
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509 * @brief Starts a PHY read via the MII
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510 * @param pENET : Pointer to selected ENET peripheral
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511 * @param reg : PHY register to read
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513 * @note Start a PHY read operation. Does not block, requires calling
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514 * IP_ENET_IsMIIBusy to determine when read is complete and calling
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515 * IP_ENET_ReadMIIData to get the data.
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517 void IP_ENET_StartMIIRead(IP_ENET_001_T *pENET, uint8_t reg);
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520 * @brief Returns MII link (PHY) busy status
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521 * @param pENET : Pointer to selected ENET peripheral
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522 * @return Returns true if busy, otherwise false
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524 bool IP_ENET_IsMIIBusy(IP_ENET_001_T *pENET);
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527 * @brief Returns the value read from the PHY
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528 * @param pENET : Pointer to selected ENET peripheral
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529 * @return Read value from PHY
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531 STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_T *pENET)
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533 return pENET->MAC_MII_DATA;
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537 * @brief Enables ethernet transmit
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538 * @param pENET : Pointer to selected ENET peripheral
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541 STATIC INLINE void IP_ENET_TXEnable(IP_ENET_001_T *pENET)
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543 pENET->MAC_CONFIG |= MAC_CFG_TE;
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544 pENET->DMA_OP_MODE |= DMA_OM_ST;
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548 * @brief Disables ethernet transmit
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549 * @param pENET : Pointer to selected ENET peripheral
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552 STATIC INLINE void IP_ENET_TXDisable(IP_ENET_001_T *pENET)
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554 pENET->MAC_CONFIG &= ~MAC_CFG_TE;
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558 * @brief Enables ethernet packet reception
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559 * @param pENET : Pointer to selected ENET peripheral
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562 STATIC INLINE void IP_ENET_RXEnable(IP_ENET_001_T *pENET)
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564 pENET->MAC_CONFIG |= MAC_CFG_RE;
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565 pENET->DMA_OP_MODE |= DMA_OM_SR;
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569 * @brief Disables ethernet packet reception
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570 * @param pENET : Pointer to selected ENET peripheral
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573 STATIC INLINE void IP_ENET_RXDisable(IP_ENET_001_T *pENET)
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575 pENET->MAC_CONFIG &= ~MAC_CFG_RE;
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579 * @brief Sets full or half duplex for the interface
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580 * @param pENET : Pointer to selected ENET peripheral
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581 * @param full : true to selected full duplex, false for half
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584 void IP_ENET_SetDuplex(IP_ENET_001_T *pENET, bool full);
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587 * @brief Sets speed for the interface
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588 * @param pENET : Pointer to selected ENET peripheral
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589 * @param speed100 : true to select 100Mbps mode, false for 10Mbps
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592 void IP_ENET_SetSpeed(IP_ENET_001_T *pENET, bool speed100);
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595 * @brief Configures the initial ethernet descriptors
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596 * @param pENET : Pointer to selected ENET peripheral
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597 * @param pTXDescs : Pointer to TX descriptor list
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598 * @param pRXDescs : Pointer to RX descriptor list
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601 void IP_ENET_InitDescriptors(IP_ENET_001_T *pENET,
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602 IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs);
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605 * @brief Starts receive polling of RX descriptors
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606 * @param pENET : Pointer to selected ENET peripheral
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609 STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_T *pENET)
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611 /* Start receive polling */
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612 pENET->DMA_REC_POLL_DEMAND = 1;
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616 * @brief Starts transmit polling of TX descriptors
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617 * @param pENET : Pointer to selected ENET peripheral
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620 STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_T *pENET)
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622 /* Start transmit polling */
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623 pENET->DMA_TRANS_POLL_DEMAND = 1;
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634 #endif /* __ENET_001_H_ */
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projects / freertos / blob