[freertos] /

/*\r
 * Copyright(C) NXP Semiconductors, 2012\r
 * All rights reserved.\r
 *\r
 * Software that is described herein is for illustrative purposes only\r
 * which provides customers with programming information regarding the\r
 * LPC products.  This software is supplied "AS IS" without any warranties of\r
 * any kind, and NXP Semiconductors and its licensor disclaim any and\r
 * all warranties, express or implied, including all implied warranties of\r
 * merchantability, fitness for a particular purpose and non-infringement of\r
 * intellectual property rights.  NXP Semiconductors assumes no responsibility\r
 * or liability for the use of the software, conveys no license or rights under any\r
 * patent, copyright, mask work right, or any other intellectual property rights in\r
 * or to any products. NXP Semiconductors reserves the right to make changes\r
 * in the software without notification. NXP Semiconductors also makes no\r
 * representation or warranty that such application will be suitable for the\r
 * specified use without further testing or modification.\r
 *\r
 * Permission to use, copy, modify, and distribute this software and its\r
 * documentation is hereby granted, under NXP Semiconductors' and its\r
 * licensor's relevant copyrights in the software, without fee, provided that it\r
 * is used in conjunction with NXP Semiconductors microcontrollers.  This\r
 * copyright, permission, and disclaimer notice must appear in all copies of\r
 * this code.\r
 */\r
\r
#include "board.h"\r
\r
/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code\r
 * @ingroup BOARD_NGX_XPLORER_18304330\r
 * The System initialization code is called prior to the application and\r
 * initializes the board for run-time operation. Board initialization\r
 * for the NGX Xplorer boards includes clock setup and default pin muxing\r
 * configuration.\r
 *\r
 * With the exception of stack space, no RW memory is used for this call.\r
 *\r
 * LPC1830 and LPC4330 NGX Xplorer setup<BR>\r
 *  Clocking:<BR>\r
 *   All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>\r
 *   CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>\r
 *   SPIFI FLASH clock setup for fastest speed<BR>\r
 *   CGU Dividers A, C, D and E are used for the LCD, USB, and SPIFI.\r
 *  Pin muxing:<BR>\r
 *   Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>\r
 *  Memory:<BR>\r
 *   There is no memory setup for this board.\r
 * @{\r
 */\r
\r
#ifndef CORE_M0\r
/* SCR pin definitions for pin muxing */\r
typedef struct {\r
        uint8_t pingrp;         /* Pin group */\r
        uint8_t pinnum;         /* Pin number */\r
        uint16_t modefunc;      /* Pin mode and function for SCU */\r
} PINMUX_GRP_T;\r
\r
/* Structure for initial base clock states */\r
struct CLK_BASE_STATES {\r
        CHIP_CGU_BASE_CLK_T clk;        /* Base clock */\r
        CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */\r
        bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */\r
        bool powerdn;           /* Set to true if the base clock is initially powered down */\r
};\r
\r
/* Initial base clock states are mostly on */\r
STATIC const struct CLK_BASE_STATES InitClkStates[] = {\r
        {CLK_BASE_SAFE, CLKIN_IRC, true, false},\r
        {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_USB0, CLKIN_USBPLL, true, true},\r
#if defined(CHIP_LPC43XX)\r
        {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},\r
#endif\r
        {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},\r
#if defined(USE_RMII)\r
        {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},\r
#else\r
        {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},\r
#endif\r
        {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},\r
        {CLK_BASE_OUT, CLKINPUT_PD, true, false},\r
        {CLK_BASE_APLL, CLKINPUT_PD, true, false},\r
        {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},\r
        {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},\r
\r
        /* Clocks derived from dividers */\r
        {CLK_BASE_LCD, CLKIN_IDIVC, true, false},\r
        {CLK_BASE_USB1, CLKIN_IDIVD, true, true}\r
};\r
\r
/* SPIFI high speed pin mode setup */\r
STATIC const PINMUX_GRP_T spifipinmuxing[] = {\r
        {0x3, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI CLK */\r
        {0x3, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D3 */\r
        {0x3, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D2 */\r
        {0x3, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D1 */\r
        {0x3, 7,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},   /* SPIFI D0 */\r
        {0x3, 8,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}    /* SPIFI CS/SSEL */\r
};\r
\r
/* USB PLL pre-initialized setup values for 480MHz output rate */\r
static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {\r
        0x0000601D,     /* Default control with main osc input, PLL disabled */\r
        0x06167FFA,     /* M-divider value for 480MHz output from 12MHz input */\r
        0x00000000,     /* N-divider value */\r
        0x00000000      /* Not applicable for USB PLL */\r
};\r
\r
/* Audio PLL pre-initialized setup values for FIXME output rate */\r
// static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {\r
//      0x0000601D, /* Default control with main osc input, PLL disabled */\r
//      0x06167FFA, /* M-divider value for FIXME output from 12MHz input */\r
//      0x00000000, /* N-divider value */\r
//      0x00000000  /* FIXME */\r
// };\r
\r
/* Setup system clocking */\r
STATIC void SystemSetupClocking(void)\r
{\r
        int i;\r
\r
        /* Switch main system clocking to crystal */\r
        Chip_Clock_EnableCrystal();\r
        Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);\r
\r
        /* Setup PLL for 100MHz and switch main system clocking */\r
        Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);\r
        Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);\r
\r
        /* Setup PLL for maximum clock */\r
        Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);\r
\r
        /* Setup system base clocks and initial states. This won't enable and\r
           disable individual clocks, but sets up the base clock sources for\r
           each individual peripheral clock. */\r
        for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {\r
                Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,\r
                                                                InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);\r
        }\r
\r
        /* Reset and enable 32Khz oscillator */\r
        LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));\r
        LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);\r
\r
        /* SPIFI pin setup is done prior to setting up system clocking */\r
        for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {\r
                Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,\r
                                                   spifipinmuxing[i].modefunc);\r
        }\r
\r
        /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.\r
           Divide rate is based on CPU speed and speed of SPI FLASH part. */\r
#if (MAX_CLOCK_FREQ > 180000000)\r
        Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);\r
#else\r
        Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);\r
#endif\r
        Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);\r
\r
        /* Attach main PLL clock to divider C with a divider of 2 */\r
        Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);\r
\r
        /* Setup default USB PLL state for a 480MHz output and attach */\r
        Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);\r
\r
        /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are\r
           chained to make a divide by 8 function. Connect the output of\r
           divider D to the USB1 base clock. */\r
        Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);\r
        Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);\r
        Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);\r
\r
        /* Setup default audio PLL state for a FIXME output */\r
        //      Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME\r
}\r
\r
STATIC const PINMUX_GRP_T pinmuxing[] = {\r
        /* RMII pin group */\r
        {0x1, 15,\r
         (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
        {0x0, 0,\r
         (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},\r
        {0x1, 16,\r
         (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},\r
        {0x0, 1,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},\r
        {0x1, 19,\r
         (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},\r
        {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
        {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
        {0x1, 17,\r
         (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
        {0x2, 0,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},\r
        /* Board LEDs */\r
        {0x2, 11, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},\r
        {0x2, 12, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},\r
        /*  I2S  */\r
        {0x3, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
        {0x6, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC4)},\r
        {0x7, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
        {0x6, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},\r
        {0x7, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
        {0x6, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},\r
};\r
\r
/* Sets up system pin muxing */\r
STATIC void SystemSetupMuxing(void)\r
{\r
        int i;\r
\r
        /* Setup system level pin muxing */\r
        for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {\r
                Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,\r
                                                   pinmuxing[i].modefunc);\r
        }\r
}\r
\r
/* Nothing to do for the Xplorer board */\r
STATIC void SystemSetupMemory(void)\r
{}\r
\r
#endif\r
\r
/**\r
 * @brief       Setup the system\r
 * @return      none\r
 * SystemInit() is called prior to the application and sets up system\r
 * clocking, memory, and any resources needed prior to the application\r
 * starting.\r
 */\r
void SystemInit(void)\r
{\r
#if defined(CORE_M3) || defined(CORE_M4)\r
        unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;\r
\r
#if defined(__IAR_SYSTEMS_ICC__)\r
        extern void *__vector_table;\r
\r
        *pSCB_VTOR = (unsigned int) &__vector_table;\r
#elif defined(__CODE_RED)\r
        extern void *g_pfnVectors;\r
\r
        *pSCB_VTOR = (unsigned int) &g_pfnVectors;\r
#elif defined(__ARMCC_VERSION)\r
        extern void *__Vectors;\r
\r
        *pSCB_VTOR = (unsigned int) &__Vectors;\r
#endif\r
\r
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1\r
        fpuInit();\r
#endif\r
\r
        /* Setup system clocking and memory. This is done early to allow the\r
           application and tools to clear memory and use scatter loading to\r
           external memory. */\r
        SystemSetupClocking();\r
        SystemSetupMuxing();\r
        SystemSetupMemory();\r
#endif\r
}\r
\r
/**\r
 * @}\r
 */\r