1 /***************************************************************************//**
\r
3 * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
\r
6 *******************************************************************************
\r
8 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
\r
9 *******************************************************************************
\r
11 * Permission is granted to anyone to use this software for any purpose,
\r
12 * including commercial applications, and to alter it and redistribute it
\r
13 * freely, subject to the following restrictions:
\r
15 * 1. The origin of this software must not be misrepresented; you must not
\r
16 * claim that you wrote the original software.
\r
17 * 2. Altered source versions must be plainly marked as such, and must not be
\r
18 * misrepresented as being the original software.
\r
19 * 3. This notice may not be removed or altered from any source distribution.
\r
21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
\r
22 * obligation to support this Software. Silicon Labs is providing the
\r
23 * Software "AS IS", with no express or implied warranties of any kind,
\r
24 * including, but not limited to, any implied warranties of merchantability
\r
25 * or fitness for any particular purpose or warranties against infringement
\r
26 * of any proprietary rights of a third party.
\r
28 * Silicon Labs will not be liable for any consequential, incidental, or
\r
29 * special damages, or any other relief, or for any claim by any third party,
\r
30 * arising from your use of this Software.
\r
32 ******************************************************************************/
\r
35 #ifndef __SILICON_LABS_EM_USART_H__
\r
36 #define __SILICON_LABS_EM_USART_H__
\r
38 #include "em_device.h"
\r
39 #if defined(USART_COUNT) && (USART_COUNT > 0)
\r
41 #include <stdbool.h>
\r
47 /***************************************************************************//**
\r
48 * @addtogroup EM_Library
\r
50 ******************************************************************************/
\r
52 /***************************************************************************//**
\r
54 * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) peripheral API
\r
56 ******************************************************************************/
\r
58 /*******************************************************************************
\r
59 ******************************** ENUMS ************************************
\r
60 ******************************************************************************/
\r
62 /** Databit selection. */
\r
65 usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
\r
66 usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
\r
67 usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
\r
68 usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 databits (not available for UART). */
\r
69 usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 databits. */
\r
70 usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 databits. */
\r
71 usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 databits (not available for UART). */
\r
72 usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 databits (not available for UART). */
\r
73 usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 databits (not available for UART). */
\r
74 usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 databits (not available for UART). */
\r
75 usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 databits (not available for UART). */
\r
76 usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 databits (not available for UART). */
\r
77 usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
\r
78 } USART_Databits_TypeDef;
\r
81 /** Enable selection. */
\r
84 /** Disable both receiver and transmitter. */
\r
87 /** Enable receiver only, transmitter disabled. */
\r
88 usartEnableRx = USART_CMD_RXEN,
\r
90 /** Enable transmitter only, receiver disabled. */
\r
91 usartEnableTx = USART_CMD_TXEN,
\r
93 /** Enable both receiver and transmitter. */
\r
94 usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
\r
95 } USART_Enable_TypeDef;
\r
98 /** Oversampling selection, used for asynchronous operation. */
\r
101 usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
\r
102 usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
\r
103 usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
\r
104 usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
\r
105 } USART_OVS_TypeDef;
\r
108 /** Parity selection, mainly used for asynchronous operation. */
\r
111 usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
\r
112 usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
\r
113 usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
\r
114 } USART_Parity_TypeDef;
\r
117 /** Stopbits selection, used for asynchronous operation. */
\r
120 usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
\r
121 usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
\r
122 usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
\r
123 usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
\r
124 } USART_Stopbits_TypeDef;
\r
127 /** Clock polarity/phase mode. */
\r
130 /** Clock idle low, sample on rising edge. */
\r
131 usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
\r
133 /** Clock idle low, sample on falling edge. */
\r
134 usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING,
\r
136 /** Clock idle high, sample on falling edge. */
\r
137 usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING,
\r
139 /** Clock idle high, sample on rising edge. */
\r
140 usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
\r
141 } USART_ClockMode_TypeDef;
\r
144 /** Pulse width selection for IrDA mode. */
\r
147 /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
\r
148 usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
\r
150 /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */
\r
151 usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO,
\r
153 /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */
\r
154 usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE,
\r
156 /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */
\r
157 usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
\r
158 } USART_IrDAPw_Typedef;
\r
161 /** PRS channel selection for IrDA mode. */
\r
164 usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
\r
165 usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
\r
166 usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
\r
167 usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, /**< PRS channel 3 */
\r
168 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH4)
\r
169 usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, /**< PRS channel 4 */
\r
171 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH5)
\r
172 usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, /**< PRS channel 5 */
\r
174 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH6)
\r
175 usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, /**< PRS channel 6 */
\r
177 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH7)
\r
178 usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7, /**< PRS channel 7 */
\r
180 } USART_IrDAPrsSel_Typedef;
\r
182 #if defined(_USART_I2SCTRL_MASK)
\r
183 /** I2S format selection. */
\r
186 usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
\r
187 usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
\r
188 usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
\r
189 usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data */
\r
190 usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data */
\r
191 usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data */
\r
192 usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data */
\r
193 usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data */
\r
194 } USART_I2sFormat_TypeDef;
\r
196 /** I2S frame data justify. */
\r
199 usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
\r
200 usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
\r
201 } USART_I2sJustify_TypeDef;
\r
204 #if defined(_USART_INPUT_MASK)
\r
205 /** USART Rx input PRS selection. */
\r
208 usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
\r
209 usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
\r
210 usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
\r
211 usartPrsRxCh3 = USART_INPUT_RXPRSSEL_PRSCH3, /**< PRSCH3 selected as USART_INPUT */
\r
213 #if defined(USART_INPUT_RXPRSSEL_PRSCH7)
\r
214 usartPrsRxCh4 = USART_INPUT_RXPRSSEL_PRSCH4, /**< PRSCH4 selected as USART_INPUT */
\r
215 usartPrsRxCh5 = USART_INPUT_RXPRSSEL_PRSCH5, /**< PRSCH5 selected as USART_INPUT */
\r
216 usartPrsRxCh6 = USART_INPUT_RXPRSSEL_PRSCH6, /**< PRSCH6 selected as USART_INPUT */
\r
217 usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7, /**< PRSCH7 selected as USART_INPUT */
\r
220 #if defined(USART_INPUT_RXPRSSEL_PRSCH11)
\r
221 usartPrsRxCh8 = USART_INPUT_RXPRSSEL_PRSCH8, /**< PRSCH8 selected as USART_INPUT */
\r
222 usartPrsRxCh9 = USART_INPUT_RXPRSSEL_PRSCH9, /**< PRSCH9 selected as USART_INPUT */
\r
223 usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10, /**< PRSCH10 selected as USART_INPUT */
\r
224 usartPrsRxCh11 = USART_INPUT_RXPRSSEL_PRSCH11 /**< PRSCH11 selected as USART_INPUT */
\r
226 } USART_PrsRxCh_TypeDef;
\r
229 /** USART PRS Transmit Trigger Channels */
\r
232 usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
\r
233 usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
\r
234 usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
\r
235 usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */
\r
237 #if defined(USART_TRIGCTRL_TSEL_PRSCH7)
\r
238 usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */
\r
239 usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */
\r
240 usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */
\r
241 usartPrsTriggerCh7 = USART_TRIGCTRL_TSEL_PRSCH7, /**< PRSCH0 selected as USART Trigger */
\r
243 } USART_PrsTriggerCh_TypeDef;
\r
245 /*******************************************************************************
\r
246 ******************************* STRUCTS ***********************************
\r
247 ******************************************************************************/
\r
249 /** Asynchronous mode init structure. */
\r
252 /** Specifies whether TX and/or RX shall be enabled when init completed. */
\r
253 USART_Enable_TypeDef enable;
\r
256 * USART/UART reference clock assumed when configuring baudrate setup. Set
\r
257 * it to 0 if currently configurated reference clock shall be used.
\r
261 /** Desired baudrate. */
\r
264 /** Oversampling used. */
\r
265 USART_OVS_TypeDef oversampling;
\r
267 /** Number of databits in frame. Notice that UART modules only support 8 or
\r
269 USART_Databits_TypeDef databits;
\r
271 /** Parity mode to use. */
\r
272 USART_Parity_TypeDef parity;
\r
274 /** Number of stopbits to use. */
\r
275 USART_Stopbits_TypeDef stopbits;
\r
277 #if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
\r
278 /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
\r
281 /** Enable USART Rx via PRS. */
\r
284 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
\r
285 USART_PrsRxCh_TypeDef prsRxCh;
\r
287 #if defined(_USART_TIMING_CSHOLD_MASK)
\r
288 /** Auto CS enabling */
\r
290 /** Auto CS hold time in baud cycles */
\r
291 uint8_t autoCsHold;
\r
292 /** Auto CS setup time in baud cycles */
\r
293 uint8_t autoCsSetup;
\r
295 } USART_InitAsync_TypeDef;
\r
297 /** USART PRS trigger enable */
\r
300 #if defined(USART_TRIGCTRL_AUTOTXTEN)
\r
301 /** Enable AUTOTX */
\r
302 bool autoTxTriggerEnable;
\r
304 /** Trigger receive via PRS channel */
\r
305 bool rxTriggerEnable;
\r
306 /** Trigger transmit via PRS channel */
\r
307 bool txTriggerEnable;
\r
308 /** PRS channel to be used to trigger auto transmission */
\r
309 USART_PrsTriggerCh_TypeDef prsTriggerChannel;
\r
310 } USART_PrsTriggerInit_TypeDef;
\r
312 /** Default config for USART async init structure. */
\r
313 #if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
\r
314 #define USART_INITASYNC_DEFAULT \
\r
316 usartEnable, /* Enable RX/TX when init completed. */ \
\r
317 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
318 115200, /* 115200 bits/s. */ \
\r
319 usartOVS16, /* 16x oversampling. */ \
\r
320 usartDatabits8, /* 8 databits. */ \
\r
321 usartNoParity, /* No parity. */ \
\r
322 usartStopbits1, /* 1 stopbit. */ \
\r
323 false, /* Do not disable majority vote. */ \
\r
324 false, /* Not USART PRS input mode. */ \
\r
325 usartPrsRxCh0, /* PRS channel 0. */ \
\r
326 false, /* Auto CS functionality enable/disable switch */ \
\r
327 0, /* Auto CS Hold cycles */ \
\r
328 0 /* Auto CS Setup cycles */ \
\r
330 #elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
\r
331 #define USART_INITASYNC_DEFAULT \
\r
333 usartEnable, /* Enable RX/TX when init completed. */ \
\r
334 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
335 115200, /* 115200 bits/s. */ \
\r
336 usartOVS16, /* 16x oversampling. */ \
\r
337 usartDatabits8, /* 8 databits. */ \
\r
338 usartNoParity, /* No parity. */ \
\r
339 usartStopbits1, /* 1 stopbit. */ \
\r
340 false, /* Do not disable majority vote. */ \
\r
341 false, /* Not USART PRS input mode. */ \
\r
342 usartPrsRxCh0 /* PRS channel 0. */ \
\r
345 #define USART_INITASYNC_DEFAULT \
\r
347 usartEnable, /* Enable RX/TX when init completed. */ \
\r
348 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
349 115200, /* 115200 bits/s. */ \
\r
350 usartOVS16, /* 16x oversampling. */ \
\r
351 usartDatabits8, /* 8 databits. */ \
\r
352 usartNoParity, /* No parity. */ \
\r
353 usartStopbits1 /* 1 stopbit. */ \
\r
357 /** Default config for USART PRS triggering structure. */
\r
358 #if defined(USART_TRIGCTRL_AUTOTXTEN)
\r
359 #define USART_INITPRSTRIGGER_DEFAULT \
\r
361 false, /* Do not enable autoTX triggering. */ \
\r
362 false, /* Do not enable receive triggering. */ \
\r
363 false, /* Do not enable transmit triggering. */ \
\r
364 usartPrsTriggerCh0 /* Set default channel to zero. */ \
\r
367 #define USART_INITPRSTRIGGER_DEFAULT \
\r
369 false, /* Do not enable receive triggering. */ \
\r
370 false, /* Do not enable transmit triggering. */ \
\r
371 usartPrsTriggerCh0 /* Set default channel to zero. */ \
\r
375 /** Synchronous mode init structure. */
\r
378 /** Specifies whether TX and/or RX shall be enabled when init completed. */
\r
379 USART_Enable_TypeDef enable;
\r
382 * USART/UART reference clock assumed when configuring baudrate setup. Set
\r
383 * it to 0 if currently configurated reference clock shall be used.
\r
387 /** Desired baudrate. */
\r
390 /** Number of databits in frame. */
\r
391 USART_Databits_TypeDef databits;
\r
393 /** Select if to operate in master or slave mode. */
\r
396 /** Select if to send most or least significant bit first. */
\r
399 /** Clock polarity/phase mode. */
\r
400 USART_ClockMode_TypeDef clockMode;
\r
402 #if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
\r
403 /** Enable USART Rx via PRS. */
\r
406 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
\r
407 USART_PrsRxCh_TypeDef prsRxCh;
\r
409 /** Enable AUTOTX mode. Transmits as long as RX is not full.
\r
410 * If TX is empty, underflows are generated. */
\r
413 #if defined(_USART_TIMING_CSHOLD_MASK)
\r
414 /** Auto CS enabling */
\r
416 /** Auto CS hold time in baud cycles */
\r
417 uint8_t autoCsHold;
\r
418 /** Auto CS setup time in baud cycles */
\r
419 uint8_t autoCsSetup;
\r
421 } USART_InitSync_TypeDef;
\r
423 /** Default config for USART sync init structure. */
\r
424 #if defined(_USART_TIMING_CSHOLD_MASK)
\r
425 #define USART_INITSYNC_DEFAULT \
\r
427 usartEnable, /* Enable RX/TX when init completed. */ \
\r
428 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
429 1000000, /* 1 Mbits/s. */ \
\r
430 usartDatabits8, /* 8 databits. */ \
\r
431 true, /* Master mode. */ \
\r
432 false, /* Send least significant bit first. */ \
\r
433 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
\r
434 false, /* Not USART PRS input mode. */ \
\r
435 usartPrsRxCh0, /* PRS channel 0. */ \
\r
436 false, /* No AUTOTX mode. */ \
\r
437 false, /* No AUTOCS mode */ \
\r
438 0, /* Auto CS Hold cycles */ \
\r
439 0 /* Auto CS Setup cycles */ \
\r
441 #elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
\r
442 #define USART_INITSYNC_DEFAULT \
\r
444 usartEnable, /* Enable RX/TX when init completed. */ \
\r
445 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
446 1000000, /* 1 Mbits/s. */ \
\r
447 usartDatabits8, /* 8 databits. */ \
\r
448 true, /* Master mode. */ \
\r
449 false, /* Send least significant bit first. */ \
\r
450 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
\r
451 false, /* Not USART PRS input mode. */ \
\r
452 usartPrsRxCh0, /* PRS channel 0. */ \
\r
453 false /* No AUTOTX mode. */ \
\r
456 #define USART_INITSYNC_DEFAULT \
\r
458 usartEnable, /* Enable RX/TX when init completed. */ \
\r
459 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
460 1000000, /* 1 Mbits/s. */ \
\r
461 usartDatabits8, /* 8 databits. */ \
\r
462 true, /* Master mode. */ \
\r
463 false, /* Send least significant bit first. */ \
\r
464 usartClockMode0 /* Clock idle low, sample on rising edge. */ \
\r
469 /** IrDA mode init structure. Inherited from asynchronous mode init structure */
\r
472 /** General Async initialization structure. */
\r
473 USART_InitAsync_TypeDef async;
\r
475 /** Set to invert Rx signal before IrDA demodulator. */
\r
478 /** Set to enable filter on IrDA demodulator. */
\r
481 /** Configure the pulse width generated by the IrDA modulator as a fraction
\r
482 * of the configured USART bit period. */
\r
483 USART_IrDAPw_Typedef irPw;
\r
485 /** Enable the PRS channel selected by irPrsSel as input to IrDA module
\r
486 * instead of TX. */
\r
489 /** A PRS can be used as input to the pulse modulator instead of TX.
\r
490 * This value selects the channel to use. */
\r
491 USART_IrDAPrsSel_Typedef irPrsSel;
\r
492 } USART_InitIrDA_TypeDef;
\r
495 /** Default config for IrDA mode init structure. */
\r
496 #define USART_INITIRDA_DEFAULT \
\r
499 usartEnable, /* Enable RX/TX when init completed. */ \
\r
500 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
501 115200, /* 115200 bits/s. */ \
\r
502 usartOVS16, /* 16x oversampling. */ \
\r
503 usartDatabits8, /* 8 databits. */ \
\r
504 usartEvenParity, /* Even parity. */ \
\r
505 usartStopbits1 /* 1 stopbit. */ \
\r
507 false, /* Rx invert disabled. */ \
\r
508 false, /* Filtering disabled. */ \
\r
509 usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
\r
510 false, /* Routing to PRS is disabled. */ \
\r
511 usartIrDAPrsCh0 /* PRS channel 0. */ \
\r
515 #if defined(_USART_I2SCTRL_MASK)
\r
516 /** I2S mode init structure. Inherited from synchronous mode init structure */
\r
519 /** General Sync initialization structure. */
\r
520 USART_InitSync_TypeDef sync;
\r
523 USART_I2sFormat_TypeDef format;
\r
525 /** Delay on I2S data. Set to add a one-cycle delay between a transition
\r
526 * on the word-clock and the start of the I2S word.
\r
527 * Should be set for standard I2S format. */
\r
530 /** Separate DMA Request For Left/Right Data. */
\r
533 /** Justification of I2S data within the frame */
\r
534 USART_I2sJustify_TypeDef justify;
\r
536 /** Stero or Mono, set to true for mono. */
\r
538 } USART_InitI2s_TypeDef;
\r
541 /** Default config for I2S mode init structure. */
\r
542 #define USART_INITI2S_DEFAULT \
\r
545 usartEnableTx, /* Enable TX when init completed. */ \
\r
546 0, /* Use current configured reference clock for configuring baudrate. */ \
\r
547 1000000, /* Baudrate 1M bits/s. */ \
\r
548 usartDatabits16, /* 16 databits. */ \
\r
549 true, /* Operate as I2S master. */ \
\r
550 true, /* Most significant bit first. */ \
\r
551 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
\r
552 false, /* Don't enable USARTRx via PRS. */ \
\r
553 usartPrsRxCh0, /* PRS channel selection (dummy). */ \
\r
554 false /* Disable AUTOTX mode. */ \
\r
556 usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
\r
557 true, /* Delay on I2S data. */ \
\r
558 false, /* No DMA split. */ \
\r
559 usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
\r
560 false /* Stereo mode. */ \
\r
564 /*******************************************************************************
\r
565 ***************************** PROTOTYPES **********************************
\r
566 ******************************************************************************/
\r
568 void USART_BaudrateAsyncSet(USART_TypeDef *usart,
\r
571 USART_OVS_TypeDef ovs);
\r
572 uint32_t USART_BaudrateCalc(uint32_t refFreq,
\r
575 USART_OVS_TypeDef ovs);
\r
576 uint32_t USART_BaudrateGet(USART_TypeDef *usart);
\r
577 void USART_BaudrateSyncSet(USART_TypeDef *usart,
\r
579 uint32_t baudrate);
\r
580 void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable);
\r
582 void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
\r
583 void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
\r
584 #if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))
\r
585 void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
\r
588 #if defined(_USART_I2SCTRL_MASK)
\r
589 void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
\r
591 void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
\r
594 /***************************************************************************//**
\r
596 * Clear one or more pending USART interrupts.
\r
599 * Pointer to USART/UART peripheral register block.
\r
602 * Pending USART/UART interrupt source(s) to clear. Use one or more valid
\r
603 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
\r
604 ******************************************************************************/
\r
605 __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
\r
607 usart->IFC = flags;
\r
611 /***************************************************************************//**
\r
613 * Disable one or more USART interrupts.
\r
616 * Pointer to USART/UART peripheral register block.
\r
619 * USART/UART interrupt source(s) to disable. Use one or more valid
\r
620 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
\r
621 ******************************************************************************/
\r
622 __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
\r
624 usart->IEN &= ~flags;
\r
628 /***************************************************************************//**
\r
630 * Enable one or more USART interrupts.
\r
633 * Depending on the use, a pending interrupt may already be set prior to
\r
634 * enabling the interrupt. Consider using USART_IntClear() prior to enabling
\r
635 * if such a pending interrupt should be ignored.
\r
638 * Pointer to USART/UART peripheral register block.
\r
641 * USART/UART interrupt source(s) to enable. Use one or more valid
\r
642 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
\r
643 ******************************************************************************/
\r
644 __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
\r
646 usart->IEN |= flags;
\r
650 /***************************************************************************//**
\r
652 * Get pending USART interrupt flags.
\r
655 * The event bits are not cleared by the use of this function.
\r
658 * Pointer to USART/UART peripheral register block.
\r
661 * USART/UART interrupt source(s) pending. Returns one or more valid
\r
662 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
\r
663 ******************************************************************************/
\r
664 __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
\r
670 /***************************************************************************//**
\r
672 * Get enabled and pending USART interrupt flags.
\r
673 * Useful for handling more interrupt sources in the same interrupt handler.
\r
676 * Pointer to USART/UART peripheral register block.
\r
679 * Interrupt flags are not cleared by the use of this function.
\r
682 * Pending and enabled USART interrupt sources.
\r
683 * The return value is the bitwise AND combination of
\r
684 * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn
\r
685 * register (USARTx_IEN_nnn) and
\r
686 * - the OR combination of valid interrupt flags of the USART module
\r
688 ******************************************************************************/
\r
689 __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
\r
693 /* Store USARTx->IEN in temporary variable in order to define explicit order
\r
694 * of volatile accesses. */
\r
697 /* Bitwise AND of pending and enabled interrupts */
\r
698 return usart->IF & ien;
\r
702 /***************************************************************************//**
\r
704 * Set one or more pending USART interrupts from SW.
\r
707 * Pointer to USART/UART peripheral register block.
\r
710 * USART/UART interrupt source(s) to set to pending. Use one or more valid
\r
711 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
\r
712 ******************************************************************************/
\r
713 __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
\r
715 usart->IFS = flags;
\r
719 /***************************************************************************//**
\r
721 * Get USART STATUS register.
\r
724 * Pointer to USART/UART peripheral register block.
\r
727 * STATUS register value.
\r
729 ******************************************************************************/
\r
730 __STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
\r
732 return usart->STATUS;
\r
735 void USART_Reset(USART_TypeDef *usart);
\r
736 uint8_t USART_Rx(USART_TypeDef *usart);
\r
737 uint16_t USART_RxDouble(USART_TypeDef *usart);
\r
738 uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
\r
739 uint16_t USART_RxExt(USART_TypeDef *usart);
\r
742 /***************************************************************************//**
\r
744 * Receive one 4-8 bit frame, (or part of 10-16 bit frame).
\r
747 * This function is used to quickly receive one 4-8 bits frame by reading the
\r
748 * RXDATA register directly, without checking the STATUS register for the
\r
749 * RXDATAV flag. This can be useful from the RXDATAV interrupt handler,
\r
750 * i.e. waiting is superfluous, in order to quickly read the received data.
\r
751 * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames.
\r
754 * Since this function does not check whether the RXDATA register actually
\r
755 * holds valid data, it should only be used in situations when it is certain
\r
756 * that there is valid data, ensured by some external program routine, e.g.
\r
757 * like when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a
\r
758 * better choice if the validity of the RXDATA register is not certain.
\r
761 * Notice that possible parity/stop bits in asynchronous mode are not
\r
762 * considered part of specified frame bit length.
\r
765 * Pointer to USART/UART peripheral register block.
\r
769 ******************************************************************************/
\r
770 __STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
\r
772 return (uint8_t)usart->RXDATA;
\r
776 /***************************************************************************//**
\r
778 * Receive two 4-8 bit frames, or one 10-16 bit frame.
\r
781 * This function is used to quickly receive one 10-16 bits frame or two 4-8
\r
782 * bit frames by reading the RXDOUBLE register directly, without checking
\r
783 * the STATUS register for the RXDATAV flag. This can be useful from the
\r
784 * RXDATAV interrupt handler, i.e. waiting is superfluous, in order to
\r
785 * quickly read the received data.
\r
786 * This function is normally used to receive one frame when operating with
\r
787 * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet()
\r
788 * for reception of two 9 bit frames.
\r
791 * Since this function does not check whether the RXDOUBLE register actually
\r
792 * holds valid data, it should only be used in situations when it is certain
\r
793 * that there is valid data, ensured by some external program routine, e.g.
\r
794 * like when handling an RXDATAV interrupt. The @ref USART_RxDouble() is
\r
795 * normally a better choice if the validity of the RXDOUBLE register is not
\r
799 * Notice that possible parity/stop bits in asynchronous mode are not
\r
800 * considered part of specified frame bit length.
\r
803 * Pointer to USART/UART peripheral register block.
\r
807 ******************************************************************************/
\r
808 __STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
\r
810 return (uint16_t)usart->RXDOUBLE;
\r
814 /***************************************************************************//**
\r
816 * Receive two 4-9 bit frames, or one 10-16 bit frame with extended
\r
820 * This function is used to quickly receive one 10-16 bits frame or two 4-9
\r
821 * bit frames by reading the RXDOUBLEX register directly, without checking
\r
822 * the STATUS register for the RXDATAV flag. This can be useful from the
\r
823 * RXDATAV interrupt handler, i.e. waiting is superfluous, in order to
\r
824 * quickly read the received data.
\r
827 * Since this function does not check whether the RXDOUBLEX register actually
\r
828 * holds valid data, it should only be used in situations when it is certain
\r
829 * that there is valid data, ensured by some external program routine, e.g.
\r
830 * like when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is
\r
831 * normally a better choice if the validity of the RXDOUBLEX register is not
\r
835 * Notice that possible parity/stop bits in asynchronous mode are not
\r
836 * considered part of specified frame bit length.
\r
839 * Pointer to USART/UART peripheral register block.
\r
843 ******************************************************************************/
\r
844 __STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
\r
846 return usart->RXDOUBLEX;
\r
850 /***************************************************************************//**
\r
852 * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
\r
856 * This function is used to quickly receive one 4-9 bit frame, (or part of
\r
857 * 10-16 bit frame) with extended information by reading the RXDATAX register
\r
858 * directly, without checking the STATUS register for the RXDATAV flag. This
\r
859 * can be useful from the RXDATAV interrupt handler, i.e. waiting is
\r
860 * superfluous, in order to quickly read the received data.
\r
863 * Since this function does not check whether the RXDATAX register actually
\r
864 * holds valid data, it should only be used in situations when it is certain
\r
865 * that there is valid data, ensured by some external program routine, e.g.
\r
866 * like when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally
\r
867 * a better choice if the validity of the RXDATAX register is not certain.
\r
870 * Notice that possible parity/stop bits in asynchronous mode are not
\r
871 * considered part of specified frame bit length.
\r
874 * Pointer to USART/UART peripheral register block.
\r
878 ******************************************************************************/
\r
879 __STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
\r
881 return (uint16_t)usart->RXDATAX;
\r
884 uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
\r
885 void USART_Tx(USART_TypeDef *usart, uint8_t data);
\r
886 void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
\r
887 void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
\r
888 void USART_TxExt(USART_TypeDef *usart, uint16_t data);
\r
891 /** @} (end addtogroup USART) */
\r
892 /** @} (end addtogroup EM_Library) */
\r
898 #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
\r
899 #endif /* __SILICON_LABS_EM_USART_H__ */
\r
projects / freertos / blob