2 * @brief UART/USART Registers and control functions
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5 * Copyright(C) NXP Semiconductors, 2012
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6 * All rights reserved.
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * LPC products. This software is supplied "AS IS" without any warranties of
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12 * any kind, and NXP Semiconductors and its licensor disclaim any and
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13 * all warranties, express or implied, including all implied warranties of
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14 * merchantability, fitness for a particular purpose and non-infringement of
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15 * intellectual property rights. NXP Semiconductors assumes no responsibility
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16 * or liability for the use of the software, conveys no license or rights under any
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17 * patent, copyright, mask work right, or any other intellectual property rights in
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18 * or to any products. NXP Semiconductors reserves the right to make changes
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19 * in the software without notification. NXP Semiconductors also makes no
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20 * representation or warranty that such application will be suitable for the
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21 * specified use without further testing or modification.
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24 * Permission to use, copy, modify, and distribute this software and its
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25 * documentation is hereby granted, under NXP Semiconductors' and its
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26 * licensor's relevant copyrights in the software, without fee, provided that it
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27 * is used in conjunction with NXP Semiconductors microcontrollers. This
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28 * copyright, permission, and disclaimer notice must appear in all copies of
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32 #ifndef __USART_001_H_
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33 #define __USART_001_H_
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35 #include "sys_config.h"
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42 /** @defgroup IP_USART_001 IP: USART register block and driver
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43 * @ingroup IP_Drivers
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48 * @brief USART register block structure
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50 typedef struct { /*!< USARTn Structure */
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53 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
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54 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
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55 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
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59 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
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60 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
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64 __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
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65 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
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68 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
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69 __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
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70 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
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71 __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
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72 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
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73 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
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74 __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
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75 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
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76 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
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77 __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
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78 uint32_t RESERVED0[3];
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79 __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
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80 __I uint32_t RESERVED1[1];
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81 __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
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82 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
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83 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
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84 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
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86 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
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87 __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
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90 #if !defined CHIP_LPC11XX
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91 __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
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95 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) /*!< UART time-out definitions in case of using Read/Write function with Blocking Flag mode */
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97 #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
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99 /* --------------------- BIT DEFINITIONS -------------------------------------- */
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101 * @brief Macro defines for UARTn Receiver Buffer Register
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103 #define UART_RBR_MASKBIT ((uint8_t) 0xFF) /*!< UART Received Buffer mask bit (8 bits) */
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106 * @brief Macro defines for UARTn Transmit Holding Register
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108 #define UART_THR_MASKBIT ((uint8_t) 0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
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111 * @brief Macro defines for UARTn Divisor Latch LSB register
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113 #define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading least significant halfs of divisors */
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114 #define UART_DLL_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch LSB bit mask */
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117 * @brief Macro defines for UARTn Divisor Latch MSB register
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119 #define UART_DLM_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch MSB bit mask */
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120 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading most significant halfs of divisors */
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123 * @brief Macro defines for UART interrupt enable register
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125 #define UART_IER_RBRINT_EN ((uint32_t) (1 << 0)) /*!< RBR Interrupt enable*/
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126 #define UART_IER_THREINT_EN ((uint32_t) (1 << 1)) /*!< THR Interrupt enable*/
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127 #define UART_IER_RLSINT_EN ((uint32_t) (1 << 2)) /*!< RX line status interrupt enable*/
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128 #define UART_IER_MSINT_EN ((uint32_t) (1 << 3)) /*!< Modem status interrupt enable */
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129 #define UART_IER_CTSINT_EN ((uint32_t) (1 << 7)) /*!< CTS1 signal transition interrupt enable */
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130 #define UART_IER_ABEOINT_EN ((uint32_t) (1 << 8)) /*!< Enables the end of auto-baud interrupt */
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131 #define UART_IER_ABTOINT_EN ((uint32_t) (1 << 9)) /*!< Enables the auto-baud time-out interrupt */
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132 #define UART_IER_BITMASK ((uint32_t) (0x307)) /*!< UART interrupt enable register bit mask */
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133 #define UART1_IER_BITMASK ((uint32_t) (0x38F)) /*!< UART1 interrupt enable register bit mask */
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136 * @brief Macro defines for UART interrupt identification register
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138 #define UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0)) /*!<Interrupt Status - Active low */
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139 #define UART_IIR_INTID_RLS ((uint32_t) (3 << 1)) /*!<Interrupt identification: Receive line status*/
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140 #define UART_IIR_INTID_RDA ((uint32_t) (2 << 1)) /*!<Interrupt identification: Receive data available*/
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141 #define UART_IIR_INTID_CTI ((uint32_t) (6 << 1)) /*!<Interrupt identification: Character time-out indicator*/
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142 #define UART_IIR_INTID_THRE ((uint32_t) (1 << 1)) /*!<Interrupt identification: THRE interrupt*/
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143 #define UART_IIR_INTID_MODEM ((uint32_t) (0 << 1)) /*!<Interrupt identification: Modem interrupt*/
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144 #define UART_IIR_INTID_MASK ((uint32_t) (7 << 1)) /*!<Interrupt identification: Interrupt ID mask */
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145 #define UART_IIR_FIFO_EN ((uint32_t) (3 << 6)) /*!<These bits are equivalent to UnFCR[0] */
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146 #define UART_IIR_ABEO_INT ((uint32_t) (1 << 8)) /*!< End of auto-baud interrupt */
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147 #define UART_IIR_ABTO_INT ((uint32_t) (1 << 9)) /*!< Auto-baud time-out interrupt */
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148 #define UART_IIR_BITMASK ((uint32_t) (0x3CF)) /*!< UART interrupt identification register bit mask */
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151 * @brief Macro defines for UART FIFO control register
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153 #define UART_FCR_FIFO_EN ((uint8_t) (1 << 0)) /*!< UART FIFO enable */
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154 #define UART_FCR_RX_RS ((uint8_t) (1 << 1)) /*!< UART FIFO RX reset */
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155 #define UART_FCR_TX_RS ((uint8_t) (1 << 2)) /*!< UART FIFO TX reset */
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156 #define UART_FCR_DMAMODE_SEL ((uint8_t) (1 << 3)) /*!< UART DMA mode selection */
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157 #define UART_FCR_TRG_LEV0 ((uint8_t) (0)) /*!< UART FIFO trigger level 0: 1 character */
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158 #define UART_FCR_TRG_LEV1 ((uint8_t) (1 << 6)) /*!< UART FIFO trigger level 1: 4 character */
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159 #define UART_FCR_TRG_LEV2 ((uint8_t) (2 << 6)) /*!< UART FIFO trigger level 2: 8 character */
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160 #define UART_FCR_TRG_LEV3 ((uint8_t) (3 << 6)) /*!< UART FIFO trigger level 3: 14 character */
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161 #define UART_FCR_BITMASK ((uint8_t) (0xCF)) /*!< UART FIFO control bit mask */
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162 #define UART_TX_FIFO_SIZE (16)
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165 * @brief Macro defines for UART line control register
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167 #define UART_LCR_WLEN5 ((uint8_t) (0)) /*!< UART 5 bit data mode */
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168 #define UART_LCR_WLEN6 ((uint8_t) (1 << 0)) /*!< UART 6 bit data mode */
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169 #define UART_LCR_WLEN7 ((uint8_t) (2 << 0)) /*!< UART 7 bit data mode */
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170 #define UART_LCR_WLEN8 ((uint8_t) (3 << 0)) /*!< UART 8 bit data mode */
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171 #define UART_LCR_SBS_1BIT ((uint8_t) (0 << 2)) /*!< UART One Stop Bit Select */
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172 #define UART_LCR_SBS_2BIT ((uint8_t) (1 << 2)) /*!< UART Two Stop Bits Select */
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173 #define UART_LCR_PARITY_EN ((uint8_t) (1 << 3)) /*!< UART Parity Enable */
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174 #define UART_LCR_PARITY_DIS ((uint8_t) (0 << 3)) /*!< UART Parity Disable */
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175 #define UART_LCR_PARITY_ODD ((uint8_t) (0)) /*!< UART Odd Parity Select */
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176 #define UART_LCR_PARITY_EVEN ((uint8_t) (1 << 4)) /*!< UART Even Parity Select */
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177 #define UART_LCR_PARITY_F_1 ((uint8_t) (2 << 4)) /*!< UART force 1 stick parity */
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178 #define UART_LCR_PARITY_F_0 ((uint8_t) (3 << 4)) /*!< UART force 0 stick parity */
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179 #define UART_LCR_BREAK_EN ((uint8_t) (1 << 6)) /*!< UART Transmission Break enable */
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180 #define UART_LCR_DLAB_EN ((uint8_t) (1 << 7)) /*!< UART Divisor Latches Access bit enable */
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181 #define UART_LCR_BITMASK ((uint8_t) (0xFF)) /*!< UART line control bit mask */
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184 * @brief Macro defines for UART Modem control register
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186 #define UART_MCR_DTR_CTRL ((uint8_t) (1 << 0)) /*!< Source for modem output pin DTR */
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187 #define UART_MCR_RTS_CTRL ((uint8_t) (1 << 1)) /*!< Source for modem output pin RTS */
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188 #define UART_MCR_LOOPB_EN ((uint8_t) (1 << 4)) /*!< Loop back mode select */
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189 #define UART_MCR_AUTO_RTS_EN ((uint8_t) (1 << 6)) /*!< Enable Auto RTS flow-control */
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190 #define UART_MCR_AUTO_CTS_EN ((uint8_t) (1 << 7)) /*!< Enable Auto CTS flow-control */
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191 #define UART_MCR_BITMASK ((uint8_t) (0x0F3)) /*!< UART1 bit mask value */
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194 * @brief Macro defines for UART line status register
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196 #define UART_LSR_RDR ((uint8_t) (1 << 0)) /*!<Line status register: Receive data ready*/
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197 #define UART_LSR_OE ((uint8_t) (1 << 1)) /*!<Line status register: Overrun error*/
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198 #define UART_LSR_PE ((uint8_t) (1 << 2)) /*!<Line status register: Parity error*/
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199 #define UART_LSR_FE ((uint8_t) (1 << 3)) /*!<Line status register: Framing error*/
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200 #define UART_LSR_BI ((uint8_t) (1 << 4)) /*!<Line status register: Break interrupt*/
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201 #define UART_LSR_THRE ((uint8_t) (1 << 5)) /*!<Line status register: Transmit holding register empty*/
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202 #define UART_LSR_TEMT ((uint8_t) (1 << 6)) /*!<Line status register: Transmitter empty*/
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203 #define UART_LSR_RXFE ((uint8_t) (1 << 7)) /*!<Error in RX FIFO*/
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204 #define UART_LSR_BITMASK ((uint8_t) (0xFF)) /*!<UART Line status bit mask */
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207 * @brief Macro defines for UART Modem status register
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209 #define UART_MSR_DELTA_CTS ((uint8_t) (1 << 0)) /*!< Set upon state change of input CTS */
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210 #define UART_MSR_DELTA_DSR ((uint8_t) (1 << 1)) /*!< Set upon state change of input DSR */
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211 #define UART_MSR_LO2HI_RI ((uint8_t) (1 << 2)) /*!< Set upon low to high transition of input RI */
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212 #define UART_MSR_DELTA_DCD ((uint8_t) (1 << 3)) /*!< Set upon state change of input DCD */
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213 #define UART_MSR_CTS ((uint8_t) (1 << 4)) /*!< Clear To Send State */
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214 #define UART_MSR_DSR ((uint8_t) (1 << 5)) /*!< Data Set Ready State */
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215 #define UART_MSR_RI ((uint8_t) (1 << 6)) /*!< Ring Indicator State */
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216 #define UART_MSR_DCD ((uint8_t) (1 << 7)) /*!< Data Carrier Detect State */
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217 #define UART_MSR_BITMASK ((uint8_t) (0xFF)) /*!< MSR register bit-mask value */
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220 * @brief Macro defines for UART Scratch Pad register
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222 #define UART_SCR_BIMASK ((uint8_t) (0xFF)) /*!< UART Scratch Pad bit mask */
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225 * @brief Macro defines for UART Auto baudrate control register
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227 #define UART_ACR_START ((uint32_t) (1 << 0)) /*!< UART Auto-baud start */
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228 #define UART_ACR_MODE ((uint32_t) (1 << 1)) /*!< UART Auto baudrate Mode 1 */
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229 #define UART_ACR_AUTO_RESTART ((uint32_t) (1 << 2)) /*!< UART Auto baudrate restart */
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230 #define UART_ACR_ABEOINT_CLR ((uint32_t) (1 << 8)) /*!< UART End of auto-baud interrupt clear */
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231 #define UART_ACR_ABTOINT_CLR ((uint32_t) (1 << 9)) /*!< UART Auto-baud time-out interrupt clear */
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232 #define UART_ACR_BITMASK ((uint32_t) (0x307)) /*!< UART Auto Baudrate register bit mask */
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235 * @brief Macro defines for UART IrDA control register
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237 #define UART_ICR_IRDAEN ((uint32_t) (1 << 0)) /*!< IrDA mode enable */
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238 #define UART_ICR_IRDAINV ((uint32_t) (1 << 1)) /*!< IrDA serial input inverted */
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239 #define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2)) /*!< IrDA fixed pulse width mode */
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240 #define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3)) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
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241 #define UART_ICR_BITMASK ((uint32_t) (0x3F)) /*!< UART IRDA bit mask */
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244 * @brief Macro defines for UART half duplex register
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246 #define UART_HDEN_HDEN ((uint32_t) (1 << 0)) /*!< enable half-duplex mode*/
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249 * @brief Macro defines for UART smart card interface control register
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251 #define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0)) /*!< enable asynchronous half-duplex smart card interface*/
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252 #define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1)) /*!< NACK response is inhibited*/
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253 #define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2)) /*!< ISO7816-3 protocol T1 is selected*/
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254 #define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5)) /*!< number of retransmission*/
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255 #define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< Extra guard time*/
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258 * @brief Macro defines for UART synchronous control register
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260 #define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0)) /*!< enable synchronous mode*/
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261 #define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1)) /*!< synchronous master mode*/
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262 #define UART_SYNCCTRL_FES ((uint32_t) (1 << 2)) /*!< sample on falling edge*/
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263 #define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3)) /*!< to be defined*/
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264 #define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4)) /*!< continuous running clock enable (master mode only)*/
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265 #define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5)) /*!< do not send start/stop bit*/
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266 #define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6)) /*!< stop continuous clock*/
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269 * @brief Macro defines for UART Fractional divider register
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271 #define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F)) /*!< Baud-rate generation pre-scaler divisor */
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272 #define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0)) /*!< Baud-rate pre-scaler multiplier value */
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273 #define UART_FDR_BITMASK ((uint32_t) (0xFF)) /*!< UART Fractional Divider register bit mask */
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276 * @brief Macro defines for UART Tx Enable register
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278 #define UART_TER1_TXEN ((uint8_t) (1 << 7)) /*!< Transmit enable bit */
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279 #define UART_TER1_BITMASK ((uint8_t) (0x80)) /*!< UART Transmit Enable Register bit mask */
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280 #define UART_TER2_TXEN ((uint8_t) (1 << 0)) /*!< Transmit enable bit */
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281 #define UART_TER2_BITMASK ((uint8_t) (0x01)) /*!< UART Transmit Enable Register bit mask */
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284 * @brief Macro defines for UART1 RS485 Control register
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286 #define UART_RS485CTRL_NMM_EN ((uint32_t) (1 << 0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
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287 #define UART_RS485CTRL_RX_DIS ((uint32_t) (1 << 1)) /*!< The receiver is disabled */
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288 #define UART_RS485CTRL_AADEN ((uint32_t) (1 << 2)) /*!< Auto Address Detect (AAD) is enabled */
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289 #define UART_RS485CTRL_SEL_DTR ((uint32_t) (1 << 3)) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
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290 used for direction control */
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291 #define UART_RS485CTRL_DCTRL_EN ((uint32_t) (1 << 4)) /*!< Enable Auto Direction Control */
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292 #define UART_RS485CTRL_OINV_1 ((uint32_t) (1 << 5)) /*!< This bit reverses the polarity of the direction
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293 control signal on the RTS (or DTR) pin. The direction control pin
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294 will be driven to logic "1" when the transmitter has data to be sent */
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295 #define UART_RS485CTRL_BITMASK ((uint32_t) (0x3F)) /*!< RS485 control bit-mask value */
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298 * @brief Macro defines for UART1 RS-485 Address Match register
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300 #define UART_RS485ADRMATCH_BITMASK ((uint8_t) (0xFF)) /*!< Bit mask value */
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303 * @brief Macro defines for UART1 RS-485 Delay value register
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305 #define UART_RS485DLY_BITMASK ((uint8_t) (0xFF)) /*!< Bit mask value */
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308 * @brief Macro defines for UART FIFO Level register
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310 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t) (n & 0x0F)) /*!< Reflects the current level of the UART receiver FIFO */
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311 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t) ((n >> 8) & 0x0F)) /*!< Reflects the current level of the UART transmitter FIFO */
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312 #define UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F)) /*!< UART FIFO Level Register bit mask */
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315 * @brief Macro defines for Ring Buffer
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317 #define UART_RING_BUFSIZE 256 /*!< buffer size definition */
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318 #define __BUF_MASK (UART_RING_BUFSIZE - 1) /*!< Buf mask */
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319 #define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK)) /*!< Check buf is full or not */
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320 #define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK)) /*!< Check buf will be full in next receiving or not */
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321 #define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK)) /*!< Check buf is empty */
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322 #define __BUF_RESET(bufidx) (bufidx = 0) /*!< Reset buf */
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323 #define __BUF_INCR(bufidx) (bufidx = (bufidx + 1) & __BUF_MASK) /*!< Increase buf */
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326 * @brief UART Ring buffer structure
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329 __IO uint32_t tx_head; /*!< UART Tx ring buffer head index */
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330 __IO uint32_t tx_tail; /*!< UART Tx ring buffer tail index */
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331 __IO uint32_t rx_head; /*!< UART Rx ring buffer head index */
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332 __IO uint32_t rx_tail; /*!< UART Rx ring buffer tail index */
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333 __IO uint8_t tx[UART_RING_BUFSIZE]; /*!< UART Tx data ring buffer */
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334 __IO uint8_t rx[UART_RING_BUFSIZE]; /*!< UART Rx data ring buffer */
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335 } UART_RingBuffer_T;
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338 * @brief UART Line Status Type definition
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340 typedef enum IP_UART_LS {
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341 UART_LINESTAT_RDR = UART_LSR_RDR, /*!< Line status register: Receive data ready*/
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342 UART_LINESTAT_OE = UART_LSR_OE, /*!< Line status register: Overrun error*/
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343 UART_LINESTAT_PE = UART_LSR_PE, /*!< Line status register: Parity error*/
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344 UART_LINESTAT_FE = UART_LSR_FE, /*!< Line status register: Framing error*/
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345 UART_LINESTAT_BI = UART_LSR_BI, /*!< Line status register: Break interrupt*/
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346 UART_LINESTAT_THRE = UART_LSR_THRE, /*!< Line status register: Transmit holding register empty*/
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347 UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!< Line status register: Transmitter empty*/
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348 UART_LINESTAT_RXFE = UART_LSR_RXFE /*!< Error in RX FIFO*/
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352 * @brief UART Full modem - Signal states definition
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354 typedef enum IP_UART_SIGNAL_STATE {
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355 INACTIVE = 0, /*!< In-active state */
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356 ACTIVE = !INACTIVE /*!< Active state */
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357 } IP_UART_SIGNAL_STATE_T;
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360 * @brief UART modem status type definition
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362 typedef enum IP_UART_MODEM_STAT {
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363 UART_MODEM_STAT_DELTA_CTS = UART_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
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364 UART_MODEM_STAT_DELTA_DSR = UART_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
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365 UART_MODEM_STAT_LO2HI_RI = UART_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
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366 UART_MODEM_STAT_DELTA_DCD = UART_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
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367 UART_MODEM_STAT_CTS = UART_MSR_CTS, /*!< Clear To Send State */
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368 UART_MODEM_STAT_DSR = UART_MSR_DSR, /*!< Data Set Ready State */
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369 UART_MODEM_STAT_RI = UART_MSR_RI, /*!< Ring Indicator State */
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370 UART_MODEM_STAT_DCD = UART_MSR_DCD /*!< Data Carrier Detect State */
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371 } IP_UART_MODEM_STAT_T;
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374 * @brief Modem output pin type definition
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376 typedef enum IP_UART_MODEM_PIN {
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377 UART_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
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378 UART_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
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379 } IP_UART_MODEM_PIN_T;
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382 * @brief UART Modem mode type definition
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384 typedef enum IP_UART_MODEM_MODE {
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385 UART_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
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386 UART_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
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387 UART_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
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388 } IP_UART_MODEM_MODE_T;
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391 * @brief UART Interrupt Type definitions
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393 typedef enum IP_UART_INT {
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394 UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
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395 UART_INTCFG_THRE, /*!< THR Interrupt enable*/
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396 UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
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397 UART_INTCFG_MS, /*!< Modem status interrupt enable */
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398 UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable */
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399 UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
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400 UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
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404 * @brief UART Parity type definitions
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406 typedef enum IP_UART_PARITY {
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407 UART_PARITY_NONE = 0, /*!< No parity */
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408 UART_PARITY_ODD = (4 << 3), /*!< Odd parity */
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409 UART_PARITY_EVEN = (5 << 3), /*!< Even parity */
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410 UART_PARITY_SP_1 = (6 << 3), /*!< Forced "1" stick parity */
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411 UART_PARITY_SP_0 = (7 << 3) /*!< Forced "0" stick parity */
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412 } IP_UART_PARITY_T;
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415 * @brief FIFO Level type definitions
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417 typedef enum IP_UART_FITO_LEVEL {
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418 UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
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419 UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
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420 UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
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421 UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
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422 } IP_UART_FITO_LEVEL_T;
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425 * @brief UART Stop bit type definitions
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427 typedef enum IP_UART_STOPBIT {
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428 UART_STOPBIT_1 = 0, /*!< UART One Stop Bit Select */
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429 UART_STOPBIT_2 = (1 << 2) /*!< UART Two Stop Bits Select */
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430 } IP_UART_STOPBIT_T;
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433 * @brief UART Databit type definitions
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435 typedef enum IP_UART_DATABIT {
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436 UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
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437 UART_DATABIT_6, /*!< UART 6 bit data mode */
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438 UART_DATABIT_7, /*!< UART 7 bit data mode */
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439 UART_DATABIT_8 /*!< UART 8 bit data mode */
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440 } IP_UART_DATABIT_T;
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445 typedef enum IP_UART_ID {
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454 * @brief UART Interrupt Status
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456 typedef enum IP_UART_INT_STATUS {
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457 UART_INTSTS_ERROR = 1 << 0, /*!< UART Interrupt Error*/
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458 UART_INTSTS_RTS = 1 << 1, /*!< UART Interrupt status: Ready to Send*/
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459 UART_INTSTS_RTR = 1 << 2, /*!< UART Interrupt status: Ready to Receive*/
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460 UART_INTSTS_ABEO = UART_IIR_ABEO_INT, /*!< UART End of auto-baud interrupt */
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461 UART_INTSTS_ABTO = UART_IIR_ABTO_INT /*!< UART Auto-baud time-out interrupt */
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462 } IP_UART_INT_STATUS_T;
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465 * @brief UART Auto-baudrate mode type definition
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467 typedef enum IP_UART_AB_MODE {
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468 UART_AUTOBAUD_MODE0 = 0, /*!< UART Auto baudrate Mode 0 */
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469 UART_AUTOBAUD_MODE1, /*!< UART Auto baudrate Mode 1 */
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470 } IP_UART_AB_MODE_T;
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473 * @brief Auto Baudrate mode configuration type definition
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476 IP_UART_AB_MODE_T ABMode; /*!< Autobaudrate mode */
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477 FunctionalState AutoRestart; /*!< Auto Restart state */
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481 * @brief UART FIFO Configuration Structure definition
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484 FunctionalState FIFO_ResetRxBuf; /*!< Reset Rx FIFO command state , should be:
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485 - ENABLE: Reset Rx FIFO in UART
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486 - DISABLE: Do not reset Rx FIFO in UART
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488 FunctionalState FIFO_ResetTxBuf; /*!< Reset Tx FIFO command state , should be:
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489 - ENABLE: Reset Tx FIFO in UART
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490 - DISABLE: Do not reset Tx FIFO in UART
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492 FunctionalState FIFO_DMAMode; /*!< DMA mode, should be:
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493 - ENABLE: Enable DMA mode in UART
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494 - DISABLE: Disable DMA mode in UART
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496 IP_UART_FITO_LEVEL_T FIFO_Level; /*!< Rx FIFO trigger level, should be:
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497 - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
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498 - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
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499 - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
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500 - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
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505 * @brief Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct.
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506 * @param pUART : Pointer to selected UARTx peripheral
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507 * @param UARTPort : UART ID type
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510 void IP_UART_Init(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
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513 * @brief De-initializes the UARTx peripheral registers to their default reset values.
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514 * @param pUART : Pointer to selected UARTx peripheral
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515 * @param UARTPort : UART ID type
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518 void IP_UART_DeInit(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
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521 * @brief Determines best dividers to get a target clock rate
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522 * @param pUART : Pointer to selected UARTx peripheral
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523 * @param baudrate : Desired UART baud rate.
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524 * @param uClk : Current Uart Block Clock.
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525 * @return Error status, could be SUCCESS or ERROR
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527 Status IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);
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530 * @brief Configure data width, parity mode and stop bits
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531 * @param pUART : Pointer to selected UARTx peripheral
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532 * @param Databits : UART Data width, should be:
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533 * UART_DATABIT_5: UART 5 bit data mode
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534 * UART_DATABIT_6: UART 6 bit data mode
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535 * UART_DATABIT_7: UART 7 bit data mode
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536 * UART_DATABIT_8: UART 8 bit data mode
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537 * @param Parity : UART Parity mode, should be:
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538 * UART_PARITY_NONE: No parity
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539 * UART_PARITY_ODD: Odd parity
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540 * UART_PARITY_EVEN: Even parity
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541 * UART_PARITY_SP_1: Forced "1" stick parity
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542 * UART_PARITY_SP_0: Forced "0" stick parity
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543 * @param Stopbits : Number of stop bits, should be:
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544 * UART_STOPBIT_1: One Stop Bit Select
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545 * UART_STOPBIT_2: Two Stop Bits Select
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548 void IP_UART_ConfigData(IP_USART_001_T *pUART,
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549 IP_UART_DATABIT_T Databits,
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550 IP_UART_PARITY_T Parity,
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551 IP_UART_STOPBIT_T Stopbits);
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553 /* UART Send/Receive functions -------------------------------------------------*/
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555 * @brief Transmit a single data through UART peripheral
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556 * @param pUART : Pointer to selected UARTx peripheral
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557 * @param data : Data to transmit (must be 8-bit long)
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558 * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
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560 Status IP_UART_SendByte(IP_USART_001_T *pUART, uint8_t data);
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563 * @brief Receive a single data from UART peripheral
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564 * @param pUART : Pointer to selected UARTx peripheral
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565 * @param *Data : Pointer to Data to receive (must be 8-bit long)
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566 * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
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568 Status IP_UART_ReceiveByte(IP_USART_001_T *pUART, uint8_t *Data);
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571 * @brief Send a block of data via UART peripheral
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572 * @param pUART : Pointer to selected UARTx peripheral
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573 * @param txbuf : Pointer to Transmit buffer
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574 * @param buflen : Length of Transmit buffer
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575 * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING
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576 * @return Number of bytes sent
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578 * Note: when using UART in BLOCKING mode, a time-out condition is used
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579 * via defined symbol UART_BLOCKING_TIMEOUT.
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581 uint32_t IP_UART_Send(IP_USART_001_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
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584 * @brief Receive a block of data via UART peripheral
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585 * @param pUART : Pointer to selected UARTx peripheral
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586 * @param rxbuf : Pointer to Received buffer
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587 * @param buflen : Length of Received buffer
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588 * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING
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589 * @return Number of bytes received
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591 * Note: when using UART in BLOCKING mode, a time-out condition is used
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592 * via defined symbol UART_BLOCKING_TIMEOUT.
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594 uint32_t IP_UART_Receive(IP_USART_001_T *pUART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
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596 /* UART operate functions -------------------------------------------------------*/
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598 * @brief Enable or disable specified UART interrupt.
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599 * @param pUART : Pointer to selected UARTx peripheral
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600 * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following:
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601 * - UART_INTCFG_RBR : RBR Interrupt enable
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602 * - UART_INTCFG_THRE : THR Interrupt enable
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603 * - UART_INTCFG_RLS : RX line status interrupt enable
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604 * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
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605 * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
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606 * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
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607 * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
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608 * @param NewState : New state of specified UART interrupt type, should be:
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609 * - ENALBE : Enable this UART interrupt type
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610 * - DISALBE : Disable this UART interrupt type
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613 void IP_UART_IntConfig(IP_USART_001_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState);
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616 * @brief Get Source Interrupt
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617 * @param pUART : Pointer to selected UARTx peripheral
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618 * @return Return the value of IIR register
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620 uint32_t IP_UART_IntGetStatus(IP_USART_001_T *pUART);
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623 * @brief Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0
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624 * @param pUART : Pointer to selected UARTx peripheral
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627 void IP_UART_ForceBreak(IP_USART_001_T *pUART);
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630 * @brief Get current value of Line Status register in UART peripheral.
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631 * @param pUART : Pointer to selected UARTx peripheral
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632 * @return Current value of Line Status register in UART peripheral
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634 * The return value of this function must be ANDed with each member in UART_LS_T
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635 * enumeration to determine current flag status corresponding to each Line status type. Because
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636 * some flags in Line Status register will be cleared after reading, the next reading Line
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637 * Status register could not be correct. So this function used to read Line status register
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638 * in one time only, then the return value used to check all flags.
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640 uint8_t IP_UART_GetLineStatus(IP_USART_001_T *pUART);
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643 * @brief Check whether if UART is busy or not
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644 * @param pUART : Pointer to selected UARTx peripheral
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645 * @return RESET if UART is not busy, otherwise return SET.
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647 FlagStatus IP_UART_CheckBusy(IP_USART_001_T *pUART);
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650 * @brief Enable/Disable transmission on UART TxD pin
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651 * @param pUART : Pointer to selected UARTx peripheral
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652 * @param UARTPort : UART ID type
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653 * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE
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656 void IP_UART_TxCmd(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort, FunctionalState NewState);
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658 /* UART FIFO functions ----------------------------------------------------------*/
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660 * @brief Configure FIFO function on selected UART peripheral
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661 * @param pUART : Pointer to selected UARTx peripheral
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662 * @param FIFOCfg : Pointer to a UART_FIFO_CFG_T Structure that contains specified information about FIFO configuration
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665 void IP_UART_FIFOConfig(IP_USART_001_T *pUART, UART_FIFO_CFG_T *FIFOCfg);
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668 * @brief Fills each UART_FIFOInitStruct member with its default value:
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669 * - FIFO_DMAMode = DISABLE
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670 * - FIFO_Level = UART_FIFO_TRGLEV0
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671 * - FIFO_ResetRxBuf = ENABLE
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672 * - FIFO_ResetTxBuf = ENABLE
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673 * - FIFO_State = ENABLE
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674 * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_T structure which will be initialized.
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677 void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_T *UART_FIFOInitStruct);
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680 * @brief Start/Stop Auto Baudrate activity
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681 * @param pUART : Pointer to selected UARTx peripheral
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682 * @param ABConfigStruct : A pointer to UART_AB_CFG_T structure that
\r
683 * contains specified information about UAR auto baud configuration
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684 * @param NewState : New State of Auto baudrate activity, should be ENABLE or DISABLE
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686 * @note Auto-baudrate mode enable bit will be cleared once this mode completed.
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688 void IP_UART_ABCmd(IP_USART_001_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState);
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691 * @brief Clear Autobaud Interrupt
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692 * @param pUART : Pointer to selected UARTx peripheral
\r
693 * @param ABIntType : type of auto-baud interrupt, should be:
\r
694 * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
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695 * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
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698 void IP_UART_ABClearIntPending(IP_USART_001_T *pUART, IP_UART_INT_STATUS_T ABIntType);
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708 #endif /* __USART_001_H_ */
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projects / freertos / blob