1 /*****************************************************************************
2 * MODIFICATION HISTORY:
5 * ----- ---- -------- ---------------------------------------------------
6 * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
7 * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
8 * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
10 * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
11 * generated by the cpu driver, for enabling caches
12 * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
14 * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
15 * Updated the MMU table to mark OCM in high address space
16 * as inner cacheable and reserved space as Invalid
17 * 3.03a sdm 08/20/11 Changes to support FreeRTOS
18 * Updated the MMU table to mark upper half of the DDR as
20 * Setup supervisor and abort mode stacks
21 * Do not initialize/enable L2CC in case of AMP
22 * Initialize UART1 for 9600bps in case of AMP
23 * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
25 * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
27 * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
28 * xparameters.h file for CR630532 - Xil_DCacheFlush()/
29 * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
30 * for MicroBlaze will invalidate data in the cache instead
31 * of flushing it for writeback caches
32 * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
33 * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
34 * Remove redundant dsb/dmb instructions in cache maintenance
36 * Remove redundant dsb in mcr instruction
37 * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
38 * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
39 * driver tcl in xparameters.h. Update the gcc/translationtable.s
40 * for the QSPI complete address range - DT644567
41 * Removed profile directory for armcc compiler and changed
42 * profiling setting to false in standalone_v2_1_0.tcl file
43 * Deleting boot.S file after preprocessing for armcc compiler
44 * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
45 * invalidate the caches before enabling back the MMU and
47 * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
48 * xil_mmu.c. Now we invalidate UTLB, Branch predictor
49 * array, flush the D-cache before changing the attributes
50 * in translation table. The user need not call Xil_DisableMMU
51 * before calling Xil_SetTlbAttributes.
52 * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
53 * sgd initialization is present. Changes for this were done in
54 * uart.c and xil-crt0.s.
55 * Made changes in xil_io.c to use volatile pointers.
56 * Made changes in xil_mmu.c to correct the function
57 * Xil_SetTlbAttributes.
58 * Changes are made xil-crt0.s to initialize the static
60 * Changes are made in boot.s, to fix the TTBR settings,
61 * correct the L2 Cache Auxiliary register settings, L2 cache
63 * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
64 * sgd usleep.c to use global timer intstead of CP15.
65 * Made changes in cortexa9/gcc/translation_table.s to map
66 * the peripheral devices as shareable device memory.
67 * Made changes in cortexa9/gcc/xil-crt0.s to initialize
69 * Made changes in cortexa9/armcc/boot.S to initialize
71 * Made changes in cortexa9/armcc/translation_table.s to
72 * map the peripheral devices as shareable device memory.
73 * Made changes in cortexa9/gcc/boot.S to optimize the
74 * L2 cache settings. Changes the section properties for
75 * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
76 * and cortexa9/gcc/translation_table.S.
77 * Made changes in cortexa9/xil_cache.c to change the
78 * cache invalidation order.
79 * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
80 * compilation/linking issues for C++ compiler.
81 * Made changes in mb_interface.h to remove compilation/
82 * linking issues for C++ compiler.
83 * Added macros for swapb and swaph microblaze instructions
85 * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
87 * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
88 * 3.07a asa 08/31/12 Added xil_printf.h include
89 * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
90 * Corrected L2 cache sequence disable sequence
91 * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
92 * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
94 * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
95 * fixes the CR #692094.
96 * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
97 * 3.10a srt 04/18/13 Implemented ARM Erratas.
98 * Cortex A9 Errata - 742230, 743622, 775420, 794073
99 * L2Cache PL310 Errata - 588369, 727915, 759370
100 * Please refer to file 'xil_errata.h' for errata
102 * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
103 * cache APIs were corresponding to only Layer 1 cache
104 * memories. New APIs were now added and the existing cache
105 * related APIs were changed to provide a uniform interface
106 * to flush/invalidate/enable/disable the complete cache
107 * system which includes both L1 and L2 caches. The changes
108 * for these were done in:
109 * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
111 * Four new files were added for supporting L2 cache. They are:
112 * microblaze_flush_cache_ext.S-> Flushes L2 cache
113 * microblaze_flush_cache_ext_range.S -> Flushes a range of
114 * memory in L2 cache.
115 * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
116 * microblaze_invalidate_cache_ext_range -> Invalidates a
117 * range of memory in L2 cache.
118 * These changes are done to implement PR #697214.
119 * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
120 * fix the CR #706464. L2 cache disabling happens independent
121 * of L1 data cache disable operation. Changes are done in the
122 * same file in cache handling APIs to do a L2 cache sync
123 * (poll reg7_?cache_?sync). This fixes CR #700542.
124 * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
125 * interrupts for ARM. These are done to fix the CR#699680.
126 * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
127 * sync operation. This fixes the CR# 716781.
128 * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
129 * for armcc toolchain.
130 * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
131 * fix issues related to NEON context saving. The assembly
132 * routines for IRQ and FIQ handling are modified.
133 * Deprecated the older BSP (3.10a).
134 * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
135 * various potential issues. Made changes in the function
136 * Xil_SetAttributes in file xil_mmu.c.
137 * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
138 * in src\cortexa9 and src\microblaze folders.
139 * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
140 * L2 cache sync operation and to fix issues around complete
141 * L2 cache flush/invalidation by ways.
142 * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
143 * to fix linking issues with armcc/DS-5. Modified the armcc
144 * makefile to fix issues.
145 * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
146 * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
147 * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
148 * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
149 * src\cortexa9\armcc\) to fix CR#767251
150 * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
151 * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
152 * Few cache lines were missed to invalidate when unaligned address
153 * invalidation was accommodated in Xil_DCacheInvalidateRange.
154 * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
155 * stack memory (which contains return address) was invalidated. So
156 * stack memory is flushed first and then L1D cache is invalidated.
157 * This is done to fix CR #763829
158 * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
159 * mblaze_nt_types.h file and replace uint32_t with u32 in the
160 * profile_hist.c to fix the above CR.
161 * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
162 * instead of libxil.a and added prototypes for
163 * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
165 * 4.1 hk 04/18/14 Add sleep function.
166 * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
167 * some of the *.s files inMB BSP source to *.S.
168 * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
169 * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
171 * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
172 * common/xil_testcache.c
175 *****************************************************************************************/
projects / freertos / blob