git.sur5r.net Git - freertos/blob

   1 /*\r
   2  * @brief Basic CMSIS include file\r
   3  *\r
   4  * @note\r
   5  * Copyright(C) NXP Semiconductors, 2012\r
   6  * All rights reserved.\r
   7  *\r
   8  * @par\r
   9  * Software that is described herein is for illustrative purposes only\r
  10  * which provides customers with programming information regarding the\r
  11  * LPC products.  This software is supplied "AS IS" without any warranties of\r
  12  * any kind, and NXP Semiconductors and its licensor disclaim any and\r
  13  * all warranties, express or implied, including all implied warranties of\r
  14  * merchantability, fitness for a particular purpose and non-infringement of\r
  15  * intellectual property rights.  NXP Semiconductors assumes no responsibility\r
  16  * or liability for the use of the software, conveys no license or rights under any\r
  17  * patent, copyright, mask work right, or any other intellectual property rights in\r
  18  * or to any products. NXP Semiconductors reserves the right to make changes\r
  19  * in the software without notification. NXP Semiconductors also makes no\r
  20  * representation or warranty that such application will be suitable for the\r
  21  * specified use without further testing or modification.\r
  22  *\r
  23  * @par\r
  24  * Permission to use, copy, modify, and distribute this software and its\r
  25  * documentation is hereby granted, under NXP Semiconductors' and its\r
  26  * licensor's relevant copyrights in the software, without fee, provided that it\r
  27  * is used in conjunction with NXP Semiconductors microcontrollers.  This\r
  28  * copyright, permission, and disclaimer notice must appear in all copies of\r
  29  * this code.\r
  30  */\r
  31 \r
  32 #ifndef __CMSIS_H_\r
  33 #define __CMSIS_H_\r
  34 \r
  35 #include "lpc_types.h"\r
  36 \r
  37 #ifdef __cplusplus\r
  38 extern "C" {\r
  39 #endif\r
  40 \r
  41 /** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file\r
  42  * @ingroup CHIP_18XX_43XX_Drivers\r
  43  * @{\r
  44  */\r
  45 \r
  46 #if defined(__ARMCC_VERSION)\r
  47 // Kill warning "#pragma push with no matching #pragma pop"\r
  48   #pragma diag_suppress 2525\r
  49   #pragma push\r
  50   #pragma anon_unions\r
  51 #elif defined(__CWCC__)\r
  52   #pragma push\r
  53   #pragma cpp_extensions on\r
  54 #elif defined(__GNUC__)\r
  55 /* anonymous unions are enabled by default */\r
  56 #elif defined(__IAR_SYSTEMS_ICC__)\r
  57 //  #pragma push // FIXME not usable for IAR\r
  58   #pragma language=extended\r
  59 #else\r
  60   #error Not supported compiler type\r
  61 #endif\r
  62 \r
  63 #if defined(CORE_M4)\r
  64 /** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions\r
  65  * @{\r
  66  */\r
  67 \r
  68 #define __CM4_REV              0x0000           /*!< Cortex-M4 Core Revision               */\r
  69 #define __MPU_PRESENT             1                     /*!< MPU present or not                    */\r
  70 #define __NVIC_PRIO_BITS          3                     /*!< Number of Bits used for Priority Levels */\r
  71 #define __Vendor_SysTickConfig    0                     /*!< Set to 1 if different SysTick Config is used */\r
  72 #ifdef CHIP_LPC43XX\r
  73 #define __FPU_PRESENT             1                     /*!< FPU present or not                    */\r
  74 #else\r
  75 #define __FPU_PRESENT             0                     /*!< FPU present or not                    */\r
  76 #endif\r
  77 \r
  78 /**\r
  79  * @}\r
  80  */\r
  81 \r
  82 /** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers\r
  83  * @{\r
  84  */\r
  85 \r
  86 typedef enum {\r
  87         /* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */\r
  88         Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */\r
  89         NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */\r
  90         HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */\r
  91         MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */\r
  92         BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
  93         UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
  94         SVCall_IRQn                       =  -5,/*!<  11  System Service Call via SVC instruction */\r
  95         DebugMonitor_IRQn                 =  -4,/*!<  12  Debug Monitor                    */\r
  96         PendSV_IRQn                       =  -2,/*!<  14  Pendable request for system service */\r
  97         SysTick_IRQn                      =  -1,/*!<  15  System Tick Timer                */\r
  98 \r
  99         /* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */\r
 100         DAC_IRQn                          =   0,/*!<   0  DAC                              */\r
 101         M0CORE_IRQn                       =   1,/*!<   1  M0a                              */\r
 102         DMA_IRQn                          =   2,/*!<   2  DMA                              */\r
 103         RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */\r
 104         RESERVED2_IRQn                    =   4,\r
 105         ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */\r
 106         SDIO_IRQn                         =   6,/*!<   6  SDIO                             */\r
 107         LCD_IRQn                          =   7,/*!<   7  LCD                              */\r
 108         USB0_IRQn                         =   8,/*!<   8  USB0                             */\r
 109         USB1_IRQn                         =   9,/*!<   9  USB1                             */\r
 110         SCT_IRQn                          =  10,/*!<  10  SCT                              */\r
 111         RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */\r
 112         TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */\r
 113         TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */\r
 114         TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */\r
 115         TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */\r
 116         MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */\r
 117         ADC0_IRQn                         =  17,/*!<  17  ADC0                             */\r
 118         I2C0_IRQn                         =  18,/*!<  18  I2C0                             */\r
 119         I2C1_IRQn                         =  19,/*!<  19  I2C1                             */\r
 120         SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */\r
 121         ADC1_IRQn                         =  21,/*!<  21  ADC1                             */\r
 122         SSP0_IRQn                         =  22,/*!<  22  SSP0                             */\r
 123         SSP1_IRQn                         =  23,/*!<  23  SSP1                             */\r
 124         USART0_IRQn                       =  24,/*!<  24  USART0                           */\r
 125         UART1_IRQn                        =  25,/*!<  25  UART1                            */\r
 126         USART2_IRQn                       =  26,/*!<  26  USART2                           */\r
 127         USART3_IRQn                       =  27,/*!<  27  USART3                           */\r
 128         I2S0_IRQn                         =  28,/*!<  28  I2S0                             */\r
 129         I2S1_IRQn                         =  29,/*!<  29  I2S1                             */\r
 130         RESERVED4_IRQn                    =  30,\r
 131         SGPIO_INT_IRQn                    =  31,/*!<  31  SGPIO_IINT                       */\r
 132         PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */\r
 133         PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */\r
 134         PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */\r
 135         PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */\r
 136         PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */\r
 137         PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */\r
 138         PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */\r
 139         PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */\r
 140         GINT0_IRQn                        =  40,/*!<  40  GINT0                            */\r
 141         GINT1_IRQn                        =  41,/*!<  41  GINT1                            */\r
 142         EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */\r
 143         C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */\r
 144         RESERVED6_IRQn                    =  44,\r
 145         RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */\r
 146         ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */\r
 147         RTC_IRQn                          =  47,/*!<  47  RTC                              */\r
 148         RESERVED8_IRQn                    =  48,\r
 149         WWDT_IRQn                         =  49,/*!<  49  WWDT                             */\r
 150         RESERVED9_IRQn                    =  50,\r
 151         C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */\r
 152         QEI_IRQn                          =  52,/*!<  52  QEI                              */\r
 153 } IRQn_Type;\r
 154 \r
 155 /**\r
 156  * @}\r
 157  */\r
 158 \r
 159 #include "core_cm4.h"                                           /*!< Cortex-M4 processor and core peripherals */\r
 160 \r
 161 #elif defined(CORE_M3)\r
 162 /** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions\r
 163  * @{\r
 164  */\r
 165 \r
 166 #define __MPU_PRESENT             1                     /*!< MPU present or not                    */\r
 167 #define __NVIC_PRIO_BITS          3                     /*!< Number of Bits used for Priority Levels */\r
 168 #define __Vendor_SysTickConfig    0                     /*!< Set to 1 if different SysTick Config is used */\r
 169 #define __FPU_PRESENT             0                     /*!< FPU present or not                    */\r
 170 \r
 171 /**\r
 172  * @}\r
 173  */\r
 174 \r
 175 /** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers\r
 176  * @{\r
 177  */\r
 178 \r
 179 typedef enum {\r
 180         /* -------------------------  Cortex-M3 Processor Exceptions Numbers  ----------------------------- */\r
 181         Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */\r
 182         NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */\r
 183         HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */\r
 184         MemoryManagement_IRQn             = -12,/*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */\r
 185         BusFault_IRQn                     = -11,/*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
 186         UsageFault_IRQn                   = -10,/*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
 187         SVCall_IRQn                       = -5, /*!<  11  System Service Call via SVC instruction */\r
 188         DebugMonitor_IRQn                 = -4, /*!<  12  Debug Monitor                    */\r
 189         PendSV_IRQn                       = -2, /*!<  14  Pendable request for system service */\r
 190         SysTick_IRQn                      = -1, /*!<  15  System Tick Timer                */\r
 191 \r
 192         /* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */\r
 193         DAC_IRQn                          =   0,/*!<   0  DAC                              */\r
 194         RESERVED0_IRQn                    =   1,\r
 195         DMA_IRQn                          =   2,/*!<   2  DMA                              */\r
 196         RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */\r
 197         RESERVED2_IRQn                    =   4,\r
 198         ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */\r
 199         SDIO_IRQn                         =   6,/*!<   6  SDIO                             */\r
 200         LCD_IRQn                          =   7,/*!<   7  LCD                              */\r
 201         USB0_IRQn                         =   8,/*!<   8  USB0                             */\r
 202         USB1_IRQn                         =   9,/*!<   9  USB1                             */\r
 203         SCT_IRQn                          =  10,/*!<  10  SCT                              */\r
 204         RITIMER_IRQn                      =  11,/*!<  11  RITIMER                          */\r
 205         TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */\r
 206         TIMER1_IRQn                       =  13,/*!<  13  TIMER1                           */\r
 207         TIMER2_IRQn                       =  14,/*!<  14  TIMER2                           */\r
 208         TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */\r
 209         MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */\r
 210         ADC0_IRQn                         =  17,/*!<  17  ADC0                             */\r
 211         I2C0_IRQn                         =  18,/*!<  18  I2C0                             */\r
 212         I2C1_IRQn                         =  19,/*!<  19  I2C1                             */\r
 213         RESERVED3_IRQn                    =  20,\r
 214         ADC1_IRQn                         =  21,/*!<  21  ADC1                             */\r
 215         SSP0_IRQn                         =  22,/*!<  22  SSP0                             */\r
 216         SSP1_IRQn                         =  23,/*!<  23  SSP1                             */\r
 217         USART0_IRQn                       =  24,/*!<  24  USART0                           */\r
 218         UART1_IRQn                        =  25,/*!<  25  UART1                            */\r
 219         USART2_IRQn                       =  26,/*!<  26  USART2                           */\r
 220         USART3_IRQn                       =  27,/*!<  27  USART3                           */\r
 221         I2S0_IRQn                         =  28,/*!<  28  I2S0                             */\r
 222         I2S1_IRQn                         =  29,/*!<  29  I2S1                             */\r
 223         RESERVED4_IRQn                    =  30,\r
 224         RESERVED5_IRQn                    =  31,\r
 225         PIN_INT0_IRQn                     =  32,/*!<  32  PIN_INT0                         */\r
 226         PIN_INT1_IRQn                     =  33,/*!<  33  PIN_INT1                         */\r
 227         PIN_INT2_IRQn                     =  34,/*!<  34  PIN_INT2                         */\r
 228         PIN_INT3_IRQn                     =  35,/*!<  35  PIN_INT3                         */\r
 229         PIN_INT4_IRQn                     =  36,/*!<  36  PIN_INT4                         */\r
 230         PIN_INT5_IRQn                     =  37,/*!<  37  PIN_INT5                         */\r
 231         PIN_INT6_IRQn                     =  38,/*!<  38  PIN_INT6                         */\r
 232         PIN_INT7_IRQn                     =  39,/*!<  39  PIN_INT7                         */\r
 233         GINT0_IRQn                        =  40,/*!<  40  GINT0                            */\r
 234         GINT1_IRQn                        =  41,/*!<  41  GINT1                            */\r
 235         EVENTROUTER_IRQn                  =  42,/*!<  42  EVENTROUTER                      */\r
 236         C_CAN1_IRQn                       =  43,/*!<  43  C_CAN1                           */\r
 237         RESERVED6_IRQn                    =  44,\r
 238         RESERVED7_IRQn                    =  45,/*!<  45  VADC                             */\r
 239         ATIMER_IRQn                       =  46,/*!<  46  ATIMER                           */\r
 240         RTC_IRQn                          =  47,/*!<  47  RTC                              */\r
 241         RESERVED8_IRQn                    =  48,\r
 242         WWDT_IRQn                         =  49,/*!<  49  WWDT                             */\r
 243         RESERVED9_IRQn                    =  50,\r
 244         C_CAN0_IRQn                       =  51,/*!<  51  C_CAN0                           */\r
 245         QEI_IRQn                          =  52,/*!<  52  QEI                              */\r
 246 } IRQn_Type;\r
 247 \r
 248 /**\r
 249  * @}\r
 250  */\r
 251 \r
 252 #include "core_cm3.h"                                           /*!< Cortex-M3 processor and core peripherals */\r
 253 \r
 254 #elif defined(CORE_M0)\r
 255 /** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions\r
 256  * @{\r
 257  */\r
 258 \r
 259 #define __MPU_PRESENT             0                     /*!< MPU present or not                    */\r
 260 #define __NVIC_PRIO_BITS          2                     /*!< Number of Bits used for Priority Levels */\r
 261 #define __Vendor_SysTickConfig    0                     /*!< Set to 1 if different SysTick Config is used */\r
 262 #define __FPU_PRESENT             0                     /*!< FPU present or not                    */\r
 263 \r
 264 /**\r
 265  * @}\r
 266  */\r
 267 \r
 268 /** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers\r
 269  * @{\r
 270  */\r
 271 \r
 272 typedef enum {\r
 273         /* -------------------------  Cortex-M0 Processor Exceptions Numbers  ----------------------------- */\r
 274         Reset_IRQn                        = -15,/*!<   1  Reset Vector, invoked on Power up and warm reset */\r
 275         NonMaskableInt_IRQn               = -14,/*!<   2  Non maskable Interrupt, cannot be stopped or preempted */\r
 276         HardFault_IRQn                    = -13,/*!<   3  Hard Fault, all classes of Fault */\r
 277         SVCall_IRQn                       = -5, /*!<  11  System Service Call via SVC instruction */\r
 278         DebugMonitor_IRQn                 = -4, /*!<  12  Debug Monitor                    */\r
 279         PendSV_IRQn                       = -2, /*!<  14  Pendable request for system service */\r
 280         SysTick_IRQn                      = -1, /*!<  15  System Tick Timer           */\r
 281 \r
 282         /* ---------------------------  LPC18xx/43xx Specific Interrupt Numbers  ------------------------------- */\r
 283         DAC_IRQn                          =   0,/*!<   0  DAC                              */\r
 284         M0_M4CORE_IRQn                    =   1,/*!<   1  M0a                              */\r
 285         DMA_IRQn                          =   2,/*!<   2  DMA                              */\r
 286         RESERVED1_IRQn                    =   3,/*!<   3  EZH/EDM                          */\r
 287         FLASHEEPROM_IRQn                  =   4,/*!<   4  ORed Flash EEPROM Bank A, B, EEPROM   */\r
 288         ETHERNET_IRQn                     =   5,/*!<   5  ETHERNET                         */\r
 289         SDIO_IRQn                         =   6,/*!<   6  SDIO                             */\r
 290         LCD_IRQn                          =   7,/*!<   7  LCD                              */\r
 291         USB0_IRQn                         =   8,/*!<   8  USB0                             */\r
 292         USB1_IRQn                         =   9,/*!<   9  USB1                             */\r
 293         SCT_IRQn                          =  10,/*!<  10  SCT                              */\r
 294         RITIMER_IRQn                      =  11,/*!<  11  ORed RITIMER, WDT                */\r
 295         TIMER0_IRQn                       =  12,/*!<  12  TIMER0                           */\r
 296         GINT1_IRQn                        =  13,/*!<  13  GINT1                            */\r
 297         PIN_INT4_IRQn                     =  14,/*!<  14  GPIO 4                           */\r
 298         TIMER3_IRQn                       =  15,/*!<  15  TIMER3                           */\r
 299         MCPWM_IRQn                        =  16,/*!<  16  MCPWM                            */\r
 300         ADC0_IRQn                         =  17,/*!<  17  ADC0                             */\r
 301         I2C0_IRQn                         =  18,/*!<  18  ORed I2C0, I2C1                  */\r
 302         SGPIO_INT_IRQn                    =  19,/*!<  19  SGPIO                            */\r
 303         SPI_INT_IRQn                      =  20,/*!<  20  SPI_INT                          */\r
 304         ADC1_IRQn                         =  21,/*!<  21  ADC1                             */\r
 305         SSP0_IRQn                         =  22,/*!<  22  ORed SSP0, SSP1                  */\r
 306         EVENTROUTER_IRQn                  =  23,/*!<  23  EVENTROUTER                      */\r
 307         USART0_IRQn                       =  24,/*!<  24  USART0                           */\r
 308         UART1_IRQn                        =  25,/*!<  25  UART1                            */\r
 309         USART2_IRQn                       =  26,/*!<  26  USART2                           */\r
 310         USART3_IRQn                       =  27,/*!<  27  USART3                           */\r
 311         I2S0_IRQn                         =  28,/*!<  28  ORed I2S0, I2S1                  */\r
 312         C_CAN0_IRQn                       =  29,/*!<  29  C_CAN0                           */\r
 313         I2S1_IRQn                         =  29,/*!<  29  I2S1                             */\r
 314         RESERVED2_IRQn                    =  30,\r
 315         RESERVED3_IRQn                    =  31,\r
 316 } IRQn_Type;\r
 317 \r
 318 /**\r
 319  * @}\r
 320  */\r
 321 \r
 322 #include "core_cm0.h"                                           /*!< Cortex-M4 processor and core peripherals */\r
 323 #else\r
 324 #error Please #define CORE_M0, CORE_M3, or CORE_M4\r
 325 #endif\r
 326 \r
 327 /**\r
 328  * @}\r
 329  */\r
 330 \r
 331 #ifdef __cplusplus\r
 332 }\r
 333 #endif\r
 334 \r
 335 #endif /* __CMSIS_H_ */\r