1 /**************************************************************************//**
\r
2 * @file efm32wg_aes.h
\r
3 * @brief EFM32WG_AES register and bit field definitions
\r
5 ******************************************************************************
\r
7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
\r
8 ******************************************************************************
\r
10 * Permission is granted to anyone to use this software for any purpose,
\r
11 * including commercial applications, and to alter it and redistribute it
\r
12 * freely, subject to the following restrictions:
\r
14 * 1. The origin of this software must not be misrepresented; you must not
\r
15 * claim that you wrote the original software.@n
\r
16 * 2. Altered source versions must be plainly marked as such, and must not be
\r
17 * misrepresented as being the original software.@n
\r
18 * 3. This notice may not be removed or altered from any source distribution.
\r
20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
\r
21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
\r
22 * providing the Software "AS IS", with no express or implied warranties of any
\r
23 * kind, including, but not limited to, any implied warranties of
\r
24 * merchantability or fitness for any particular purpose or warranties against
\r
25 * infringement of any proprietary rights of a third party.
\r
27 * Silicon Laboratories, Inc. will not be liable for any consequential,
\r
28 * incidental, or special damages, or any other relief, or for any claim by
\r
29 * any third party, arising from your use of this Software.
\r
31 *****************************************************************************/
\r
32 /**************************************************************************//**
\r
35 ******************************************************************************/
\r
36 /**************************************************************************//**
\r
37 * @defgroup EFM32WG_AES
\r
39 * @brief EFM32WG_AES Register Declaration
\r
40 *****************************************************************************/
\r
43 __IO uint32_t CTRL; /**< Control Register */
\r
44 __IO uint32_t CMD; /**< Command Register */
\r
45 __I uint32_t STATUS; /**< Status Register */
\r
46 __IO uint32_t IEN; /**< Interrupt Enable Register */
\r
47 __I uint32_t IF; /**< Interrupt Flag Register */
\r
48 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
\r
49 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
\r
50 __IO uint32_t DATA; /**< DATA Register */
\r
51 __IO uint32_t XORDATA; /**< XORDATA Register */
\r
52 uint32_t RESERVED0[3]; /**< Reserved for future use **/
\r
53 __IO uint32_t KEYLA; /**< KEY Low Register */
\r
54 __IO uint32_t KEYLB; /**< KEY Low Register */
\r
55 __IO uint32_t KEYLC; /**< KEY Low Register */
\r
56 __IO uint32_t KEYLD; /**< KEY Low Register */
\r
57 __IO uint32_t KEYHA; /**< KEY High Register */
\r
58 __IO uint32_t KEYHB; /**< KEY High Register */
\r
59 __IO uint32_t KEYHC; /**< KEY High Register */
\r
60 __IO uint32_t KEYHD; /**< KEY High Register */
\r
61 } AES_TypeDef; /** @} */
\r
63 /**************************************************************************//**
\r
64 * @defgroup EFM32WG_AES_BitFields
\r
66 *****************************************************************************/
\r
68 /* Bit fields for AES CTRL */
\r
69 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
\r
70 #define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
\r
71 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
\r
72 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
\r
73 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
\r
74 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
75 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
\r
76 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
\r
77 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
\r
78 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
\r
79 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
80 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
\r
81 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
\r
82 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
\r
83 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
\r
84 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
85 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
\r
86 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
\r
87 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
\r
88 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
\r
89 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
90 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
\r
91 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
\r
92 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
\r
93 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
\r
94 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
95 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
\r
96 #define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
\r
97 #define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
\r
98 #define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
\r
99 #define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
\r
100 #define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
\r
102 /* Bit fields for AES CMD */
\r
103 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
\r
104 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
\r
105 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
\r
106 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
\r
107 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
\r
108 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
\r
109 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
\r
110 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
\r
111 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
\r
112 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
\r
113 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
\r
114 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
\r
116 /* Bit fields for AES STATUS */
\r
117 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
\r
118 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
\r
119 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
\r
120 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
\r
121 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
\r
122 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
\r
123 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
\r
125 /* Bit fields for AES IEN */
\r
126 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
\r
127 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
\r
128 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
\r
129 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
\r
130 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
\r
131 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
\r
132 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
\r
134 /* Bit fields for AES IF */
\r
135 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
\r
136 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
\r
137 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
\r
138 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
\r
139 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
\r
140 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
\r
141 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
\r
143 /* Bit fields for AES IFS */
\r
144 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
\r
145 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
\r
146 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
\r
147 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
\r
148 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
\r
149 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
\r
150 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
\r
152 /* Bit fields for AES IFC */
\r
153 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
\r
154 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
\r
155 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
\r
156 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
\r
157 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
\r
158 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
\r
159 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
\r
161 /* Bit fields for AES DATA */
\r
162 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
\r
163 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
\r
164 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
\r
165 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
\r
166 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
\r
167 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
\r
169 /* Bit fields for AES XORDATA */
\r
170 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
\r
171 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
\r
172 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
\r
173 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
\r
174 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
\r
175 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
\r
177 /* Bit fields for AES KEYLA */
\r
178 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
\r
179 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
\r
180 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
\r
181 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
\r
182 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
\r
183 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
\r
185 /* Bit fields for AES KEYLB */
\r
186 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
\r
187 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
\r
188 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
\r
189 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
\r
190 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
\r
191 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
\r
193 /* Bit fields for AES KEYLC */
\r
194 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
\r
195 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
\r
196 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
\r
197 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
\r
198 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
\r
199 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
\r
201 /* Bit fields for AES KEYLD */
\r
202 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
\r
203 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
\r
204 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
\r
205 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
\r
206 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
\r
207 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
\r
209 /* Bit fields for AES KEYHA */
\r
210 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
\r
211 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
\r
212 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
\r
213 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
\r
214 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
\r
215 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
\r
217 /* Bit fields for AES KEYHB */
\r
218 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
\r
219 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
\r
220 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
\r
221 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
\r
222 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
\r
223 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
\r
225 /* Bit fields for AES KEYHC */
\r
226 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
\r
227 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
\r
228 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
\r
229 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
\r
230 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
\r
231 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
\r
233 /* Bit fields for AES KEYHD */
\r
234 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
\r
235 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
\r
236 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
\r
237 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
\r
238 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
\r
239 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
\r
241 /** @} End of group EFM32WG_AES */
\r
242 /** @} End of group Parts */
\r
projects / freertos / blob