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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /****************************************************************************/
  33 /**
  34 *
  35 * @file xaxipmon_hw.h
  36 * @addtogroup axipmon_v6_3
  37 * @{
  38 *
  39 * This header file contains identifiers and basic driver functions (or
  40 * macros) that can be used to access the AXI Performance Monitor.
  41 *
  42 * Refer to the device specification for more information about this driver.
  43 *
  44 * @note  None.
  45 *
  46 * <pre>
  47 *
  48 * MODIFICATION HISTORY:
  49 *
  50 * Ver   Who    Date     Changes
  51 * ----- -----  -------- -----------------------------------------------------
  52 * 1.00a bss    02/27/12 First release
  53 * 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
  54 * 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
  55 *                       v2_01a version of IP.
  56 * 3.01a bss    10/25/12 To support new version of IP:
  57 *                       Added XAPM_MCXLOGEN_OFFSET and
  58 *                       XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
  59 * 4.00a bss    01/17/13 To support new version of IP:
  60 *                       Added XAPM_LATENCYID_OFFSET,
  61 *                       XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
  62 *                       XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
  63 * 5.00a bss   08/26/13  To support new version of IP:
  64 *                       Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
  65 *                       XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
  66 *                       Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
  67 *                       Added XAPM_CR_IDFILTER_ENABLE_MASK,
  68 *                       XAPM_CR_WRLATENCY_START_MASK,
  69 *                       XAPM_CR_WRLATENCY_END_MASK,
  70 *                       XAPM_CR_RDLATENCY_START_MASK,
  71 *                       XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
  72 *                       and XAPM_MASKID_WID_MASK macros.
  73 *                       Renamed:
  74 *                       XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
  75 *                       XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
  76 *                       XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
  77 *
  78 * 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
  79 *                                        Zynq MP APM.
  80 *
  81 * 6.3  kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
  82 * </pre>
  83 *
  84 *****************************************************************************/
  85 #ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
  86 #define XAXIPMON_HW_H /* by using protection macros  */
  87
  88 #ifdef __cplusplus
  89 extern "C" {
  90 #endif
  91
  92 /***************************** Include Files ********************************/
  93
  94 #include "xil_types.h"
  95 #include "xil_assert.h"
  96 #include "xil_io.h"
  97
  98 /************************** Constant Definitions ****************************/
  99
 100
 101 /**@name Register offsets of AXIMONITOR in the Device Config
 102  *
 103  * The following constants provide access to each of the registers of the
 104  * AXI PERFORMANCE MONITOR device.
 105  * @{
 106  */
 107
 108 #define XAPM_GCC_HIGH_OFFSET            0x00000000U     /**< Global Clock Counter
 109                                                         32 to 63 bits  */
 110 #define XAPM_GCC_LOW_OFFSET             0x00000004U     /**< Global Clock Counter Lower
 111                                                         0-31 bits  */
 112 #define XAPM_SI_HIGH_OFFSET             0x00000020U     /**< Sample Interval MSB */
 113 #define XAPM_SI_LOW_OFFSET              0x00000024U     /**< Sample Interval LSB */
 114 #define XAPM_SICR_OFFSET                0x00000028U     /**< Sample Interval Control
 115                                                         Register */
 116 #define XAPM_SR_OFFSET                  0x0000002CU     /**< Sample Register */
 117 #define XAPM_GIE_OFFSET                 0x00000030U     /**< Global Interrupt Enable
 118                                                         Register */
 119 #define XAPM_IE_OFFSET                  0x00000034U     /**< Interrupt Enable Register */
 120 #define XAPM_IS_OFFSET                  0x00000038U     /**< Interrupt Status Register */
 121
 122 #define XAPM_MSR0_OFFSET                0x00000044U     /**< Metric Selector 0 Register */
 123 #define XAPM_MSR1_OFFSET                0x00000048U     /**< Metric Selector 1 Register */
 124 #define XAPM_MSR2_OFFSET                0x0000004CU     /**< Metric Selector 2 Register */
 125
 126 #define XAPM_MC0_OFFSET                 0x00000100U     /**< Metric Counter 0 Register */
 127 #define XAPM_INC0_OFFSET                0x00000104U     /**< Incrementer 0 Register */
 128 #define XAPM_RANGE0_OFFSET              0x00000108U     /**< Range 0 Register */
 129 #define XAPM_MC0LOGEN_OFFSET            0x0000010CU     /**< Metric Counter 0
 130                                                         Log Enable Register */
 131 #define XAPM_MC1_OFFSET                 0x00000110U     /**< Metric Counter 1 Register */
 132 #define XAPM_INC1_OFFSET                0x00000114U     /**< Incrementer 1 Register */
 133 #define XAPM_RANGE1_OFFSET              0x00000118U     /**< Range 1 Register */
 134 #define XAPM_MC1LOGEN_OFFSET            0x0000011CU     /**< Metric Counter 1
 135                                                         Log Enable Register */
 136 #define XAPM_MC2_OFFSET                 0x00000120U     /**< Metric Counter 2 Register */
 137 #define XAPM_INC2_OFFSET                0x00000124U     /**< Incrementer 2 Register */
 138 #define XAPM_RANGE2_OFFSET              0x00000128U     /**< Range 2 Register */
 139 #define XAPM_MC2LOGEN_OFFSET            0x0000012CU     /**< Metric Counter 2
 140                                                         Log Enable Register */
 141 #define XAPM_MC3_OFFSET                 0x00000130U     /**< Metric Counter 3 Register */
 142 #define XAPM_INC3_OFFSET                0x00000134U     /**< Incrementer 3 Register */
 143 #define XAPM_RANGE3_OFFSET              0x00000138U     /**< Range 3 Register */
 144 #define XAPM_MC3LOGEN_OFFSET            0x0000013CU     /**< Metric Counter 3
 145                                                         Log Enable Register */
 146 #define XAPM_MC4_OFFSET                 0x00000140U     /**< Metric Counter 4 Register */
 147 #define XAPM_INC4_OFFSET                0x00000144U     /**< Incrementer 4 Register */
 148 #define XAPM_RANGE4_OFFSET              0x00000148U     /**< Range 4 Register */
 149 #define XAPM_MC4LOGEN_OFFSET            0x0000014CU     /**< Metric Counter 4
 150                                                         Log Enable Register */
 151 #define XAPM_MC5_OFFSET                 0x00000150U     /**< Metric Counter 5
 152                                                         Register */
 153 #define XAPM_INC5_OFFSET                0x00000154U     /**< Incrementer 5 Register */
 154 #define XAPM_RANGE5_OFFSET              0x00000158U     /**< Range 5 Register */
 155 #define XAPM_MC5LOGEN_OFFSET            0x0000015CU     /**< Metric Counter 5
 156                                                         Log Enable Register */
 157 #define XAPM_MC6_OFFSET                 0x00000160U     /**< Metric Counter 6
 158                                                         Register */
 159 #define XAPM_INC6_OFFSET                0x00000164U     /**< Incrementer 6 Register */
 160 #define XAPM_RANGE6_OFFSET              0x00000168U     /**< Range 6 Register */
 161 #define XAPM_MC6LOGEN_OFFSET            0x0000016CU     /**< Metric Counter 6
 162                                                         Log Enable Register */
 163 #define XAPM_MC7_OFFSET                 0x00000170U     /**< Metric Counter 7
 164                                                         Register */
 165 #define XAPM_INC7_OFFSET                0x00000174U     /**< Incrementer 7 Register */
 166 #define XAPM_RANGE7_OFFSET              0x00000178U     /**< Range 7 Register */
 167 #define XAPM_MC7LOGEN_OFFSET            0x0000017CU     /**< Metric Counter 7
 168                                                         Log Enable Register */
 169 #define XAPM_MC8_OFFSET                 0x00000180U     /**< Metric Counter 8
 170                                                         Register */
 171 #define XAPM_INC8_OFFSET                0x00000184U     /**< Incrementer 8 Register */
 172 #define XAPM_RANGE8_OFFSET              0x00000188U     /**< Range 8 Register */
 173 #define XAPM_MC8LOGEN_OFFSET            0x0000018CU     /**< Metric Counter 8
 174                                                         Log Enable Register */
 175 #define XAPM_MC9_OFFSET                 0x00000190U     /**< Metric Counter 9
 176                                                         Register */
 177 #define XAPM_INC9_OFFSET                0x00000194U     /**< Incrementer 9 Register */
 178 #define XAPM_RANGE9_OFFSET              0x00000198U     /**< Range 9 Register */
 179 #define XAPM_MC9LOGEN_OFFSET            0x0000019CU     /**< Metric Counter 9
 180                                                         Log Enable Register */
 181 #define XAPM_SMC0_OFFSET                0x00000200U     /**< Sampled Metric Counter
 182                                                         0 Register */
 183 #define XAPM_SINC0_OFFSET               0x00000204U     /**< Sampled Incrementer
 184                                                         0 Register */
 185 #define XAPM_SMC1_OFFSET                0x00000210U     /**< Sampled Metric Counter
 186                                                         1 Register */
 187 #define XAPM_SINC1_OFFSET               0x00000214U     /**< Sampled Incrementer
 188                                                         1 Register */
 189 #define XAPM_SMC2_OFFSET                0x00000220U     /**< Sampled Metric Counter
 190                                                         2 Register */
 191 #define XAPM_SINC2_OFFSET               0x00000224U     /**< Sampled Incrementer
 192                                                         2 Register */
 193 #define XAPM_SMC3_OFFSET                0x00000230U     /**< Sampled Metric Counter
 194                                                         3 Register */
 195 #define XAPM_SINC3_OFFSET               0x00000234U     /**< Sampled Incrementer
 196                                                         3 Register */
 197 #define XAPM_SMC4_OFFSET                0x00000240U     /**< Sampled Metric Counter
 198                                                         4 Register */
 199 #define XAPM_SINC4_OFFSET               0x00000244U     /**< Sampled Incrementer
 200                                                         4 Register */
 201 #define XAPM_SMC5_OFFSET                0x00000250U     /**< Sampled Metric Counter
 202                                                         5 Register */
 203 #define XAPM_SINC5_OFFSET               0x00000254U     /**< Sampled Incrementer
 204                                                         5 Register */
 205 #define XAPM_SMC6_OFFSET                0x00000260U     /**< Sampled Metric Counter
 206                                                         6 Register */
 207 #define XAPM_SINC6_OFFSET               0x00000264U     /**< Sampled Incrementer
 208                                                         6 Register */
 209 #define XAPM_SMC7_OFFSET                0x00000270U     /**< Sampled Metric Counter
 210                                                         7 Register */
 211 #define XAPM_SINC7_OFFSET               0x00000274U     /**< Sampled Incrementer
 212                                                         7 Register */
 213 #define XAPM_SMC8_OFFSET                0x00000280U     /**< Sampled Metric Counter
 214                                                         8 Register */
 215 #define XAPM_SINC8_OFFSET               0x00000284U     /**< Sampled Incrementer
 216                                                         8 Register */
 217 #define XAPM_SMC9_OFFSET                0x00000290U     /**< Sampled Metric Counter
 218                                                         9 Register */
 219 #define XAPM_SINC9_OFFSET               0x00000294U     /**< Sampled Incrementer
 220                                                         9 Register */
 221
 222 #define XAPM_MC10_OFFSET                0x000001A0U     /**< Metric Counter 10
 223                                                         Register */
 224 #define XAPM_MC11_OFFSET                0x000001B0U     /**< Metric Counter 11
 225                                                         Register */
 226 #define XAPM_MC12_OFFSET                0x00000500U     /**< Metric Counter 12
 227                                                         Register */
 228 #define XAPM_MC13_OFFSET                0x00000510U     /**< Metric Counter 13
 229                                                         Register */
 230 #define XAPM_MC14_OFFSET                0x00000520U     /**< Metric Counter 14
 231                                                         Register */
 232 #define XAPM_MC15_OFFSET                0x00000530U     /**< Metric Counter 15
 233                                                         Register */
 234 #define XAPM_MC16_OFFSET                0x00000540U     /**< Metric Counter 16
 235                                                         Register */
 236 #define XAPM_MC17_OFFSET                0x00000550U     /**< Metric Counter 17
 237                                                         Register */
 238 #define XAPM_MC18_OFFSET                0x00000560U     /**< Metric Counter 18
 239                                                         Register */
 240 #define XAPM_MC19_OFFSET                0x00000570U     /**< Metric Counter 19
 241                                                         Register */
 242 #define XAPM_MC20_OFFSET                0x00000580U     /**< Metric Counter 20
 243                                                         Register */
 244 #define XAPM_MC21_OFFSET                0x00000590U     /**< Metric Counter 21
 245                                                         Register */
 246 #define XAPM_MC22_OFFSET                0x000005A0U     /**< Metric Counter 22
 247                                                         Register */
 248 #define XAPM_MC23_OFFSET                0x000005B0U     /**< Metric Counter 23
 249                                                         Register */
 250 #define XAPM_MC24_OFFSET                0x00000700U     /**< Metric Counter 24
 251                                                         Register */
 252 #define XAPM_MC25_OFFSET                0x00000710U     /**< Metric Counter 25
 253                                                         Register */
 254 #define XAPM_MC26_OFFSET                0x00000720U     /**< Metric Counter 26
 255                                                         Register */
 256 #define XAPM_MC27_OFFSET                0x00000730U     /**< Metric Counter 27
 257                                                         Register */
 258 #define XAPM_MC28_OFFSET                0x00000740U     /**< Metric Counter 28
 259                                                         Register */
 260 #define XAPM_MC29_OFFSET                0x00000750U     /**< Metric Counter 29
 261                                                         Register */
 262 #define XAPM_MC30_OFFSET                0x00000760U     /**< Metric Counter 30
 263                                                         Register */
 264 #define XAPM_MC31_OFFSET                0x00000770U     /**< Metric Counter 31
 265                                                         Register */
 266 #define XAPM_MC32_OFFSET                0x00000780U     /**< Metric Counter 32
 267                                                         Register */
 268 #define XAPM_MC33_OFFSET                0x00000790U     /**< Metric Counter 33
 269                                                         Register */
 270 #define XAPM_MC34_OFFSET                0x000007A0U     /**< Metric Counter 34
 271                                                         Register */
 272 #define XAPM_MC35_OFFSET                0x000007B0U     /**< Metric Counter 35
 273                                                         Register */
 274 #define XAPM_MC36_OFFSET                0x00000900U     /**< Metric Counter 36
 275                                                         Register */
 276 #define XAPM_MC37_OFFSET                0x00000910U     /**< Metric Counter 37
 277                                                         Register */
 278 #define XAPM_MC38_OFFSET                0x00000920U     /**< Metric Counter 38
 279                                                         Register */
 280 #define XAPM_MC39_OFFSET                0x00000930U     /**< Metric Counter 39
 281                                                         Register */
 282 #define XAPM_MC40_OFFSET                0x00000940U     /**< Metric Counter 40
 283                                                         Register */
 284 #define XAPM_MC41_OFFSET                0x00000950U     /**< Metric Counter 41
 285                                                         Register */
 286 #define XAPM_MC42_OFFSET                0x00000960U     /**< Metric Counter 42
 287                                                         Register */
 288 #define XAPM_MC43_OFFSET                0x00000970U     /**< Metric Counter 43
 289                                                         Register */
 290 #define XAPM_MC44_OFFSET                0x00000980U     /**< Metric Counter 44
 291                                                         Register */
 292 #define XAPM_MC45_OFFSET                0x00000990U     /**< Metric Counter 45
 293                                                         Register */
 294 #define XAPM_MC46_OFFSET                0x000009A0U     /**< Metric Counter 46
 295                                                         Register */
 296 #define XAPM_MC47_OFFSET                0x000009B0U     /**< Metric Counter 47
 297                                                         Register */
 298
 299 #define XAPM_SMC10_OFFSET               0x000002A0U     /**< Sampled Metric Counter
 300                                                         10 Register */
 301 #define XAPM_SMC11_OFFSET               0x000002B0U     /**< Sampled Metric Counter
 302                                                         11 Register */
 303 #define XAPM_SMC12_OFFSET               0x00000600U     /**< Sampled Metric Counter
 304                                                         12 Register */
 305 #define XAPM_SMC13_OFFSET               0x00000610U     /**< Sampled Metric Counter
 306                                                         13 Register */
 307 #define XAPM_SMC14_OFFSET               0x00000620U     /**< Sampled Metric Counter
 308                                                         14 Register */
 309 #define XAPM_SMC15_OFFSET               0x00000630U     /**< Sampled Metric Counter
 310                                                         15 Register */
 311 #define XAPM_SMC16_OFFSET               0x00000640U     /**< Sampled Metric Counter
 312                                                         16 Register */
 313 #define XAPM_SMC17_OFFSET               0x00000650U     /**< Sampled Metric Counter
 314                                                         17 Register */
 315 #define XAPM_SMC18_OFFSET               0x00000660U     /**< Sampled Metric Counter
 316                                                         18 Register */
 317 #define XAPM_SMC19_OFFSET               0x00000670U     /**< Sampled Metric Counter
 318                                                         19 Register */
 319 #define XAPM_SMC20_OFFSET               0x00000680U     /**< Sampled Metric Counter
 320                                                         20 Register */
 321 #define XAPM_SMC21_OFFSET               0x00000690U     /**< Sampled Metric Counter
 322                                                         21 Register */
 323 #define XAPM_SMC22_OFFSET               0x000006A0U     /**< Sampled Metric Counter
 324                                                         22 Register */
 325 #define XAPM_SMC23_OFFSET               0x000006B0U     /**< Sampled Metric Counter
 326                                                         23 Register */
 327 #define XAPM_SMC24_OFFSET               0x00000800U     /**< Sampled Metric Counter
 328                                                         24 Register */
 329 #define XAPM_SMC25_OFFSET               0x00000810U     /**< Sampled Metric Counter
 330                                                         25 Register */
 331 #define XAPM_SMC26_OFFSET               0x00000820U     /**< Sampled Metric Counter
 332                                                         26 Register */
 333 #define XAPM_SMC27_OFFSET               0x00000830U     /**< Sampled Metric Counter
 334                                                         27 Register */
 335 #define XAPM_SMC28_OFFSET               0x00000840U     /**< Sampled Metric Counter
 336                                                         28 Register */
 337 #define XAPM_SMC29_OFFSET               0x00000850U     /**< Sampled Metric Counter
 338                                                         29 Register */
 339 #define XAPM_SMC30_OFFSET               0x00000860U     /**< Sampled Metric Counter
 340                                                         30 Register */
 341 #define XAPM_SMC31_OFFSET               0x00000870U     /**< Sampled Metric Counter
 342                                                         31 Register */
 343 #define XAPM_SMC32_OFFSET               0x00000880U     /**< Sampled Metric Counter
 344                                                         32 Register */
 345 #define XAPM_SMC33_OFFSET               0x00000890U     /**< Sampled Metric Counter
 346                                                         33 Register */
 347 #define XAPM_SMC34_OFFSET               0x000008A0U     /**< Sampled Metric Counter
 348                                                         34 Register */
 349 #define XAPM_SMC35_OFFSET               0x000008B0U     /**< Sampled Metric Counter
 350                                                         35 Register */
 351 #define XAPM_SMC36_OFFSET               0x00000A00U     /**< Sampled Metric Counter
 352                                                         36 Register */
 353 #define XAPM_SMC37_OFFSET               0x00000A10U     /**< Sampled Metric Counter
 354                                                         37 Register */
 355 #define XAPM_SMC38_OFFSET               0x00000A20U     /**< Sampled Metric Counter
 356                                                         38 Register */
 357 #define XAPM_SMC39_OFFSET               0x00000A30U     /**< Sampled Metric Counter
 358                                                         39 Register */
 359 #define XAPM_SMC40_OFFSET               0x00000A40U     /**< Sampled Metric Counter
 360                                                         40 Register */
 361 #define XAPM_SMC41_OFFSET               0x00000A50U     /**< Sampled Metric Counter
 362                                                         41 Register */
 363 #define XAPM_SMC42_OFFSET               0x00000A60U     /**< Sampled Metric Counter
 364                                                         42 Register */
 365 #define XAPM_SMC43_OFFSET               0x00000A70U     /**< Sampled Metric Counter
 366                                                         43 Register */
 367 #define XAPM_SMC44_OFFSET               0x00000A80U     /**< Sampled Metric Counter
 368                                                         44 Register */
 369 #define XAPM_SMC45_OFFSET               0x00000A90U     /**< Sampled Metric Counter
 370                                                         45 Register */
 371 #define XAPM_SMC46_OFFSET               0x00000AA0U     /**< Sampled Metric Counter
 372                                                         46 Register */
 373 #define XAPM_SMC47_OFFSET               0x00000AB0U     /**< Sampled Metric Counter
 374                                                         47 Register */
 375
 376 #define XAPM_CTL_OFFSET                 0x00000300U     /**< Control Register */
 377
 378 #define XAPM_ID_OFFSET                  0x00000304U     /**< Latency ID Register */
 379
 380 #define XAPM_IDMASK_OFFSET              0x00000308U     /**< ID Mask Register */
 381
 382 #define XAPM_RID_OFFSET                 0x0000030CU     /**< Latency Write ID Register */
 383
 384 #define XAPM_RIDMASK_OFFSET             0x00000310U     /**< Read ID Mask Register */
 385
 386 #define XAPM_FEC_OFFSET                 0x00000400U     /**< Flag Enable
 387                                                         Control Register */
 388
 389 #define XAPM_SWD_OFFSET                 0x00000404U     /**< Software-written
 390                                                         Data Register */
 391
 392 /* @} */
 393
 394 /**
 395  * @name AXI Monitor Sample Interval Control Register mask(s)
 396  * @{
 397  */
 398
 399 #define XAPM_SICR_MCNTR_RST_MASK        0x00000100U /**< Enable the Metric
 400                                                         Counter Reset */
 401 #define XAPM_SICR_LOAD_MASK             0x00000002U /**< Load the Sample Interval
 402                                                         *  Register Value into the
 403                                                         *  counter */
 404 #define XAPM_SICR_ENABLE_MASK           0x00000001U /**< Enable the downcounter */
 405
 406 /*@}*/
 407
 408
 409 /** @name Interrupt Status/Enable Register Bit Definitions and Masks
 410  *  @{
 411  */
 412
 413 #define XAPM_IXR_MC9_OVERFLOW_MASK      0x00001000U     /**< Metric Counter 9
 414                                                           *  Overflow> */
 415 #define XAPM_IXR_MC8_OVERFLOW_MASK      0x00000800U     /**< Metric Counter 8
 416                                                           *  Overflow> */
 417 #define XAPM_IXR_MC7_OVERFLOW_MASK      0x00000400U     /**< Metric Counter 7
 418                                                           *  Overflow> */
 419 #define XAPM_IXR_MC6_OVERFLOW_MASK      0x00000200U     /**< Metric Counter 6
 420                                                           *  Overflow> */
 421 #define XAPM_IXR_MC5_OVERFLOW_MASK      0x00000100U     /**< Metric Counter 5
 422                                                           *  Overflow> */
 423 #define XAPM_IXR_MC4_OVERFLOW_MASK      0x00000080U     /**< Metric Counter 4
 424                                                           *  Overflow> */
 425 #define XAPM_IXR_MC3_OVERFLOW_MASK      0x00000040U     /**< Metric Counter 3
 426                                                           *  Overflow> */
 427 #define XAPM_IXR_MC2_OVERFLOW_MASK      0x00000020U     /**< Metric Counter 2
 428                                                           *  Overflow> */
 429 #define XAPM_IXR_MC1_OVERFLOW_MASK      0x00000010U     /**< Metric Counter 1
 430                                                           *  Overflow> */
 431 #define XAPM_IXR_MC0_OVERFLOW_MASK      0x00000008U     /**< Metric Counter 0
 432                                                           *  Overflow> */
 433 #define XAPM_IXR_FIFO_FULL_MASK         0x00000004U     /**< Event Log FIFO
 434                                                           *  full> */
 435 #define XAPM_IXR_SIC_OVERFLOW_MASK      0x00000002U     /**< Sample Interval
 436                                                           * Counter Overflow> */
 437 #define XAPM_IXR_GCC_OVERFLOW_MASK      0x00000001U     /**< Global Clock Counter
 438                                                           *  Overflow> */
 439 #define XAPM_IXR_ALL_MASK               (XAPM_IXR_SIC_OVERFLOW_MASK | \
 440                                         XAPM_IXR_GCC_OVERFLOW_MASK |  \
 441                                         XAPM_IXR_FIFO_FULL_MASK | \
 442                                         XAPM_IXR_MC0_OVERFLOW_MASK | \
 443                                         XAPM_IXR_MC1_OVERFLOW_MASK | \
 444                                         XAPM_IXR_MC2_OVERFLOW_MASK | \
 445                                         XAPM_IXR_MC3_OVERFLOW_MASK | \
 446                                         XAPM_IXR_MC4_OVERFLOW_MASK | \
 447                                         XAPM_IXR_MC5_OVERFLOW_MASK | \
 448                                         XAPM_IXR_MC6_OVERFLOW_MASK | \
 449                                         XAPM_IXR_MC7_OVERFLOW_MASK | \
 450                                         XAPM_IXR_MC8_OVERFLOW_MASK | \
 451                                         XAPM_IXR_MC9_OVERFLOW_MASK)
 452 /* @} */
 453
 454 /**
 455  * @name AXI Monitor Control Register mask(s)
 456  * @{
 457  */
 458
 459 #define XAPM_CR_FIFO_RESET_MASK                 0x02000000U
 460                                                 /**< FIFO Reset */
 461 #define XAPM_CR_GCC_RESET_MASK                  0x00020000U
 462                                                 /**< Global Clk
 463                                                   Counter Reset */
 464 #define XAPM_CR_GCC_ENABLE_MASK                 0x00010000U
 465                                                 /**< Global Clk
 466                                                    Counter Enable */
 467 #define XAPM_CR_EVTLOG_EXTTRIGGER_MASK          0x00000200U
 468                                                 /**< Enable External trigger
 469                                                 to start event Log */
 470 #define XAPM_CR_EVENTLOG_ENABLE_MASK            0x00000100U
 471                                                 /**< Event Log Enable */
 472
 473 #define XAPM_CR_RDLATENCY_END_MASK              0x00000080U
 474                                                 /**< Write Latency
 475                                                         End point */
 476 #define XAPM_CR_RDLATENCY_START_MASK            0x00000040U
 477                                                 /**< Read Latency
 478                                                         Start point */
 479 #define XAPM_CR_WRLATENCY_END_MASK              0x00000020U
 480                                                 /**< Write Latency
 481                                                         End point */
 482 #define XAPM_CR_WRLATENCY_START_MASK            0x00000010U
 483                                                 /**< Write Latency
 484                                                         Start point */
 485 #define XAPM_CR_IDFILTER_ENABLE_MASK            0x00000008U
 486                                                 /**< ID Filter Enable */
 487
 488 #define XAPM_CR_MCNTR_EXTTRIGGER_MASK           0x00000004U
 489                                                 /**< Enable External
 490                                                    trigger to start
 491                                                    Metric Counters  */
 492 #define XAPM_CR_MCNTR_RESET_MASK                0x00000002U
 493                                                 /**< Metrics Counter
 494                                                    Reset */
 495 #define XAPM_CR_MCNTR_ENABLE_MASK               0x00000001U
 496                                                 /**< Metrics Counter
 497                                                    Enable */
 498 /*@}*/
 499
 500 /**
 501  * @name AXI Monitor ID Register mask(s)
 502  * @{
 503  */
 504
 505 #define XAPM_ID_RID_MASK                        0xFFFF0000U /**< Read ID */
 506
 507 #define XAPM_ID_WID_MASK                        0x0000FFFFU /**< Write ID */
 508
 509 /*@}*/
 510
 511 /**
 512  * @name AXI Monitor ID Mask Register mask(s)
 513  * @{
 514  */
 515
 516 #define XAPM_MASKID_RID_MASK                    0xFFFF0000U /**< Read ID Mask */
 517
 518 #define XAPM_MASKID_WID_MASK                    0x0000FFFFU /**< Write ID Mask*/
 519
 520 /*@}*/
 521
 522 /**************************** Type Definitions *******************************/
 523
 524 /***************** Macros (Inline Functions) Definitions *********************/
 525
 526 /*****************************************************************************/
 527 /**
 528 *
 529 * Read a register of the AXI Performance Monitor device. This macro provides
 530 * register access to all registers using the register offsets defined above.
 531 *
 532 * @param        BaseAddress contains the base address of the device.
 533 * @param        RegOffset is the offset of the register to read.
 534 *
 535 * @return       The contents of the register.
 536 *
 537 * @note         C-style Signature:
 538 *               u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
 539 *
 540 ******************************************************************************/
 541 #define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
 542                 (Xil_In32((BaseAddress) + (RegOffset)))
 543
 544 /*****************************************************************************/
 545 /**
 546 *
 547 * Write a register of the AXI Performance Monitor device. This macro provides
 548 * register access to all registers using the register offsets defined above.
 549 *
 550 * @param        BaseAddress contains the base address of the device.
 551 * @param        RegOffset is the offset of the register to write.
 552 * @param        Data is the value to write to the register.
 553 *
 554 * @return       None.
 555 *
 556 * @note         C-style Signature:
 557 *               void XAxiPmon_WriteReg(u32 BaseAddress,
 558 *                                       u32 RegOffset,u32 Data)
 559 *
 560 ******************************************************************************/
 561 #define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
 562                 (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
 563
 564 /************************** Function Prototypes ******************************/
 565
 566 #ifdef __cplusplus
 567 }
 568 #endif
 569
 570 #endif  /* End of protection macro. */
 571 /** @} */