1 ;*************************************************
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3 ;* Part one of the system initialization code, contains low-level
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4 ;* initialization, plain thumb variant.
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6 ;* Copyright 2008 IAR Systems. All rights reserved.
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8 ;* $Revision: 50748 $
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10 ;*************************************************
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13 ; The modules in this file are included in the libraries, and may be replaced
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14 ; by any user-defined modules that define the PUBLIC symbol _program_start or
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15 ; a user defined start symbol.
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16 ; To override the cstartup defined in the library, simply add your modified
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17 ; version to the workbench project.
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19 ; The vector table is normally located at address 0.
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20 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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21 ; The name "__vector_table" has special meaning for C-SPY:
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22 ; it is where the SP start value is found, and the NVIC vector
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23 ; table register (VTOR) is initialized to this address if != 0.
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25 ; Cortex-M version with interrupt handler for XMC4500 from Infineon
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28 MODULE ?vector_table
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30 AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
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34 ;; Forward declaration of sections.
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35 SECTION CSTACK:DATA:NOROOT(3)
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37 SECTION .intvec:CODE:NOROOT(2)
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39 EXTERN __iar_program_start
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40 PUBLIC __vector_table
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44 __iar_init$$done: ; The vector table is not needed
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45 ; until after copy initialization is done
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52 DCD HardFault_Handler
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53 DCD MemManage_Handler
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54 DCD BusFault_Handler
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55 DCD UsageFault_Handler
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61 DCD DebugMon_Handler
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66 ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
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67 DCD SCU_0_IRQHandler ; Handler name for SR SCU_0
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68 DCD ERU0_0_IRQHandler ; Handler name for SR ERU0_0
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69 DCD ERU0_1_IRQHandler ; Handler name for SR ERU0_1
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70 DCD ERU0_2_IRQHandler ; Handler name for SR ERU0_2
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71 DCD ERU0_3_IRQHandler ; Handler name for SR ERU0_3
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72 DCD ERU1_0_IRQHandler ; Handler name for SR ERU1_0
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73 DCD ERU1_1_IRQHandler ; Handler name for SR ERU1_1
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74 DCD ERU1_2_IRQHandler ; Handler name for SR ERU1_2
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75 DCD ERU1_3_IRQHandler ; Handler name for SR ERU1_3
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76 DCD 0 ; Not Available
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77 DCD 0 ; Not Available
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78 DCD 0 ; Not Available
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79 DCD PMU0_0_IRQHandler ; Handler name for SR PMU0_0
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80 DCD 0 ; Not Available
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81 DCD VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
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82 DCD VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
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83 DCD VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
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84 DCD VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
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85 DCD VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
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86 DCD VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
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87 DCD VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
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88 DCD VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
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89 DCD VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
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90 DCD VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
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91 DCD VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
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92 DCD VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
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93 DCD VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
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94 DCD VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
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95 DCD VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
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96 DCD VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
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97 DCD VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
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98 DCD VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
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99 DCD VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
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100 DCD VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
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101 DCD DSD0_0_IRQHandler ; Handler name for SR DSD0_0
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102 DCD DSD0_1_IRQHandler ; Handler name for SR DSD0_1
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103 DCD DSD0_2_IRQHandler ; Handler name for SR DSD0_2
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104 DCD DSD0_3_IRQHandler ; Handler name for SR DSD0_3
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105 DCD DSD0_4_IRQHandler ; Handler name for SR DSD0_4
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106 DCD DSD0_5_IRQHandler ; Handler name for SR DSD0_5
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107 DCD DSD0_6_IRQHandler ; Handler name for SR DSD0_6
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108 DCD DSD0_7_IRQHandler ; Handler name for SR DSD0_7
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109 DCD DAC0_0_IRQHandler ; Handler name for SR DAC0_0
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110 DCD DAC0_1_IRQHandler ; Handler name for SR DAC0_0
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111 DCD CCU40_0_IRQHandler ; Handler name for SR CCU40_0
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112 DCD CCU40_1_IRQHandler ; Handler name for SR CCU40_1
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113 DCD CCU40_2_IRQHandler ; Handler name for SR CCU40_2
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114 DCD CCU40_3_IRQHandler ; Handler name for SR CCU40_3
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115 DCD CCU41_0_IRQHandler ; Handler name for SR CCU41_0
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116 DCD CCU41_1_IRQHandler ; Handler name for SR CCU41_1
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117 DCD CCU41_2_IRQHandler ; Handler name for SR CCU41_2
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118 DCD CCU41_3_IRQHandler ; Handler name for SR CCU41_3
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119 DCD CCU42_0_IRQHandler ; Handler name for SR CCU42_0
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120 DCD CCU42_1_IRQHandler ; Handler name for SR CCU42_1
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121 DCD CCU42_2_IRQHandler ; Handler name for SR CCU42_2
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122 DCD CCU42_3_IRQHandler ; Handler name for SR CCU42_3
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123 DCD CCU43_0_IRQHandler ; Handler name for SR CCU43_0
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124 DCD CCU43_1_IRQHandler ; Handler name for SR CCU43_1
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125 DCD CCU43_2_IRQHandler ; Handler name for SR CCU43_2
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126 DCD CCU43_3_IRQHandler ; Handler name for SR CCU43_3
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127 DCD CCU80_0_IRQHandler ; Handler name for SR CCU80_0
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128 DCD CCU80_1_IRQHandler ; Handler name for SR CCU80_1
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129 DCD CCU80_2_IRQHandler ; Handler name for SR CCU80_2
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130 DCD CCU80_3_IRQHandler ; Handler name for SR CCU80_3
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131 DCD CCU81_0_IRQHandler ; Handler name for SR CCU81_0
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132 DCD CCU81_1_IRQHandler ; Handler name for SR CCU81_1
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133 DCD CCU81_2_IRQHandler ; Handler name for SR CCU81_2
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134 DCD CCU81_3_IRQHandler ; Handler name for SR CCU81_3
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135 DCD POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
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136 DCD POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
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137 DCD POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
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138 DCD POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
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139 DCD 0 ; Not Available
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140 DCD 0 ; Not Available
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141 DCD 0 ; Not Available
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142 DCD 0 ; Not Available
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143 DCD CAN0_0_IRQHandler ; Handler name for SR CAN0_0
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144 DCD CAN0_1_IRQHandler ; Handler name for SR CAN0_1
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145 DCD CAN0_2_IRQHandler ; Handler name for SR CAN0_2
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146 DCD CAN0_3_IRQHandler ; Handler name for SR CAN0_3
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147 DCD CAN0_4_IRQHandler ; Handler name for SR CAN0_4
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148 DCD CAN0_5_IRQHandler ; Handler name for SR CAN0_5
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149 DCD CAN0_6_IRQHandler ; Handler name for SR CAN0_6
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150 DCD CAN0_7_IRQHandler ; Handler name for SR CAN0_7
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151 DCD USIC0_0_IRQHandler ; Handler name for SR USIC0_0
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152 DCD USIC0_1_IRQHandler ; Handler name for SR USIC0_1
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153 DCD USIC0_2_IRQHandler ; Handler name for SR USIC0_2
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154 DCD USIC0_3_IRQHandler ; Handler name for SR USIC0_3
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155 DCD USIC0_4_IRQHandler ; Handler name for SR USIC0_4
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156 DCD USIC0_5_IRQHandler ; Handler name for SR USIC0_5
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157 DCD USIC1_0_IRQHandler ; Handler name for SR USIC1_0
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158 DCD USIC1_1_IRQHandler ; Handler name for SR USIC1_1
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159 DCD USIC1_2_IRQHandler ; Handler name for SR USIC1_2
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160 DCD USIC1_3_IRQHandler ; Handler name for SR USIC1_3
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161 DCD USIC1_4_IRQHandler ; Handler name for SR USIC1_4
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162 DCD USIC1_5_IRQHandler ; Handler name for SR USIC1_5
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163 DCD USIC2_0_IRQHandler ; Handler name for SR USIC2_0
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164 DCD USIC2_1_IRQHandler ; Handler name for SR USIC2_1
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165 DCD USIC2_2_IRQHandler ; Handler name for SR USIC2_2
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166 DCD USIC2_3_IRQHandler ; Handler name for SR USIC2_3
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167 DCD USIC2_4_IRQHandler ; Handler name for SR USIC2_4
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168 DCD USIC2_5_IRQHandler ; Handler name for SR USIC2_5
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169 DCD LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
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170 DCD 0 ; Not Available
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171 DCD FCE0_0_IRQHandler ; Handler name for SR FCE0_0
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172 DCD GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
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173 DCD SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
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174 DCD USB0_0_IRQHandler ; Handler name for SR USB0_0
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175 DCD ETH0_0_IRQHandler ; Handler name for SR ETH0_0
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176 DCD 0 ; Not Available
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177 DCD GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
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178 DCD 0 ; Not Available
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183 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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185 ;; Default interrupt handlers.
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188 PUBWEAK NMI_Handler
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189 PUBWEAK HardFault_Handler
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190 PUBWEAK MemManage_Handler
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191 PUBWEAK BusFault_Handler
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192 PUBWEAK UsageFault_Handler
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193 PUBWEAK SVC_Handler
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194 PUBWEAK DebugMon_Handler
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195 PUBWEAK PendSV_Handler
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196 PUBWEAK SysTick_Handler
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197 ;; XMC4500 interrupt handlers
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198 PUBWEAK SCU_0_IRQHandler
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199 PUBWEAK ERU0_0_IRQHandler
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200 PUBWEAK ERU0_1_IRQHandler
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201 PUBWEAK ERU0_2_IRQHandler
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202 PUBWEAK ERU0_3_IRQHandler
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203 PUBWEAK ERU1_0_IRQHandler
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204 PUBWEAK ERU1_1_IRQHandler
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205 PUBWEAK ERU1_2_IRQHandler
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206 PUBWEAK ERU1_3_IRQHandler
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207 PUBWEAK PMU0_0_IRQHandler
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208 PUBWEAK PMU0_1_IRQHandler
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209 PUBWEAK VADC0_C0_0_IRQHandler
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210 PUBWEAK VADC0_C0_1_IRQHandler
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211 PUBWEAK VADC0_C0_2_IRQHandler
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212 PUBWEAK VADC0_C0_3_IRQHandler
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213 PUBWEAK VADC0_G0_0_IRQHandler
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214 PUBWEAK VADC0_G0_1_IRQHandler
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215 PUBWEAK VADC0_G0_2_IRQHandler
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216 PUBWEAK VADC0_G0_3_IRQHandler
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217 PUBWEAK VADC0_G1_0_IRQHandler
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218 PUBWEAK VADC0_G1_1_IRQHandler
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219 PUBWEAK VADC0_G1_2_IRQHandler
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220 PUBWEAK VADC0_G1_3_IRQHandler
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221 PUBWEAK VADC0_G2_0_IRQHandler
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222 PUBWEAK VADC0_G2_1_IRQHandler
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223 PUBWEAK VADC0_G2_2_IRQHandler
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224 PUBWEAK VADC0_G2_3_IRQHandler
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225 PUBWEAK VADC0_G3_0_IRQHandler
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226 PUBWEAK VADC0_G3_1_IRQHandler
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227 PUBWEAK VADC0_G3_2_IRQHandler
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228 PUBWEAK VADC0_G3_3_IRQHandler
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229 PUBWEAK DSD0_0_IRQHandler
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230 PUBWEAK DSD0_1_IRQHandler
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231 PUBWEAK DSD0_2_IRQHandler
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232 PUBWEAK DSD0_3_IRQHandler
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233 PUBWEAK DSD0_4_IRQHandler
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234 PUBWEAK DSD0_5_IRQHandler
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235 PUBWEAK DSD0_6_IRQHandler
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236 PUBWEAK DSD0_7_IRQHandler
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237 PUBWEAK DAC0_0_IRQHandler
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238 PUBWEAK DAC0_1_IRQHandler
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239 PUBWEAK CCU40_0_IRQHandler
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240 PUBWEAK CCU40_1_IRQHandler
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241 PUBWEAK CCU40_2_IRQHandler
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242 PUBWEAK CCU40_3_IRQHandler
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243 PUBWEAK CCU41_0_IRQHandler
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244 PUBWEAK CCU41_1_IRQHandler
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245 PUBWEAK CCU41_2_IRQHandler
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246 PUBWEAK CCU41_3_IRQHandler
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247 PUBWEAK CCU42_0_IRQHandler
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248 PUBWEAK CCU42_1_IRQHandler
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249 PUBWEAK CCU42_2_IRQHandler
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250 PUBWEAK CCU42_3_IRQHandler
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251 PUBWEAK CCU43_0_IRQHandler
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252 PUBWEAK CCU43_1_IRQHandler
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253 PUBWEAK CCU43_2_IRQHandler
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254 PUBWEAK CCU43_3_IRQHandler
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255 PUBWEAK CCU80_0_IRQHandler
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256 PUBWEAK CCU80_1_IRQHandler
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257 PUBWEAK CCU80_2_IRQHandler
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258 PUBWEAK CCU80_3_IRQHandler
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259 PUBWEAK CCU81_0_IRQHandler
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260 PUBWEAK CCU81_1_IRQHandler
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261 PUBWEAK CCU81_2_IRQHandler
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262 PUBWEAK CCU81_3_IRQHandler
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263 PUBWEAK POSIF0_0_IRQHandler
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264 PUBWEAK POSIF0_1_IRQHandler
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265 PUBWEAK POSIF1_0_IRQHandler
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266 PUBWEAK POSIF1_1_IRQHandler
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267 PUBWEAK CAN0_0_IRQHandler
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268 PUBWEAK CAN0_1_IRQHandler
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269 PUBWEAK CAN0_2_IRQHandler
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270 PUBWEAK CAN0_3_IRQHandler
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271 PUBWEAK CAN0_4_IRQHandler
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272 PUBWEAK CAN0_5_IRQHandler
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273 PUBWEAK CAN0_6_IRQHandler
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274 PUBWEAK CAN0_7_IRQHandler
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275 PUBWEAK USIC0_0_IRQHandler
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276 PUBWEAK USIC0_1_IRQHandler
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277 PUBWEAK USIC0_2_IRQHandler
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278 PUBWEAK USIC0_3_IRQHandler
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279 PUBWEAK USIC0_4_IRQHandler
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280 PUBWEAK USIC0_5_IRQHandler
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281 PUBWEAK USIC1_0_IRQHandler
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282 PUBWEAK USIC1_1_IRQHandler
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283 PUBWEAK USIC1_2_IRQHandler
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284 PUBWEAK USIC1_3_IRQHandler
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285 PUBWEAK USIC1_4_IRQHandler
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286 PUBWEAK USIC1_5_IRQHandler
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287 PUBWEAK USIC2_0_IRQHandler
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288 PUBWEAK USIC2_1_IRQHandler
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289 PUBWEAK USIC2_2_IRQHandler
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290 PUBWEAK USIC2_3_IRQHandler
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291 PUBWEAK USIC2_4_IRQHandler
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292 PUBWEAK USIC2_5_IRQHandler
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293 PUBWEAK LEDTS0_0_IRQHandler
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294 PUBWEAK FCE0_0_IRQHandler
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295 PUBWEAK GPDMA0_0_IRQHandler
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296 PUBWEAK SDMMC0_0_IRQHandler
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297 PUBWEAK USB0_0_IRQHandler
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298 PUBWEAK ETH0_0_IRQHandler
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299 PUBWEAK GPDMA1_0_IRQHandler
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301 SECTION .text:CODE:REORDER(2)
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325 VADC0_C0_0_IRQHandler
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326 VADC0_C0_1_IRQHandler
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327 VADC0_C0_2_IRQHandler
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328 VADC0_C0_3_IRQHandler
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329 VADC0_G0_0_IRQHandler
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330 VADC0_G0_1_IRQHandler
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331 VADC0_G0_2_IRQHandler
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332 VADC0_G0_3_IRQHandler
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333 VADC0_G1_0_IRQHandler
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334 VADC0_G1_1_IRQHandler
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335 VADC0_G1_2_IRQHandler
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336 VADC0_G1_3_IRQHandler
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337 VADC0_G2_0_IRQHandler
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338 VADC0_G2_1_IRQHandler
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339 VADC0_G2_2_IRQHandler
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340 VADC0_G2_3_IRQHandler
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341 VADC0_G3_0_IRQHandler
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342 VADC0_G3_1_IRQHandler
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343 VADC0_G3_2_IRQHandler
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344 VADC0_G3_3_IRQHandler
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379 POSIF0_0_IRQHandler
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380 POSIF0_1_IRQHandler
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381 POSIF1_0_IRQHandler
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382 POSIF1_1_IRQHandler
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409 LEDTS0_0_IRQHandler
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411 GPDMA0_0_IRQHandler
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412 SDMMC0_0_IRQHandler
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415 GPDMA1_0_IRQHandler
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418 NOCALL Default_Handler
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421 PREF_PCON EQU 0x58004000
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422 SCU_GCU_PEEN EQU 0x5000413C
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423 SCU_GCU_PEFLAG EQU 0x50004150
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425 SECTION .text:CODE:REORDER(2)
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428 ; A11 workaround for branch prediction and parity
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429 LDR R0,=PREF_PCON /* switch off branch prediction required in A11 step to use cached memory*/
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431 ORR R1,R1,#0x00010000
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434 /* Clear existing parity errors if any required in A11 step */
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435 LDR R0,=SCU_GCU_PEFLAG
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439 /* Disable parity required in A11 step*/
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440 LDR R0,=SCU_GCU_PEEN
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443 B __iar_program_start
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