1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2011, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 IAR startup file for AT91SAMA5D3X microcontrollers.
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36 ;; Forward declaration of sections.
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37 SECTION IRQ_STACK:DATA:NOROOT(2)
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38 SECTION CSTACK:DATA:NOROOT(3)
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40 //------------------------------------------------------------------------------
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42 //------------------------------------------------------------------------------
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44 //#define __ASSEMBLY__
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45 //#include "board.h"
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47 //------------------------------------------------------------------------------
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49 //------------------------------------------------------------------------------
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51 #define AIC 0xFFFFF000
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52 #define AIC_IVR 0x10
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53 #define AIC_EOICR 0x38
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55 #define ARM_MODE_ABT 0x17
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56 #define ARM_MODE_FIQ 0x11
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57 #define ARM_MODE_IRQ 0x12
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58 #define ARM_MODE_SVC 0x13
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59 #define ARM_MODE_SYS 0x1F
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64 //------------------------------------------------------------------------------
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66 //------------------------------------------------------------------------------
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71 SECTION .vectors:CODE:NOROOT(2)
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76 EXTERN Undefined_Handler
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78 EXTERN Prefetch_Handler
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79 EXTERN Abort_Handler
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84 __iar_init$$done: ; The interrupt vector is not needed
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85 ; until after copy initialization is done
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88 ; All default exception handlers (except reset) are
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89 ; defined as weak symbol definitions.
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90 ; If a handler is defined by the application it will take precedence.
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91 LDR pc, =resetHandler ; Reset
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92 LDR pc, Undefined_Addr ; Undefined instructions
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93 LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
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94 LDR pc, Prefetch_Addr ; Prefetch abort
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95 LDR pc, Abort_Addr ; Data abort
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97 LDR pc, =irqHandler ; IRQ
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98 LDR pc, FIQ_Addr ; FIQ
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100 Undefined_Addr: DCD Undefined_Handler
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101 SWI_Addr: DCD SWI_Handler
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102 Prefetch_Addr: DCD Prefetch_Handler
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103 Abort_Addr: DCD Abort_Handler
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104 FIQ_Addr: DCD FIQ_Handler
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107 Handles incoming interrupt requests by branching to the corresponding
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108 handler, as defined in the AIC. Supports interrupt nesting.
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111 /* Save interrupt context on the stack to allow nesting */
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115 STMFD sp!, {r0, lr}
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117 /* Write in the IVR to support Protect Mode */
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119 LDR r0, [r14, #AIC_IVR]
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120 STR lr, [r14, #AIC_IVR]
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122 /* Branch to interrupt handler in Supervisor mode */
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123 MSR CPSR_c, #ARM_MODE_SYS
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124 STMFD sp!, {r1-r3, r4, r12, lr}
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126 /* Check for 8-byte alignment and save lr plus a */
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127 /* word to indicate the stack adjustment used (0 or 4) */
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130 STMFD sp!, {r1, lr}
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134 LDMIA sp!, {r1, lr}
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137 LDMIA sp!, {r1-r3, r4, r12, lr}
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138 MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
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140 /* Acknowledge interrupt */
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142 STR lr, [r14, #AIC_EOICR]
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144 /* Restore interrupt context and branch back to calling code */
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145 LDMIA sp!, {r0, lr}
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151 After a reset, execution starts here, the mode is ARM, supervisor
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152 with interrupts disabled.
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153 Initializes the chip and branches to the main() function.
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155 SECTION .cstartup:CODE:NOROOT(2)
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157 PUBLIC resetHandler
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158 EXTERN LowLevelInit
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160 REQUIRE resetVector
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166 /* - Enable access to CP10 and CP11 in CP15.CACR */
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167 mrc p15, 0, r0, c1, c0, 2
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168 orr r0, r0, #0xf00000
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169 mcr p15, 0, r0, c1, c0, 2
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170 /* - Enable access to CP10 and CP11 in CP15.NSACR */
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171 /* - Set FPEXC.EN (B30) */
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173 orr r0, r0, #0x40000000
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175 /* Set pc to actual code location (i.e. not in remap zone) */
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178 /* Perform low-level initialization of the chip using LowLevelInit() */
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180 LDR r0, =LowLevelInit
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181 LDR r4, =SFE(CSTACK)
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185 /* Set up the interrupt stack pointer. */
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186 MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
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187 LDR sp, =SFE(IRQ_STACK)
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189 /* Set up the SYS stack pointer. */
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190 MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
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191 LDR sp, =SFE(CSTACK)
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193 /* Branch to main() */
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197 /* Loop indefinitely when program is finished */
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