2 * @brief Open Host Controller Interface
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5 * Copyright(C) NXP Semiconductors, 2012
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6 * All rights reserved.
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * LPC products. This software is supplied "AS IS" without any warranties of
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12 * any kind, and NXP Semiconductors and its licensor disclaim any and
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13 * all warranties, express or implied, including all implied warranties of
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14 * merchantability, fitness for a particular purpose and non-infringement of
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15 * intellectual property rights. NXP Semiconductors assumes no responsibility
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16 * or liability for the use of the software, conveys no license or rights under any
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17 * patent, copyright, mask work right, or any other intellectual property rights in
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18 * or to any products. NXP Semiconductors reserves the right to make changes
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19 * in the software without notification. NXP Semiconductors also makes no
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20 * representation or warranty that such application will be suitable for the
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21 * specified use without further testing or modification.
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24 * Permission to use, copy, modify, and distribute this software and its
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25 * documentation is hereby granted, under NXP Semiconductors' and its
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26 * licensor's relevant copyrights in the software, without fee, provided that it
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27 * is used in conjunction with NXP Semiconductors microcontrollers. This
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28 * copyright, permission, and disclaimer notice must appear in all copies of
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31 /** @ingroup Group_HCD
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32 * @defgroup Host_OHCI Open Host Controller Interface Driver
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36 #ifndef __LPC_OHCI_H__
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37 #define __LPC_OHCI_H__
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39 #ifndef __LPC_OHCI_C__ // TODO INCLUDE FROM OHCI.C
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40 #error OHCI.h is private header and can only be included by OHCI.c, try to include HCD.h instead
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43 #ifdef __TEST__ // suppress static/inline for Testing purpose
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48 #define MAX_ED HCD_MAX_ENDPOINT
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49 #define MAX_GTD (MAX_ED + 3)
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50 #define MAX_STATIC_ED 3 /* Serve as list head, fixed, not configurable */
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58 #define CONTROL_BULK_SERVICE_RATIO 3 /* Control Bulk transfer ratio 0 = 1:1 - 1 = 2:1 - 2 = 3:1 - 3 = 4:1 */
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59 #define INTERRUPT_ROUTING 0 /* Host interrupt routing 0 = IRQ - 1 = SMI */
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60 #define REMOTE_WAKEUP_CONNECTED NO /* Remote wakeup connected */
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61 #define REMOTE_WAKEUP_ENABLE NO /* Remote wakeup enable */
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63 #define SCHEDULING_OVRERRUN_INTERRUPT NO
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65 #define SOF_INTERRUPT NO
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66 #define RESUME_DETECT_INTERRUPT NO
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67 #define UNRECOVERABLE_ERROR_INTERRUPT NO
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68 #define FRAMENUMBER_OVERFLOW_INTERRUPT NO
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70 #define OWNERSHIP_CHANGE_INTERRUPT NO
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72 #define FRAME_INTERVAL 0x2EDF /* Reset default value */
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73 #define HC_FMINTERVAL_DEFAULT ((((6 * (FRAME_INTERVAL - 210)) / 7) << 16) | FRAME_INTERVAL)
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75 #define PERIODIC_START 0x00002A27UL /* 10% off from FRAME_INTERVAL */
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77 #define PORT_POWER_SWITCHING NO
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78 #define PER_PORT_POWER_SWITCHING NO
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79 #define PER_PORT_OVER_CURRENT_REPORT NO
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80 #define OVER_CURRENT_PROTECTION NO
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82 #define INTERRUPT_1ms_LIST_HEAD 0
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83 #define INTERRUPT_2ms_LIST_HEAD 1
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84 #define INTERRUPT_4ms_LIST_HEAD 3
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85 #define INTERRUPT_8ms_LIST_HEAD 7
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86 #define INTERRUPT_16ms_LIST_HEAD 15
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87 #define INTERRUPT_32ms_LIST_HEAD 31
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88 #define ISO_LIST_HEAD (MAX_STATIC_ED - 3)
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89 #define CONTROL_LIST_HEAD (MAX_STATIC_ED - 2)
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90 #define BULK_LIST_HEAD (MAX_STATIC_ED - 1)
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91 #define TD_MAX_XFER_LENGTH 0x2000
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93 #define TD_NoInterruptOnComplete (7)
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95 #define HC_REVISION 0x000000FFUL
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97 #define HC_FM_REMAIN 0x00003FFFUL /* Frame remaining */
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99 #define HC_FM_NUMBER 0x0000FFFFUL /* Frame Number */
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101 #define HC_CONTROL_ControlBulkServiceRatio 0x00000003UL /* Control/Bulk ratio */
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102 #define HC_CONTROL_PeriodListEnable 0x00000004UL /* Periodic List Enable */
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103 #define HC_CONTROL_IsochronousEnable 0x00000008UL /* Isochronous Enable */
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104 #define HC_CONTROL_ControlListEnable 0x00000010UL /* Control List Enable */
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105 #define HC_CONTROL_BulkListEnable 0x00000020UL /* Bulk List Enable */
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106 #define HC_CONTROL_HostControllerFunctionalState 0x000000C0UL /* Host Controller Functional State */
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107 #define HC_CONTROL_InterruptRouting 0x00000100UL /* Interrupt Routing */
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108 #define HC_CONTROL_RemoteWakeupConnected 0x00000200UL /* Remote Wakeup Connected */
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109 #define HC_CONTROL_RemoteWakeupEnable 0x00000400UL /* Remote Wakeup Enable */
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111 #define HC_HOST_RESET 0x00000000UL /* Reset state */
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112 #define HC_HOST_RESUME 0X00000001UL /* Resume state */
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113 #define HC_HOST_OPERATIONAL 0x00000002UL /* Operational state */
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114 #define HC_HOST_SUSPEND 0x00000003UL /* Suspend state */
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116 #define HC_COMMAND_STATUS_HostControllerReset 0x00000001UL /* Host Controller Reset */
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117 #define HC_COMMAND_STATUS_ControlListFilled 0x00000002UL /* Control List Filled */
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118 #define HC_COMMAND_STATUS_BulkListFilled 0x00000004UL /* Bulk List Filled */
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120 #define HC_INTERRUPT_SchedulingOverrun 0x00000001UL /* Scheduling Overrun */
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121 #define HC_INTERRUPT_WritebackDoneHead 0x00000002UL /* Writeback DoneHead */
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122 #define HC_INTERRUPT_StartofFrame 0x00000004UL /* Start of Frame */
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123 #define HC_INTERRUPT_ResumeDetected 0x00000008UL /* Resume Detect */
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124 #define HC_INTERRUPT_UnrecoverableError 0x00000010UL /* Unrecoverable error */
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125 #define HC_INTERRUPT_FrameNumberOverflow 0x00000020UL /* Frame Number Overflow */
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126 #define HC_INTERRUPT_RootHubStatusChange 0x00000040UL /* Root Hub Status Change */
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127 #define HC_INTERRUPT_OwnershipChange 0x40000000UL /* Ownership Change */
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128 #define HC_INTERRUPT_MasterInterruptEnable 0x80000000UL /* Master Interrupt Enable */
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129 #define HC_INTERRUPT_ALL 0xC000007FUL /* All interrupts */
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131 #define HC_RH_DESCRIPTORA_NumberDownstreamPorts 0x000000FFUL /* Number of downstream ports */
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132 #define HC_RH_DESCRIPTORA_PowerSwitchingMode 0x00000100UL /* Power Switching Mode */
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133 #define HC_RH_DESCRIPTORA_NoPowerSwitching 0x00000200UL /* No Power Switching */
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134 #define HC_RH_DESCRIPTORA_OverCurrentProtectionMode 0x00000800UL /* OverCurrent Protection Mode */
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135 #define HC_RH_DESCRIPTORA_NoOverCurrentProtection 0x00001000UL /* No OverCurrent Protection */
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136 #define HC_RH_DESCRIPTORA_PowerOnToPowerGoodTime 0xFF000000UL /* Power On To Power Good Time */
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138 #define HC_RH_DESCRIPTORB_PortPowerControlMask 0xFFFF0000UL /* Port Power Control Mask */
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139 #define HC_RH_DESCRIPTORB_DeviceRemovable 0x0000FFFFUL /* Device Removable */
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141 #define HC_RH_STATUS_LocalPowerStatus 0x00000001UL /* R: Local Power Status - W: Clear Global Power */
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142 #define HC_RH_STATUS_LocalPowerStatusChange 0x00010000UL /* R: Local Power Status Change - W: Set Global Power */
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143 #define HC_RH_STATUS_DeviceRemoteWakeupEnable 0x00008000UL /* W: Set Remote Wakeup Enable */
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145 #define HC_RH_PORT_STATUS_CurrentConnectStatus 0x00000001UL /* R: Current Connect Status - W: Clear Port Enable */
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146 #define HC_RH_PORT_STATUS_PowerEnableStatus 0x00000002UL /* R: Port Enable Status - W: Set Port Enable */
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147 #define HC_RH_PORT_STATUS_PortSuspendStatus 0x00000004UL /* R: Port Suspend Status - W: Set Port Suspend */
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148 #define HC_RH_PORT_STATUS_PortOverCurrentIndicator 0x00000008UL /* R: Port OverCurrent Indicator- W: Clear Suspend Status */
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149 #define HC_RH_PORT_STATUS_PortResetStatus 0x00000010UL /* R: Port Reset Status - W: Set Port Reset */
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150 #define HC_RH_PORT_STATUS_PortPowerStatus 0x00000100UL /* R: Port Power Status - W: Set Port Power */
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151 #define HC_RH_PORT_STATUS_LowSpeedDeviceAttached 0x00000200UL /* R: Low Speed Device Attached - W: Clear Port Power */
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153 #define HC_RH_PORT_STATUS_ConnectStatusChange 0x00010000UL /* Connect Status Change */
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154 #define HC_RH_PORT_STATUS_PortEnableStatusChange 0x00020000UL /* Port Enable Status Change */
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155 #define HC_RH_PORT_STATUS_PortSuspendStatusChange 0x00040000UL /* Port Suspend Status Change */
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156 #define HC_RH_PORT_STATUS_OverCurrentIndicatorChange 0x00080000UL /* OverCurrent Indicator Change */
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157 #define HC_RH_PORT_STATUS_PortResetStatusChange 0x00100000UL /* Port Reset Status Change */
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158 #define HC_RH_PORT_STATUS_StatusChangeMask (HC_RH_PORT_STATUS_ConnectStatusChange | \
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159 HC_RH_PORT_STATUS_PortEnableStatusChange | \
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160 HC_RH_PORT_STATUS_PortSuspendStatusChange | \
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161 HC_RH_PORT_STATUS_OverCurrentIndicatorChange | \
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162 HC_RH_PORT_STATUS_PortResetStatusChange)
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164 typedef struct st_HC_HCCA {
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165 __O uint32_t HccaIntTable[32];
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166 __I uint16_t HccaFrameNumber;
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167 __I uint16_t HccaPad1;
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168 __I uint32_t HccaDoneHead;
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169 __I uint8_t HccaReserved[116];
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170 } ATTR_ALIGNED (256) HC_HCCA;
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172 typedef struct st_HC_ED { // 16 byte align
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173 /*---------- Word 1 ----------*/
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174 uint32_t FunctionAddr : 7;
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175 uint32_t EndpointNumber : 4;
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176 uint32_t Direction : 2;
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177 uint32_t Speed : 1;
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179 uint32_t Format : 1;
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180 uint32_t MaxPackageSize : 11;
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181 uint32_t : 0;/* Force next member on next storage unit */
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182 /*---------- End Word 1 ----------*/
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184 /*---------- Word 2 ----------*/
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185 uint32_t TailP; // only 28 bits - 16B align
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187 /*---------- Word 3 ----------*/
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191 uint32_t Halted : 1;
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192 uint32_t ToggleCarry : 1;
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196 } HeadP;/* TODO remove this name */
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198 /*---------- Word 4 ----------*/
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199 uint32_t NextED;// only 28 bits - 16B align
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200 } ATTR_ALIGNED (16) HC_ED, *PHC_ED;
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202 typedef struct st_HCD_EndpointDescriptor { // 32 byte align
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205 /*---------- Word 1 ----------*/
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206 uint32_t inUse : 1;
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207 uint32_t ListIndex : 7; // 0: Interrupt/ISO, 1: Control, 2: bulk
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208 uint32_t Interval : 8; /* Used by ISO, High speed Bulk/Control maximum NAK */
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209 uint32_t : 0; /* Force next member on next storage unit */
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210 /*---------- End Word 1 ----------*/
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212 __IO uint32_t status; // TODO status is updated by ISR --> is non-caching
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213 uint16_t *pActualTransferCount; /* total transferred bytes of a usb request */
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216 } HCD_EndpointDescriptor, *PHCD_EndpointDescriptor;
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218 typedef struct st_HC_GTD { // 16 byte align
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219 /*---------- Word 1 ----------*/
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221 uint32_t BufferRounding : 1;
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222 uint32_t DirectionPID : 2;
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223 uint32_t DelayInterrupt : 3;
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224 __IO uint32_t DataToggle : 2;
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225 __IO uint32_t ErrorCount : 2;
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226 __IO uint32_t ConditionCode : 4;
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227 uint32_t : 0; /* Force next member on next storage unit */
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228 /*---------- End Word 1 ----------*/
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230 /*---------- Word 2 ----------*/
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231 __IO uint8_t *CurrentBufferPointer;
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233 /*---------- Word 3 ----------*/
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234 __IO uint32_t NextTD; // only 28 bits - 16B align
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236 /*---------- Word 4 ----------*/
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237 uint8_t *BufferEnd;
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238 } ATTR_ALIGNED (16) HC_GTD, *PHC_GTD; /* TODO merge into HCD_GeneralTransferDescriptor */
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240 typedef struct st_HCD_GeneralTransferDescriptor { // 32 byte align
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243 /*---------- Word 1 ----------*/
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244 uint32_t inUse : 1;
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245 uint32_t : 0; /* Force next member on next storage unit */
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246 /*---------- End Word 1 ----------*/
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249 uint16_t TransferCount;
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251 uint32_t reserved2;
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252 uint32_t reserved3;
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253 } HCD_GeneralTransferDescriptor, *PHCD_GeneralTransferDescriptor;
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255 typedef struct st_HCD_IsoTransferDescriptor { // 64 byte align
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256 /*---------- Word 1 ----------*/
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257 uint32_t StartingFrame : 16;
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259 uint32_t DelayInterrupt : 3;
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260 uint32_t FrameCount : 3;
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262 __IO uint32_t ConditionCode : 4;
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263 uint32_t : 0; /* Force next member on next storage unit */
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264 /*---------- End Word 1 ----------*/
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266 /*---------- Word 2 ----------*/
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267 uint32_t BufferPage0; // only 20 bits - 4KB align
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269 /*---------- Word 3 ----------*/
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270 __IO uint32_t NextTD; // only 27 bits - 32B align
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272 /*---------- Word 4 ----------*/
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273 uint32_t BufferEnd;
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275 /*---------- Word 5-8 ----------*/
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276 __IO uint16_t OffsetPSW[8];
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278 /*---------- HCD AREA ----------*/
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279 /*---------- Word 9 ----------*/
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280 uint32_t inUse : 1;
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281 uint32_t : 0; /* Force next member on next storage unit */
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282 /*---------- End Word 9 ----------*/
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284 /*---------- Word 10 ----------*/
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286 uint16_t reserved3;
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287 /*---------- End Word 10 ----------*/
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289 uint32_t reserved2[6];
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290 } ATTR_ALIGNED (32) HCD_IsoTransferDescriptor, *PHCD_IsoTransferDescriptor;
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292 typedef struct st_OHCI_HOST {
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294 uint32_t host_reserved1;
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295 #if ISO_LIST_ENABLE
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296 HCD_IsoTransferDescriptor iTDs[MAX_ITD];
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298 HCD_GeneralTransferDescriptor gTDs[MAX_GTD];
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299 HCD_EndpointDescriptor EDs[MAX_ED];
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300 HC_ED staticEDs[MAX_STATIC_ED];
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301 } OHCI_HOST_DATA_T;
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303 // #define OHCI_DATA(HostID) ((OHCI_HOST_DATA_T*) HCD_RAM_ADDR_BASE)
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304 extern OHCI_HOST_DATA_T ohci_data[MAX_USB_CORE];
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306 static INLINE HCD_STATUS OHciHostInit(uint8_t HostID);
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308 static INLINE HCD_STATUS OHciHostReset(uint8_t HostID);
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310 static INLINE HCD_STATUS OHciHostOperational(uint8_t HostID);
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312 #if 0 // just to clear warning
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313 static INLINE HCD_STATUS OHciHostSuspend(uint8_t HostID);
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315 static INLINE HCD_STATUS OHciRhPortPowerOn(uint8_t HostID, uint8_t uPortNumber);
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317 static INLINE HCD_STATUS OHciRhPortPowerOff(uint8_t HostID, uint8_t uPortNumber);
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319 static INLINE HCD_STATUS OHciRhPortSuspend(uint8_t HostID, uint8_t uPortNumber);
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321 static INLINE HCD_STATUS OHciRhPortResume(uint8_t HostID, uint8_t uPortNumber);
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323 static INLINE Bool IsInterruptEndpoint (uint8_t EdIdx);
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327 static INLINE uint32_t Align16 (uint32_t Value);
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329 static INLINE PHCD_EndpointDescriptor HcdED(uint8_t idx);
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331 static INLINE PHCD_GeneralTransferDescriptor HcdGTD(uint8_t idx);
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333 static INLINE PHCD_IsoTransferDescriptor HcdITD(uint8_t idx);
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335 static INLINE Bool IsIsoEndpoint(uint8_t EdIdx);
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337 static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, uint8_t idx);
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339 static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *HostID, uint8_t *EdIdx);
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341 static INLINE void BuildPeriodicStaticEdTree(uint8_t HostID);
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343 static INLINE HCD_STATUS AllocEd(uint8_t DeviceAddr,
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344 HCD_USB_SPEED DeviceSpeed,
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345 uint8_t EndpointNumber,
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346 HCD_TRANSFER_TYPE TransferType,
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347 HCD_TRANSFER_DIR TransferDir,
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348 uint16_t MaxPacketSize,
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352 static INLINE HCD_STATUS AllocGtdForEd(uint8_t EdIdx);
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354 static INLINE HCD_STATUS AllocItdForEd(uint8_t EdIdx);
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356 static INLINE HCD_STATUS FreeED(uint8_t EdIdx);
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358 static INLINE HCD_STATUS FreeGtd(PHCD_GeneralTransferDescriptor pGtd);
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360 static INLINE HCD_STATUS FreeItd(PHCD_IsoTransferDescriptor pItd);
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362 static INLINE HCD_STATUS InsertEndpoint(uint8_t HostID, uint32_t EdIdx, uint8_t ListIndex);
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364 static INLINE HCD_STATUS RemoveEndpoint(uint8_t HostID, uint32_t EdIdx);
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366 /*static INLINE uint8_t FindInterruptTransferListIndex(uint8_t HostID, uint8_t Interval);*/
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367 static HCD_STATUS QueueOneGTD (uint32_t EdIdx,
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368 uint8_t *const CurrentBufferPointer,
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370 uint8_t DirectionPID,
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371 uint8_t DataToggle,
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374 static HCD_STATUS QueueGTDs (uint32_t EdIdx, uint8_t *dataBuff, uint32_t xferLen, uint8_t Direction);
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376 static HCD_STATUS WaitForTransferComplete(uint8_t EdIdx);
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378 #endif /*defined(__LPC_OHCI__)*/
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