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40 ******************************************************************************/
41 /****************************************************************************/
44 * @file xdevcfg_intr.c
46 * Contains the implementation of interrupt related functions of the XDcfg
50 * MODIFICATION HISTORY:
52 * Ver Who Date Changes
53 * ----- --- -------- ---------------------------------------------
54 * 1.00a hvm 02/07/11 First release
55 * 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
56 * set the mask instead of oring it with the
57 * value read from the interrupt status register
60 ******************************************************************************/
62 /***************************** Include Files *********************************/
66 /************************** Constant Definitions *****************************/
68 /**************************** Type Definitions *******************************/
70 /***************** Macros (Inline Functions) Definitions *********************/
72 /************************** Function Prototypes ******************************/
74 /************************** Variable Definitions *****************************/
76 /****************************************************************************/
79 * This function enables the specified interrupts in the device.
81 * @param InstancePtr is a pointer to the XDcfg instance.
82 * @param Mask is the bit-mask of the interrupts to be enabled.
83 * Bit positions of 1 will be enabled. Bit positions of 0 will
84 * keep the previous setting. This mask is formed by OR'ing
85 * XDCFG_INT_* bits defined in xdevcfg_hw.h.
91 *****************************************************************************/
92 void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
97 * Assert the arguments.
99 Xil_AssertVoid(InstancePtr != NULL);
100 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
103 * Enable the specified interrupts in the Interrupt Mask Register.
105 RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
106 XDCFG_INT_MASK_OFFSET);
107 RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
108 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
109 XDCFG_INT_MASK_OFFSET,
114 /****************************************************************************/
117 * This function disables the specified interrupts in the device.
119 * @param InstancePtr is a pointer to the XDcfg instance.
120 * @param Mask is the bit-mask of the interrupts to be disabled.
121 * Bit positions of 1 will be disabled. Bit positions of 0 will
122 * keep the previous setting. This mask is formed by OR'ing
123 * XDCFG_INT_* bits defined in xdevcfg_hw.h.
129 *****************************************************************************/
130 void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
135 * Assert the arguments.
137 Xil_AssertVoid(InstancePtr != NULL);
138 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
141 * Disable the specified interrupts in the Interrupt Mask Register.
143 RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
144 XDCFG_INT_MASK_OFFSET);
145 RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
146 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
147 XDCFG_INT_MASK_OFFSET,
150 /****************************************************************************/
153 * This function returns the enabled interrupts read from the Interrupt Mask
154 * Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
155 * to interpret the returned value.
157 * @param InstancePtr is a pointer to the XDcfg instance.
159 * @return A 32-bit value representing the contents of the IMR.
163 *****************************************************************************/
164 u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
167 * Assert the arguments.
169 Xil_AssertNonvoid(InstancePtr != NULL);
170 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
173 * Return the value read from the Interrupt Mask Register.
175 return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
176 XDCFG_INT_MASK_OFFSET));
179 /****************************************************************************/
182 * This function returns the interrupt status read from Interrupt Status
183 * Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
184 * to interpret the returned value.
186 * @param InstancePtr is a pointer to the XDcfg instance.
188 * @return A 32-bit value representing the contents of the Interrupt
193 *****************************************************************************/
194 u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
197 * Assert the arguments.
199 Xil_AssertNonvoid(InstancePtr != NULL);
200 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
203 * Return the value read from the Interrupt Status register.
205 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
206 XDCFG_INT_STS_OFFSET);
209 /****************************************************************************/
212 * This function clears the specified interrupts in the Interrupt Status
215 * @param InstancePtr is a pointer to the XDcfg instance.
216 * @param Mask is the bit-mask of the interrupts to be cleared.
217 * Bit positions of 1 will be cleared. Bit positions of 0 will not
218 * change the previous interrupt status. This mask is formed by
219 * OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
225 *****************************************************************************/
226 void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
229 * Assert the arguments.
231 Xil_AssertVoid(InstancePtr != NULL);
232 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
234 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
235 XDCFG_INT_STS_OFFSET,
240 /*****************************************************************************/
242 * The interrupt handler for the Device Config Interface.
244 * Events are signaled to upper layer for proper handling.
247 * @param InstancePtr is a pointer to the XDcfg instance.
253 ****************************************************************************/
254 void XDcfg_InterruptHandler(XDcfg *InstancePtr)
259 * Assert validates the input arguments.
261 Xil_AssertVoid(InstancePtr != NULL);
262 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
265 * Read the Interrupt status register.
267 IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
268 XDCFG_INT_STS_OFFSET);
271 * Write the status back to clear the interrupts so that no
272 * subsequent interrupts are missed while processing this interrupt.
273 * This also does the DMA acknowledgment automatically.
275 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
276 XDCFG_INT_STS_OFFSET, IntrStatusReg);
279 * Signal application that there are events to handle.
281 InstancePtr->StatusHandler(InstancePtr->CallBackRef,
286 /****************************************************************************/
289 * This function sets the handler that will be called when an event (interrupt)
290 * occurs that needs application's attention.
292 * @param InstancePtr is a pointer to the XDcfg instance
293 * @param CallBackFunc is the address of the callback function.
294 * @param CallBackRef is a user data item that will be passed to the
295 * callback function when it is invoked.
302 *****************************************************************************/
303 void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
307 * Asserts validate the input arguments
308 * CallBackRef not checked, no way to know what is valid
310 Xil_AssertVoid(InstancePtr != NULL);
311 Xil_AssertVoid(CallBackFunc != NULL);
312 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
314 InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
315 InstancePtr->CallBackRef = CallBackRef;