1 /**************************************************************************//**
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2 * @file efm32pg1b100f256gm32.h
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3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
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4 * for EFM32PG1B100F256GM32
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6 ******************************************************************************
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8 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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9 ******************************************************************************
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11 * Permission is granted to anyone to use this software for any purpose,
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12 * including commercial applications, and to alter it and redistribute it
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13 * freely, subject to the following restrictions:
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15 * 1. The origin of this software must not be misrepresented; you must not
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16 * claim that you wrote the original software.@n
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17 * 2. Altered source versions must be plainly marked as such, and must not be
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18 * misrepresented as being the original software.@n
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19 * 3. This notice may not be removed or altered from any source distribution.
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21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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23 * providing the Software "AS IS", with no express or implied warranties of any
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24 * kind, including, but not limited to, any implied warranties of
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25 * merchantability or fitness for any particular purpose or warranties against
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26 * infringement of any proprietary rights of a third party.
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28 * Silicon Laboratories, Inc. will not be liable for any consequential,
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29 * incidental, or special damages, or any other relief, or for any claim by
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30 * any third party, arising from your use of this Software.
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32 *****************************************************************************/
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34 #ifndef SILICON_LABS_EFM32PG1B100F256GM32_H
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35 #define SILICON_LABS_EFM32PG1B100F256GM32_H
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41 /**************************************************************************//**
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44 *****************************************************************************/
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46 /**************************************************************************//**
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47 * @defgroup EFM32PG1B100F256GM32 EFM32PG1B100F256GM32
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49 *****************************************************************************/
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51 /** Interrupt Number Definition */
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54 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/
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55 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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56 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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58 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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59 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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60 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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62 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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63 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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65 /****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/
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67 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
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68 WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
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69 LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
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70 GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
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71 TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
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72 USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
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73 USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
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74 ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
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75 ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
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76 IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
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77 I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
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78 GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
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79 TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
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80 USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
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81 USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
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82 LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
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83 PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
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84 CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
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85 MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
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86 CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
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87 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
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88 RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
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89 CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
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90 FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
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93 /**************************************************************************//**
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94 * @defgroup EFM32PG1B100F256GM32_Core EFM32PG1B100F256GM32 Core
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96 * @brief Processor and Core Peripheral Section
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97 *****************************************************************************/
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98 #define __MPU_PRESENT 1 /**< Presence of MPU */
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99 #define __FPU_PRESENT 1 /**< Presence of FPU */
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100 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
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101 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
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103 /** @} End of group EFM32PG1B100F256GM32_Core */
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105 /**************************************************************************//**
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106 * @defgroup EFM32PG1B100F256GM32_Part EFM32PG1B100F256GM32 Part
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108 ******************************************************************************/
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111 #define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */
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112 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
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113 #define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */
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114 #define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */
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116 /* If part number is not defined as compiler option, define it */
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117 #if !defined(EFM32PG1B100F256GM32)
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118 #define EFM32PG1B100F256GM32 1 /**< PEARL Gecko Part */
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121 /** Configure part number */
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122 #define PART_NUMBER "EFM32PG1B100F256GM32" /**< Part Number */
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124 /** Memory Base addresses and limits */
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125 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
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126 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
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127 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
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128 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
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129 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
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130 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
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131 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
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132 #define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */
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133 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
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134 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
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135 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
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136 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */
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137 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
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138 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
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139 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
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140 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */
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141 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
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142 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
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143 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
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144 #define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */
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145 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
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146 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
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147 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
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148 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */
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149 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
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150 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
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151 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
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152 #define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */
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153 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
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154 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
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155 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
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156 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
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157 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
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158 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
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159 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
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160 #define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
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162 /** Bit banding area */
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163 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
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164 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
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166 /** Flash and SRAM limits for EFM32PG1B100F256GM32 */
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167 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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168 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
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169 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
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170 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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171 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
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172 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
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173 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
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174 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
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176 /** AF channels connect the different on-chip peripherals with the af-mux */
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177 #define AFCHAN_MAX 72
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178 #define AFCHANLOC_MAX 32
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179 /** Analog AF channels */
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180 #define AFACHAN_MAX 61
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182 /* Part number capabilities */
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184 #define TIMER_PRESENT /**< TIMER is available in this part */
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185 #define TIMER_COUNT 2 /**< 2 TIMERs available */
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186 #define USART_PRESENT /**< USART is available in this part */
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187 #define USART_COUNT 2 /**< 2 USARTs available */
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188 #define LEUART_PRESENT /**< LEUART is available in this part */
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189 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
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190 #define LETIMER_PRESENT /**< LETIMER is available in this part */
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191 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
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192 #define PCNT_PRESENT /**< PCNT is available in this part */
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193 #define PCNT_COUNT 1 /**< 1 PCNTs available */
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194 #define I2C_PRESENT /**< I2C is available in this part */
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195 #define I2C_COUNT 1 /**< 1 I2Cs available */
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196 #define ADC_PRESENT /**< ADC is available in this part */
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197 #define ADC_COUNT 1 /**< 1 ADCs available */
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198 #define ACMP_PRESENT /**< ACMP is available in this part */
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199 #define ACMP_COUNT 2 /**< 2 ACMPs available */
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200 #define IDAC_PRESENT /**< IDAC is available in this part */
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201 #define IDAC_COUNT 1 /**< 1 IDACs available */
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202 #define WDOG_PRESENT /**< WDOG is available in this part */
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203 #define WDOG_COUNT 1 /**< 1 WDOGs available */
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204 #define MSC_PRESENT
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205 #define MSC_COUNT 1
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206 #define EMU_PRESENT
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207 #define EMU_COUNT 1
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208 #define RMU_PRESENT
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209 #define RMU_COUNT 1
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210 #define CMU_PRESENT
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211 #define CMU_COUNT 1
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212 #define CRYPTO_PRESENT
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213 #define CRYPTO_COUNT 1
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214 #define GPIO_PRESENT
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215 #define GPIO_COUNT 1
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216 #define PRS_PRESENT
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217 #define PRS_COUNT 1
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218 #define LDMA_PRESENT
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219 #define LDMA_COUNT 1
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220 #define FPUEH_PRESENT
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221 #define FPUEH_COUNT 1
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222 #define GPCRC_PRESENT
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223 #define GPCRC_COUNT 1
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224 #define CRYOTIMER_PRESENT
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225 #define CRYOTIMER_COUNT 1
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226 #define RTCC_PRESENT
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227 #define RTCC_COUNT 1
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228 #define BOOTLOADER_PRESENT
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229 #define BOOTLOADER_COUNT 1
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231 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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232 #include "system_efm32pg1b.h" /* System Header File */
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234 /** @} End of group EFM32PG1B100F256GM32_Part */
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236 /**************************************************************************//**
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237 * @defgroup EFM32PG1B100F256GM32_Peripheral_TypeDefs EFM32PG1B100F256GM32 Peripheral TypeDefs
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239 * @brief Device Specific Peripheral Register Structures
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240 *****************************************************************************/
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242 #include "efm32pg1b_msc.h"
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243 #include "efm32pg1b_emu.h"
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244 #include "efm32pg1b_rmu.h"
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245 #include "efm32pg1b_cmu.h"
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246 #include "efm32pg1b_crypto.h"
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247 #include "efm32pg1b_gpio_p.h"
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248 #include "efm32pg1b_gpio.h"
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249 #include "efm32pg1b_prs_ch.h"
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250 #include "efm32pg1b_prs.h"
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251 #include "efm32pg1b_ldma_ch.h"
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252 #include "efm32pg1b_ldma.h"
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253 #include "efm32pg1b_fpueh.h"
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254 #include "efm32pg1b_gpcrc.h"
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255 #include "efm32pg1b_timer_cc.h"
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256 #include "efm32pg1b_timer.h"
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257 #include "efm32pg1b_usart.h"
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258 #include "efm32pg1b_leuart.h"
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259 #include "efm32pg1b_letimer.h"
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260 #include "efm32pg1b_cryotimer.h"
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261 #include "efm32pg1b_pcnt.h"
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262 #include "efm32pg1b_i2c.h"
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263 #include "efm32pg1b_adc.h"
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264 #include "efm32pg1b_acmp.h"
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265 #include "efm32pg1b_idac.h"
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266 #include "efm32pg1b_rtcc_cc.h"
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267 #include "efm32pg1b_rtcc_ret.h"
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268 #include "efm32pg1b_rtcc.h"
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269 #include "efm32pg1b_wdog_pch.h"
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270 #include "efm32pg1b_wdog.h"
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271 #include "efm32pg1b_dma_descriptor.h"
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272 #include "efm32pg1b_devinfo.h"
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273 #include "efm32pg1b_romtable.h"
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275 /** @} End of group EFM32PG1B100F256GM32_Peripheral_TypeDefs */
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277 /**************************************************************************//**
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278 * @defgroup EFM32PG1B100F256GM32_Peripheral_Base EFM32PG1B100F256GM32 Peripheral Memory Map
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280 *****************************************************************************/
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282 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
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283 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
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284 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
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285 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
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286 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
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287 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
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288 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
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289 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
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290 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
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291 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
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292 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
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293 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
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294 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
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295 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
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296 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
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297 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
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298 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
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299 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
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300 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
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301 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
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302 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
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303 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
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304 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
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305 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
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306 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
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307 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
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308 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
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309 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
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310 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
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312 /** @} End of group EFM32PG1B100F256GM32_Peripheral_Base */
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314 /**************************************************************************//**
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315 * @defgroup EFM32PG1B100F256GM32_Peripheral_Declaration EFM32PG1B100F256GM32 Peripheral Declarations
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317 *****************************************************************************/
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319 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
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320 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
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321 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
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322 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
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323 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
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324 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
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325 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
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326 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
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327 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
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328 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
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329 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
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330 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
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331 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
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332 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
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333 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
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334 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
\r
335 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
\r
336 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
\r
337 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
\r
338 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
\r
339 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
\r
340 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
\r
341 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
\r
342 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
\r
343 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
\r
344 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
\r
345 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
\r
347 /** @} End of group EFM32PG1B100F256GM32_Peripheral_Declaration */
\r
349 /**************************************************************************//**
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350 * @defgroup EFM32PG1B100F256GM32_Peripheral_Offsets EFM32PG1B100F256GM32 Peripheral Offsets
\r
352 *****************************************************************************/
\r
354 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
\r
355 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
\r
356 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
\r
357 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
\r
358 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
\r
359 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
\r
360 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
\r
361 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
\r
362 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
\r
363 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
\r
365 /** @} End of group EFM32PG1B100F256GM32_Peripheral_Offsets */
\r
368 /**************************************************************************//**
\r
369 * @defgroup EFM32PG1B100F256GM32_BitFields EFM32PG1B100F256GM32 Bit Fields
\r
371 *****************************************************************************/
\r
373 #include "efm32pg1b_prs_signals.h"
\r
374 #include "efm32pg1b_dmareq.h"
\r
376 /**************************************************************************//**
\r
377 * @defgroup EFM32PG1B100F256GM32_UNLOCK EFM32PG1B100F256GM32 Unlock Codes
\r
379 *****************************************************************************/
\r
380 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
\r
381 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
\r
382 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
\r
383 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
\r
384 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
\r
385 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
\r
386 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
\r
388 /** @} End of group EFM32PG1B100F256GM32_UNLOCK */
\r
390 /** @} End of group EFM32PG1B100F256GM32_BitFields */
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392 /**************************************************************************//**
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393 * @defgroup EFM32PG1B100F256GM32_Alternate_Function EFM32PG1B100F256GM32 Alternate Function
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395 *****************************************************************************/
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397 #include "efm32pg1b_af_ports.h"
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398 #include "efm32pg1b_af_pins.h"
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400 /** @} End of group EFM32PG1B100F256GM32_Alternate_Function */
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402 /**************************************************************************//**
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403 * @brief Set the value of a bit field within a register.
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406 * The register to update
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408 * The mask for the bit field to update
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410 * The value to write to the bit field
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412 * The number of bits that the field is offset within the register.
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413 * 0 (zero) means LSB.
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414 *****************************************************************************/
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415 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
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416 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
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418 /** @} End of group EFM32PG1B100F256GM32 */
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420 /** @} End of group Parts */
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425 #endif /* SILICON_LABS_EFM32PG1B100F256GM32_H */
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projects / freertos / blob