1 /**************************************************************************//**
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2 * @file efm32wg_aes.h
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3 * @brief EFM32WG_AES register and bit field definitions
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5 ******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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33 * @defgroup EFM32WG_AES
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35 * @brief EFM32WG_AES Register Declaration
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36 *****************************************************************************/
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39 __IO uint32_t CTRL; /**< Control Register */
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40 __IO uint32_t CMD; /**< Command Register */
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41 __I uint32_t STATUS; /**< Status Register */
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42 __IO uint32_t IEN; /**< Interrupt Enable Register */
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43 __I uint32_t IF; /**< Interrupt Flag Register */
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44 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
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45 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
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46 __IO uint32_t DATA; /**< DATA Register */
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47 __IO uint32_t XORDATA; /**< XORDATA Register */
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48 uint32_t RESERVED0[3]; /**< Reserved for future use **/
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49 __IO uint32_t KEYLA; /**< KEY Low Register */
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50 __IO uint32_t KEYLB; /**< KEY Low Register */
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51 __IO uint32_t KEYLC; /**< KEY Low Register */
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52 __IO uint32_t KEYLD; /**< KEY Low Register */
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53 __IO uint32_t KEYHA; /**< KEY High Register */
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54 __IO uint32_t KEYHB; /**< KEY High Register */
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55 __IO uint32_t KEYHC; /**< KEY High Register */
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56 __IO uint32_t KEYHD; /**< KEY High Register */
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57 } AES_TypeDef; /** @} */
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59 /**************************************************************************//**
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60 * @defgroup EFM32WG_AES_BitFields
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62 *****************************************************************************/
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64 /* Bit fields for AES CTRL */
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65 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
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66 #define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
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67 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
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68 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
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69 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
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70 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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71 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
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72 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
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73 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
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74 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
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75 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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76 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
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77 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
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78 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
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79 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
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80 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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81 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
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82 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
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83 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
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84 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
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85 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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86 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
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87 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
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88 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
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89 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
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90 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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91 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
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92 #define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
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93 #define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
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94 #define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
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95 #define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
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96 #define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
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98 /* Bit fields for AES CMD */
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99 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
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100 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
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101 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
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102 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
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103 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
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104 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
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105 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
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106 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
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107 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
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108 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
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109 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
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110 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
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112 /* Bit fields for AES STATUS */
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113 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
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114 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
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115 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
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116 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
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117 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
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118 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
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119 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
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121 /* Bit fields for AES IEN */
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122 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
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123 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
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124 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
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125 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
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126 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
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127 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
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128 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
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130 /* Bit fields for AES IF */
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131 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
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132 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
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133 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
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134 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
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135 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
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136 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
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137 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
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139 /* Bit fields for AES IFS */
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140 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
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141 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
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142 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
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143 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
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144 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
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145 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
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146 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
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148 /* Bit fields for AES IFC */
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149 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
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150 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
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151 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
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152 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
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153 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
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154 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
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155 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
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157 /* Bit fields for AES DATA */
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158 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
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159 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
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160 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
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161 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
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162 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
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163 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
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165 /* Bit fields for AES XORDATA */
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166 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
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167 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
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168 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
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169 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
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170 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
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171 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
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173 /* Bit fields for AES KEYLA */
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174 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
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175 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
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176 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
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177 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
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178 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
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179 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
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181 /* Bit fields for AES KEYLB */
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182 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
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183 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
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184 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
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185 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
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186 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
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187 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
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189 /* Bit fields for AES KEYLC */
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190 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
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191 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
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192 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
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193 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
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194 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
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195 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
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197 /* Bit fields for AES KEYLD */
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198 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
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199 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
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200 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
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201 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
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202 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
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203 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
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205 /* Bit fields for AES KEYHA */
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206 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
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207 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
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208 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
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209 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
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210 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
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211 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
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213 /* Bit fields for AES KEYHB */
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214 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
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215 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
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216 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
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217 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
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218 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
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219 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
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221 /* Bit fields for AES KEYHC */
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222 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
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223 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
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224 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
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225 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
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226 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
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227 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
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229 /* Bit fields for AES KEYHD */
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230 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
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231 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
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232 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
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233 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
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234 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
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235 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
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237 /** @} End of group EFM32WG_AES */
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