1 /**************************************************************************//**
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2 * @file efm32wg_i2c.h
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3 * @brief EFM32WG_I2C register and bit field definitions
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5 ******************************************************************************
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7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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35 ******************************************************************************/
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36 /**************************************************************************//**
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37 * @defgroup EFM32WG_I2C
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39 * @brief EFM32WG_I2C Register Declaration
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40 *****************************************************************************/
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43 __IO uint32_t CTRL; /**< Control Register */
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44 __IO uint32_t CMD; /**< Command Register */
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45 __I uint32_t STATE; /**< State Register */
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46 __I uint32_t STATUS; /**< Status Register */
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47 __IO uint32_t CLKDIV; /**< Clock Division Register */
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48 __IO uint32_t SADDR; /**< Slave Address Register */
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49 __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
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50 __I uint32_t RXDATA; /**< Receive Buffer Data Register */
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51 __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
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52 __IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
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53 __I uint32_t IF; /**< Interrupt Flag Register */
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54 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
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55 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
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56 __IO uint32_t IEN; /**< Interrupt Enable Register */
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57 __IO uint32_t ROUTE; /**< I/O Routing Register */
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58 } I2C_TypeDef; /** @} */
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60 /**************************************************************************//**
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61 * @defgroup EFM32WG_I2C_BitFields
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63 *****************************************************************************/
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65 /* Bit fields for I2C CTRL */
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66 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
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67 #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
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68 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
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69 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
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70 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
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71 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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72 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
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73 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
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74 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
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75 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
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76 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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77 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
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78 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
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79 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
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80 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
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81 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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82 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
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83 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
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84 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
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85 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
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86 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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87 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
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88 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
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89 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
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90 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
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91 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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92 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
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93 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
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94 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
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95 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
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96 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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97 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
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98 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
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99 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
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100 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
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101 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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102 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
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103 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
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104 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
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105 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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106 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
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107 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
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108 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
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109 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
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110 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
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111 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
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112 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
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113 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
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114 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
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115 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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116 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
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117 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
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118 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
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119 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
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120 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
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121 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
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122 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
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123 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
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124 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
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125 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
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126 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
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127 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
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128 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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129 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
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130 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
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131 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
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132 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
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133 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
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134 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
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135 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
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136 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
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137 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
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138 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
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139 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
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140 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
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141 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
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142 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
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143 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
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144 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
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145 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
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147 /* Bit fields for I2C CMD */
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148 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
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149 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
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150 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
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151 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
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152 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
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153 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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154 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
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155 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
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156 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
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157 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
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158 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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159 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
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160 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
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161 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
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162 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
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163 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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164 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
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165 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
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166 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
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167 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
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168 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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169 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
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170 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
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171 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
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172 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
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173 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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174 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
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175 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
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176 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
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177 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
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178 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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179 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
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180 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
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181 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
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182 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
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183 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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184 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
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185 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
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186 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
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187 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
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188 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
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189 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
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191 /* Bit fields for I2C STATE */
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192 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
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193 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
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194 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
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195 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
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196 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
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197 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
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198 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
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199 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
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200 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
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201 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
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202 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
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203 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
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204 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
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205 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
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206 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
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207 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
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208 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
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209 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
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210 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
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211 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
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212 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
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213 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
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214 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
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215 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
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216 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
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217 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
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218 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
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219 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
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220 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
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221 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
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222 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
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223 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
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224 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
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225 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
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226 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
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227 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
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228 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
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229 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
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230 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
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231 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
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232 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
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233 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
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234 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
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235 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
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236 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
\r
238 /* Bit fields for I2C STATUS */
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239 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
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240 #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
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241 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
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242 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
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243 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
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244 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
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245 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
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246 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
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247 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
\r
248 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
\r
249 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
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250 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
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251 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
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252 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
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253 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
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254 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
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255 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
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256 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
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257 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
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258 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
\r
259 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
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260 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
261 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
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262 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
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263 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
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264 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
\r
265 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
266 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
\r
267 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
\r
268 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
\r
269 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
\r
270 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
271 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
\r
272 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
\r
273 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
\r
274 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
\r
275 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
276 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
\r
277 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
\r
278 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
\r
279 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
\r
280 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
281 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
\r
282 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
\r
283 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
\r
284 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
\r
285 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
\r
287 /* Bit fields for I2C CLKDIV */
\r
288 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
\r
289 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
\r
290 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
\r
291 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
\r
292 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
\r
293 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
\r
295 /* Bit fields for I2C SADDR */
\r
296 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
\r
297 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
\r
298 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
\r
299 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
\r
300 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
\r
301 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
\r
303 /* Bit fields for I2C SADDRMASK */
\r
304 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
\r
305 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
\r
306 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
\r
307 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
\r
308 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
\r
309 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
\r
311 /* Bit fields for I2C RXDATA */
\r
312 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
\r
313 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
\r
314 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
\r
315 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
\r
316 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
\r
317 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
\r
319 /* Bit fields for I2C RXDATAP */
\r
320 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
\r
321 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
\r
322 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
\r
323 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
\r
324 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
\r
325 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
\r
327 /* Bit fields for I2C TXDATA */
\r
328 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
\r
329 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
\r
330 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
\r
331 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
\r
332 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
\r
333 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
\r
335 /* Bit fields for I2C IF */
\r
336 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
\r
337 #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
\r
338 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
\r
339 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
\r
340 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
\r
341 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
342 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
\r
343 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
\r
344 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
\r
345 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
\r
346 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
347 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
\r
348 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
\r
349 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
\r
350 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
\r
351 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
352 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
\r
353 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
\r
354 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
\r
355 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
\r
356 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
357 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
\r
358 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
\r
359 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
\r
360 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
\r
361 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
362 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
\r
363 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
\r
364 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
\r
365 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
\r
366 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
367 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
\r
368 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
\r
369 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
\r
370 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
\r
371 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
372 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
\r
373 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
\r
374 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
\r
375 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
\r
376 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
377 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
\r
378 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
\r
379 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
\r
380 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
\r
381 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
382 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
\r
383 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
\r
384 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
\r
385 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
\r
386 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
387 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
\r
388 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
\r
389 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
\r
390 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
\r
391 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
392 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
\r
393 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
\r
394 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
\r
395 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
\r
396 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
397 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
\r
398 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
\r
399 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
\r
400 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
\r
401 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
402 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
\r
403 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
\r
404 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
\r
405 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
\r
406 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
407 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
\r
408 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
\r
409 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
\r
410 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
\r
411 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
412 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
\r
413 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
\r
414 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
\r
415 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
\r
416 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
417 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
\r
418 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
\r
419 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
\r
420 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
\r
421 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
\r
422 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
\r
424 /* Bit fields for I2C IFS */
\r
425 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
\r
426 #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
\r
427 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
\r
428 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
\r
429 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
\r
430 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
431 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
\r
432 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
\r
433 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
\r
434 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
\r
435 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
436 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
\r
437 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
\r
438 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
\r
439 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
\r
440 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
441 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
\r
442 #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
\r
443 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
\r
444 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
\r
445 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
446 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
\r
447 #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
\r
448 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
\r
449 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
\r
450 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
451 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
\r
452 #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
\r
453 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
\r
454 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
\r
455 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
456 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
\r
457 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
\r
458 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
\r
459 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
\r
460 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
461 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
\r
462 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
\r
463 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
\r
464 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
\r
465 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
466 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
\r
467 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
\r
468 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
\r
469 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
\r
470 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
471 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
\r
472 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
\r
473 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
\r
474 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
\r
475 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
476 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
\r
477 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
\r
478 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
\r
479 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
\r
480 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
481 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
\r
482 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
\r
483 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
\r
484 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
\r
485 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
486 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
\r
487 #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
\r
488 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
\r
489 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
\r
490 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
491 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
\r
492 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
\r
493 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
\r
494 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
\r
495 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
496 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
\r
497 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
\r
498 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
\r
499 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
\r
500 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
\r
501 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
\r
503 /* Bit fields for I2C IFC */
\r
504 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
\r
505 #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
\r
506 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
\r
507 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
\r
508 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
\r
509 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
510 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
\r
511 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
\r
512 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
\r
513 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
\r
514 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
515 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
\r
516 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
\r
517 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
\r
518 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
\r
519 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
520 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
\r
521 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
\r
522 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
\r
523 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
\r
524 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
525 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
\r
526 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
\r
527 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
\r
528 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
\r
529 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
530 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
\r
531 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
\r
532 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
\r
533 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
\r
534 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
535 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
\r
536 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
\r
537 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
\r
538 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
\r
539 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
540 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
\r
541 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
\r
542 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
\r
543 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
\r
544 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
545 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
\r
546 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
\r
547 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
\r
548 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
\r
549 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
550 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
\r
551 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
\r
552 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
\r
553 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
\r
554 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
555 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
\r
556 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
\r
557 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
\r
558 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
\r
559 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
560 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
\r
561 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
\r
562 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
\r
563 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
\r
564 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
565 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
\r
566 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
\r
567 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
\r
568 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
\r
569 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
570 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
\r
571 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
\r
572 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
\r
573 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
\r
574 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
575 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
\r
576 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
\r
577 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
\r
578 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
\r
579 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
\r
580 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
\r
582 /* Bit fields for I2C IEN */
\r
583 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
\r
584 #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
\r
585 #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
\r
586 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
\r
587 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
\r
588 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
589 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
\r
590 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
\r
591 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
\r
592 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
\r
593 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
594 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
\r
595 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
\r
596 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
\r
597 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
\r
598 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
599 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
\r
600 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
\r
601 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
\r
602 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
\r
603 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
604 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
\r
605 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
\r
606 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
\r
607 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
\r
608 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
609 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
\r
610 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
\r
611 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
\r
612 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
\r
613 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
614 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
\r
615 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
\r
616 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
\r
617 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
\r
618 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
619 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
\r
620 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
\r
621 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
\r
622 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
\r
623 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
624 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
\r
625 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
\r
626 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
\r
627 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
\r
628 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
629 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
\r
630 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
\r
631 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
\r
632 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
\r
633 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
634 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
\r
635 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
\r
636 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
\r
637 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
\r
638 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
639 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
\r
640 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
\r
641 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
\r
642 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
\r
643 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
644 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
\r
645 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
\r
646 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
\r
647 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
\r
648 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
649 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
\r
650 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
\r
651 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
\r
652 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
\r
653 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
654 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
\r
655 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
\r
656 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
\r
657 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
\r
658 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
659 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
\r
660 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
\r
661 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
\r
662 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
\r
663 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
664 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
\r
665 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
\r
666 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
\r
667 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
\r
668 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
\r
669 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
\r
671 /* Bit fields for I2C ROUTE */
\r
672 #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
\r
673 #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */
\r
674 #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
\r
675 #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
\r
676 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
\r
677 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
\r
678 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
\r
679 #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
\r
680 #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
\r
681 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
\r
682 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
\r
683 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
\r
684 #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
\r
685 #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */
\r
686 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
\r
687 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
\r
688 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
\r
689 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
\r
690 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
\r
691 #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */
\r
692 #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */
\r
693 #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */
\r
694 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
\r
695 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
\r
696 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
\r
697 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
\r
698 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
\r
699 #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */
\r
700 #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */
\r
701 #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
\r
703 /** @} End of group EFM32WG_I2C */
\r
704 /** @} End of group Parts */
\r
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