1 /**************************************************************************//**
\r
2 * @file efm32gg_dmactrl.h
\r
3 * @brief EFM32GG_DMACTRL register and bit field definitions
\r
5 ******************************************************************************
\r
7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
\r
8 ******************************************************************************
\r
10 * Permission is granted to anyone to use this software for any purpose,
\r
11 * including commercial applications, and to alter it and redistribute it
\r
12 * freely, subject to the following restrictions:
\r
14 * 1. The origin of this software must not be misrepresented; you must not
\r
15 * claim that you wrote the original software.@n
\r
16 * 2. Altered source versions must be plainly marked as such, and must not be
\r
17 * misrepresented as being the original software.@n
\r
18 * 3. This notice may not be removed or altered from any source distribution.
\r
20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
\r
21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
\r
22 * providing the Software "AS IS", with no express or implied warranties of any
\r
23 * kind, including, but not limited to, any implied warranties of
\r
24 * merchantability or fitness for any particular purpose or warranties against
\r
25 * infringement of any proprietary rights of a third party.
\r
27 * Silicon Laboratories, Inc. will not be liable for any consequential,
\r
28 * incidental, or special damages, or any other relief, or for any claim by
\r
29 * any third party, arising from your use of this Software.
\r
31 *****************************************************************************/
\r
32 /**************************************************************************//**
\r
35 ******************************************************************************/
\r
37 /**************************************************************************//**
\r
38 * @defgroup EFM32GG_DMACTRL_BitFields
\r
40 *****************************************************************************/
\r
41 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
\r
42 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
\r
43 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
\r
44 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
\r
45 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
\r
46 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
\r
47 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
\r
48 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
\r
49 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
\r
50 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
\r
51 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
\r
52 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
\r
53 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
\r
54 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
\r
55 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
\r
56 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
\r
57 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
\r
58 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
\r
59 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
\r
60 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
\r
61 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
\r
62 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
\r
63 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
\r
64 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
\r
65 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
\r
66 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
\r
67 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
\r
68 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
\r
69 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
\r
70 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
\r
71 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
\r
72 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
\r
73 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
\r
74 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
\r
75 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
\r
76 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
\r
77 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
\r
78 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
\r
79 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
\r
80 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
\r
81 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
\r
82 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
\r
83 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
\r
84 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
\r
85 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
\r
86 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
\r
87 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
\r
88 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
\r
89 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
\r
90 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
\r
91 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
\r
92 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
\r
93 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
\r
94 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
\r
95 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
\r
96 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
\r
97 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
\r
98 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
\r
99 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
\r
100 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
\r
101 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
\r
102 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
\r
103 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
\r
104 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
\r
105 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
\r
106 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
\r
107 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
\r
108 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
\r
109 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
\r
110 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
\r
111 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
\r
112 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
\r
113 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
\r
114 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
\r
115 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
\r
116 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
\r
117 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
\r
118 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
\r
119 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
\r
120 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
\r
121 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
\r
122 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
\r
123 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
\r
124 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
\r
125 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
\r
126 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
\r
127 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
\r
128 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
\r
129 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
\r
130 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
\r
131 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
\r
132 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
\r
133 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
\r
134 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
\r
135 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
\r
136 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
\r
138 /** @} End of group EFM32GG_DMA */
\r
139 /** @} End of group Parts */
\r
projects / freertos / blob