1 /**********************************************************************
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2 * $Id$ lpc18xx_i2s.h 2011-06-02
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4 * @file lpc18xx_i2s.h
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5 * @brief Contains all macro definitions and function prototypes
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6 * support for I2S firmware library on LPC18xx
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @defgroup I2S I2S (Inter-IC Sound)
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29 * @ingroup LPC1800CMSIS_FwLib_Drivers
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33 #ifndef LPC18XX_I2S_H_
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34 #define LPC18XX_I2S_H_
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36 /* Includes ------------------------------------------------------------------- */
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37 #include "LPC18xx.h"
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38 #include "lpc_types.h"
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46 /* Private Macros ------------------------------------------------------------- */
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47 /** @defgroup I2S_Private_Macros I2S Private Macros
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51 /*********************************************************************//**
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52 * I2S configuration parameter defines
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53 **********************************************************************/
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54 /** I2S Wordwidth bit */
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55 #define I2S_WORDWIDTH_8 ((uint32_t)(0))
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56 #define I2S_WORDWIDTH_16 ((uint32_t)(1))
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57 #define I2S_WORDWIDTH_32 ((uint32_t)(3))
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58 /** I2S Channel bit */
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59 #define I2S_STEREO ((uint32_t)(0))
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60 #define I2S_MONO ((uint32_t)(1))
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61 /** I2S Master/Slave mode bit */
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62 #define I2S_MASTER_MODE ((uint8_t)(0))
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63 #define I2S_SLAVE_MODE ((uint8_t)(1))
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65 #define I2S_STOP_ENABLE ((uint8_t)(1))
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66 #define I2S_STOP_DISABLE ((uint8_t)(0))
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67 /** I2S Reset bit */
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68 #define I2S_RESET_ENABLE ((uint8_t)(1))
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69 #define I2S_RESET_DISABLE ((uint8_t)(0))
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71 #define I2S_MUTE_ENABLE ((uint8_t)(1))
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72 #define I2S_MUTE_DISABLE ((uint8_t)(0))
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73 /** I2S Transmit/Receive bit */
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74 #define I2S_TX_MODE ((uint8_t)(0))
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75 #define I2S_RX_MODE ((uint8_t)(1))
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76 /** I2S Clock Select bit */
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77 #define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
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78 #define I2S_CLKSEL_MCLK ((uint8_t)(2))
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79 /** I2S 4-pin Mode bit */
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80 #define I2S_4PIN_ENABLE ((uint8_t)(1))
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81 #define I2S_4PIN_DISABLE ((uint8_t)(0))
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82 /** I2S MCLK Enable bit */
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83 #define I2S_MCLK_ENABLE ((uint8_t)(1))
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84 #define I2S_MCLK_DISABLE ((uint8_t)(0))
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85 /** I2S select DMA bit */
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86 #define I2S_DMA_1 ((uint8_t)(0))
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87 #define I2S_DMA_2 ((uint8_t)(1))
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89 /*********************************************************************//**
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90 * Macro defines for DAO-Digital Audio Output register
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91 **********************************************************************/
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92 /** I2S wordwide - the number of bytes in data*/
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93 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
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94 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
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95 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
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96 /** I2S control mono or stereo format */
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97 #define I2S_DAO_MONO ((uint32_t)(1<<2))
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98 /** I2S control stop mode */
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99 #define I2S_DAO_STOP ((uint32_t)(1<<3))
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100 /** I2S control reset mode */
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101 #define I2S_DAO_RESET ((uint32_t)(1<<4))
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102 /** I2S control master/slave mode */
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103 #define I2S_DAO_SLAVE ((uint32_t)(1<<5))
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104 /** I2S word select half period minus one */
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105 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
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106 /** I2S control mute mode */
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107 #define I2S_DAO_MUTE ((uint32_t)(1<<15))
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109 /*********************************************************************//**
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110 * Macro defines for DAI-Digital Audio Input register
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111 **********************************************************************/
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112 /** I2S wordwide - the number of bytes in data*/
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113 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
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114 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
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115 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
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116 /** I2S control mono or stereo format */
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117 #define I2S_DAI_MONO ((uint32_t)(1<<2))
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118 /** I2S control stop mode */
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119 #define I2S_DAI_STOP ((uint32_t)(1<<3))
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120 /** I2S control reset mode */
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121 #define I2S_DAI_RESET ((uint32_t)(1<<4))
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122 /** I2S control master/slave mode */
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123 #define I2S_DAI_SLAVE ((uint32_t)(1<<5))
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124 /** I2S word select half period minus one (9 bits)*/
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125 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
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126 /** I2S control mute mode */
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127 #define I2S_DAI_MUTE ((uint32_t)(1<<15))
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129 /*********************************************************************//**
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130 * Macro defines for STAT register (Status Feedback register)
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131 **********************************************************************/
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132 /** I2S Status Receive or Transmit Interrupt */
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133 #define I2S_STATE_IRQ ((uint32_t)(1))
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134 /** I2S Status Receive or Transmit DMA1 */
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135 #define I2S_STATE_DMA1 ((uint32_t)(1<<1))
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136 /** I2S Status Receive or Transmit DMA2 */
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137 #define I2S_STATE_DMA2 ((uint32_t)(1<<2))
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138 /** I2S Status Current level of the Receive FIFO (5 bits)*/
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139 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
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140 /** I2S Status Current level of the Transmit FIFO (5 bits)*/
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141 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
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143 /*********************************************************************//**
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144 * Macro defines for DMA1 register (DMA1 Configuration register)
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145 **********************************************************************/
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146 /** I2S control DMA1 for I2S receive */
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147 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
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148 /** I2S control DMA1 for I2S transmit */
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149 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
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150 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
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151 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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152 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
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153 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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155 /*********************************************************************//**
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156 * Macro defines for DMA2 register (DMA2 Configuration register)
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157 **********************************************************************/
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158 /** I2S control DMA2 for I2S receive */
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159 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
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160 /** I2S control DMA1 for I2S transmit */
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161 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
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162 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
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163 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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164 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
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165 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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167 /*********************************************************************//**
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168 * Macro defines for IRQ register (Interrupt Request Control register)
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169 **********************************************************************/
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170 /** I2S control I2S receive interrupt */
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171 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
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172 /** I2S control I2S transmit interrupt */
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173 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
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174 /** I2S set the FIFO level on which to create an irq request */
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175 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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176 /** I2S set the FIFO level on which to create an irq request */
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177 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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179 /********************************************************************************//**
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180 * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
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181 *********************************************************************************/
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182 /** I2S Transmit MCLK rate denominator */
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183 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
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184 /** I2S Transmit MCLK rate denominator */
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185 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
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186 /** I2S Receive MCLK rate denominator */
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187 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
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188 /** I2S Receive MCLK rate denominator */
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189 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
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191 /*************************************************************************************//**
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192 * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
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193 **************************************************************************************/
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194 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
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195 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
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197 /**********************************************************************************//**
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198 * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
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199 ************************************************************************************/
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200 /** I2S Transmit select clock source (2 bits)*/
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201 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
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202 /** I2S Transmit control 4-pin mode */
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203 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
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204 /** I2S Transmit control the TX_MCLK output */
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205 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
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206 /** I2S Receive select clock source */
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207 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
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208 /** I2S Receive control 4-pin mode */
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209 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
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210 /** I2S Receive control the TX_MCLK output */
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211 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
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214 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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215 /** Macro to determine if it is valid I2S peripheral */
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216 #define PARAM_I2Sx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2S0)) || (((uint32_t *)n)==((uint32_t *)LPC_I2S1)))
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217 /** Macro to check Data to send valid */
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218 #define PRAM_I2S_FREQ(freq) ((freq>=8000)&&(freq <= 96000))
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219 /* Macro check I2S word width type */
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220 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
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221 ||(n==I2S_WORDWIDTH_32))
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222 /* Macro check I2S channel type */
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223 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
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224 /* Macro check I2S master/slave mode */
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225 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
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226 /* Macro check I2S stop mode */
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227 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
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228 /* Macro check I2S reset mode */
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229 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
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230 /* Macro check I2S reset mode */
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231 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
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232 /* Macro check I2S transmit/receive mode */
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233 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
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234 /* Macro check I2S clock select mode */
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235 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
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236 /* Macro check I2S 4-pin mode */
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237 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
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238 /* Macro check I2S MCLK mode */
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239 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
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240 /* Macro check I2S DMA mode */
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241 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
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242 /* Macro check I2S DMA depth value */
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243 #define PARAM_I2S_DMA_DEPTH(n) ((n<=31))
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244 /* Macro check I2S irq level value */
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245 #define PARAM_I2S_IRQ_LEVEL(n) ((n<=31))
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246 /* Macro check I2S half-period value */
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247 #define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
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248 /* Macro check I2S bit-rate value */
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249 #define PARAM_I2S_BITRATE(n) ((n<=63))
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256 /* Public Types --------------------------------------------------------------- */
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257 /** @defgroup I2S_Public_Types I2S Public Types
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262 * @brief I2S configuration structure definition
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265 uint8_t wordwidth; /** the number of bytes in data as follow:
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266 -I2S_WORDWIDTH_8: 8 bit data
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267 -I2S_WORDWIDTH_16: 16 bit data
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268 -I2S_WORDWIDTH_32: 32 bit data */
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269 uint8_t mono; /** Set mono/stereo mode, should be:
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270 - I2S_STEREO: stereo mode
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271 - I2S_MONO: mono mode */
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272 uint8_t stop; /** Disables accesses on FIFOs, should be:
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273 - I2S_STOP_ENABLE: enable stop mode
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274 - I2S_STOP_DISABLE: disable stop mode */
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275 uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
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276 - I2S_RESET_ENABLE: enable reset mode
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277 - I2S_RESET_DISABLE: disable reset mode */
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278 uint8_t ws_sel; /** Set Master/Slave mode, should be:
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279 - I2S_MASTER_MODE: I2S master mode
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280 - I2S_SLAVE_MODE: I2S slave mode */
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281 uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
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282 - I2S_MUTE_ENABLE: enable mute mode
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283 - I2S_MUTE_DISABLE: disable mute mode */
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284 uint8_t Reserved0[2];
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288 * @brief I2S DMA configuration structure definition
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291 uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
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293 - I2S_DMA_2: DMA2 */
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294 uint8_t depth; /** FIFO level that triggers a DMA request */
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295 uint8_t Reserved0[2];
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299 * @brief I2S mode configuration structure definition
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302 uint8_t clksel; /** Clock source selection, should be:
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303 - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
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304 - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
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305 uint8_t fpin; /** Select four pin mode, should be:
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306 - I2S_4PIN_ENABLE: 4-pin enable
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307 - I2S_4PIN_DISABLE: 4-pin disable */
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308 uint8_t mcena; /** Select MCLK mode, should be:
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309 - I2S_MCLK_ENABLE: MCLK enable for output
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310 - I2S_MCLK_DISABLE: MCLK disable for output */
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312 }I2S_MODEConf_Type;
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320 /* Public Functions ----------------------------------------------------------- */
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321 /** @defgroup I2S_Public_Functions I2S Public Functions
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324 /* I2S Init/DeInit functions ---------*/
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325 void I2S_Init(LPC_I2Sn_Type *I2Sx);
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326 void I2S_DeInit(LPC_I2Sn_Type *I2Sx);
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328 /* I2S configuration functions --------*/
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329 void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
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330 Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode);
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331 void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode);
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332 void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
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333 uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
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335 /* I2S operate functions -------------*/
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336 void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData);
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337 uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx);
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338 void I2S_Start(LPC_I2Sn_Type *I2Sx);
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339 void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
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340 void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
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341 void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
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343 /* I2S DMA functions ----------------*/
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344 void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
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345 void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
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347 /* I2S IRQ functions ----------------*/
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348 void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState);
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349 void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level);
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350 FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
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351 uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
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363 #endif /* LPC18XX_I2S_H_ */
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369 /* --------------------------------- End Of File ------------------------------ */
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