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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xsdps_options.c
  36 *
  37 * Contains API's for changing the various options in host and card.
  38 * See xsdps.h for a detailed description of the device and driver.
  39 *
  40 * <pre>
  41 * MODIFICATION HISTORY:
  42 *
  43 * Ver   Who    Date     Changes
  44 * ----- ---    -------- -----------------------------------------------
  45 * 1.00a hk/sg  10/17/13 Initial release
  46 * 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
  47 *                       Add sleep for microblaze designs. CR# 781117.
  48 * 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
  49 *                                               clock.CR# 816586.
  50 *
  51 * </pre>
  52 *
  53 ******************************************************************************/
  54
  55 /***************************** Include Files *********************************/
  56 #include "xsdps.h"
  57 /*
  58  * The header sleep.h and API usleep() can only be used with an arm design.
  59  * MB_Sleep() is used for microblaze design.
  60  */
  61 #ifdef __arm__
  62
  63 #include "sleep.h"
  64
  65 #endif
  66
  67 #ifdef __MICROBLAZE__
  68
  69 #include "microblaze_sleep.h"
  70
  71 #endif
  72
  73 /************************** Constant Definitions *****************************/
  74 #define XSDPS_SCR_BLKCNT        1
  75 #define XSDPS_SCR_BLKSIZE       8
  76 #define XSDPS_4_BIT_WIDTH       0x2
  77 #define XSDPS_SWITCH_CMD_BLKCNT         1
  78 #define XSDPS_SWITCH_CMD_BLKSIZE        64
  79 #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0
  80 #define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1
  81 #define XSDPS_EXT_CSD_CMD_BLKCNT        1
  82 #define XSDPS_EXT_CSD_CMD_BLKSIZE       512
  83 #define XSDPS_CLK_52_MHZ                52000000
  84 #define XSDPS_MMC_HIGH_SPEED_ARG        0x03B90100
  85 #define XSDPS_MMC_4_BIT_BUS_ARG         0x03B70100
  86 #define XSDPS_MMC_DELAY_FOR_SWITCH      2000
  87
  88 /**************************** Type Definitions *******************************/
  89
  90 /***************** Macros (Inline Functions) Definitions *********************/
  91
  92 /************************** Function Prototypes ******************************/
  93 int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
  94 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
  95
  96 /*****************************************************************************/
  97 /**
  98 * Update Block size for read/write operations.
  99 *
 100 * @param        InstancePtr is a pointer to the instance to be worked on.
 101 * @param        BlkSize - Block size passed by the user.
 102 *
 103 * @return       None
 104 *
 105 ******************************************************************************/
 106 int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
 107 {
 108         u32 Status = 0;
 109         u32 PresentStateReg = 0;
 110
 111         Xil_AssertNonvoid(InstancePtr != NULL);
 112         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 113
 114         PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 115                         XSDPS_PRES_STATE_OFFSET);
 116
 117         if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK |
 118                         XSDPS_PSR_INHIBIT_DAT_MASK |
 119                         XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) {
 120                 Status = XST_FAILURE;
 121                 goto RETURN_PATH;
 122         }
 123
 124
 125         /*
 126          * Send block write command
 127          */
 128         Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0);
 129         if (Status != XST_SUCCESS) {
 130                 Status = XST_FAILURE;
 131                 goto RETURN_PATH;
 132         }
 133
 134         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 135                         XSDPS_RESP0_OFFSET);
 136
 137         /*
 138          * Set block size to the value passed
 139          */
 140         BlkSize &= XSDPS_BLK_SIZE_MASK;
 141         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
 142                          BlkSize);
 143
 144         Status = XST_SUCCESS;
 145
 146         RETURN_PATH:
 147                 return Status;
 148
 149 }
 150
 151 /*****************************************************************************/
 152 /**
 153 *
 154 * API to get bus width support by card.
 155 *
 156 *
 157 * @param        InstancePtr is a pointer to the XSdPs instance.
 158 * @param        SCR - buffer to store SCR register returned by card.
 159 *
 160 * @return
 161 *               - XST_SUCCESS if successful.
 162 *               - XST_FAILURE if fail.
 163 *
 164 * @note         None.
 165 *
 166 ******************************************************************************/
 167 int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
 168 {
 169         u32 Status = 0;
 170         u32 StatusReg = 0x0;
 171         u16 BlkCnt;
 172         u16 BlkSize;
 173         int LoopCnt;
 174
 175         Xil_AssertNonvoid(InstancePtr != NULL);
 176         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 177
 178         for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
 179                 SCR[LoopCnt] = 0;
 180         }
 181
 182         /*
 183          * Send block write command
 184          */
 185         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 186                         InstancePtr->RelCardAddr, 0);
 187         if (Status != XST_SUCCESS) {
 188                 Status = XST_FAILURE;
 189                 goto RETURN_PATH;
 190         }
 191
 192         BlkCnt = XSDPS_SCR_BLKCNT;
 193         BlkSize = XSDPS_SCR_BLKSIZE;
 194
 195         /*
 196          * Set block size to the value passed
 197          */
 198         BlkSize &= XSDPS_BLK_SIZE_MASK;
 199         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 200                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 201
 202         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
 203
 204         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 205                         XSDPS_XFER_MODE_OFFSET,
 206                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 207
 208         Xil_DCacheInvalidateRange(SCR, 8);
 209
 210         Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt);
 211         if (Status != XST_SUCCESS) {
 212                 Status = XST_FAILURE;
 213                 goto RETURN_PATH;
 214         }
 215
 216         /*
 217          * Check for transfer complete
 218          * Polling for response for now
 219          */
 220         do {
 221                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 222                                         XSDPS_NORM_INTR_STS_OFFSET);
 223                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 224                         /*
 225                          * Write to clear error bits
 226                          */
 227                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 228                                         XSDPS_ERR_INTR_STS_OFFSET,
 229                                         XSDPS_ERROR_INTR_ALL_MASK);
 230                         Status = XST_FAILURE;
 231                         goto RETURN_PATH;
 232                 }
 233         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 234
 235         /*
 236          * Write to clear bit
 237          */
 238         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 239                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 240
 241         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 242                         XSDPS_RESP0_OFFSET);
 243
 244         Status = XST_SUCCESS;
 245
 246         RETURN_PATH:
 247                 return Status;
 248
 249 }
 250
 251 /*****************************************************************************/
 252 /**
 253 *
 254 * API to set bus width to 4-bit in card and host
 255 *
 256 *
 257 * @param        InstancePtr is a pointer to the XSdPs instance.
 258 *
 259 * @return
 260 *               - XST_SUCCESS if successful.
 261 *               - XST_FAILURE if fail.
 262 *
 263 * @note         None.
 264 *
 265 ******************************************************************************/
 266 int XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 267 {
 268         u32 Status = 0;
 269         u32 StatusReg = 0x0;
 270         u32 Arg = 0;
 271
 272         Xil_AssertNonvoid(InstancePtr != NULL);
 273         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 274
 275 #ifndef MMC_CARD
 276
 277         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 278                         InstancePtr->RelCardAddr, 0);
 279         if (Status != XST_SUCCESS) {
 280                 Status = XST_FAILURE;
 281                 goto RETURN_PATH;
 282         }
 283
 284         Arg = XSDPS_4_BIT_WIDTH;
 285         Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
 286         if (Status != XST_SUCCESS) {
 287                 Status = XST_FAILURE;
 288                 goto RETURN_PATH;
 289         }
 290
 291         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 292                                         XSDPS_HOST_CTRL1_OFFSET);
 293         StatusReg |= XSDPS_HC_WIDTH_MASK;
 294         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 295                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 296
 297         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 298                         XSDPS_RESP0_OFFSET);
 299
 300 #else
 301
 302         Arg = XSDPS_MMC_4_BIT_BUS_ARG;
 303         Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
 304         if (Status != XST_SUCCESS) {
 305                 Status = XST_FAILURE;
 306                 goto RETURN_PATH;
 307         }
 308
 309 #ifdef __arm__
 310
 311         usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 312
 313 #endif
 314
 315 #ifdef __MICROBLAZE__
 316
 317         /* 2 msec delay */
 318         MB_Sleep(2);
 319
 320 #endif
 321
 322         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 323                                         XSDPS_HOST_CTRL1_OFFSET);
 324         StatusReg |= XSDPS_HC_WIDTH_MASK;
 325         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 326                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 327
 328         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 329                         XSDPS_RESP0_OFFSET);
 330
 331 #endif
 332
 333         Status = XST_SUCCESS;
 334
 335         RETURN_PATH:
 336                 return Status;
 337
 338 }
 339
 340 /*****************************************************************************/
 341 /**
 342 *
 343 * API to get bus speed supported by card.
 344 *
 345 *
 346 * @param        InstancePtr is a pointer to the XSdPs instance.
 347 * @param        ReadBuff - buffer to store function group support data
 348 *               returned by card.
 349 *
 350 * @return
 351 *               - XST_SUCCESS if successful.
 352 *               - XST_FAILURE if fail.
 353 *
 354 * @note         None.
 355 *
 356 ******************************************************************************/
 357 int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 358 {
 359         u32 Status = 0;
 360         u32 StatusReg = 0x0;
 361         u32 Arg = 0;
 362         u16 BlkCnt;
 363         u16 BlkSize;
 364         int LoopCnt;
 365
 366         Xil_AssertNonvoid(InstancePtr != NULL);
 367         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 368
 369         for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
 370                 ReadBuff[LoopCnt] = 0;
 371         }
 372
 373         BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
 374         BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
 375         BlkSize &= XSDPS_BLK_SIZE_MASK;
 376         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 377                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 378
 379         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 380
 381         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 382                         XSDPS_XFER_MODE_OFFSET,
 383                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 384
 385         Arg = XSDPS_SWITCH_CMD_HS_GET;
 386
 387         Xil_DCacheInvalidateRange(ReadBuff, 64);
 388
 389         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
 390         if (Status != XST_SUCCESS) {
 391                 Status = XST_FAILURE;
 392                 goto RETURN_PATH;
 393         }
 394
 395         /*
 396          * Check for transfer complete
 397          * Polling for response for now
 398          */
 399         do {
 400                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 401                                         XSDPS_NORM_INTR_STS_OFFSET);
 402                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 403                         /*
 404                          * Write to clear error bits
 405                          */
 406                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 407                                         XSDPS_ERR_INTR_STS_OFFSET,
 408                                         XSDPS_ERROR_INTR_ALL_MASK);
 409                         Status = XST_FAILURE;
 410                         goto RETURN_PATH;
 411                 }
 412         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 413
 414         /*
 415          * Write to clear bit
 416          */
 417         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 418                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 419
 420         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 421                         XSDPS_RESP0_OFFSET);
 422
 423         Status = XST_SUCCESS;
 424
 425         RETURN_PATH:
 426                 return Status;
 427
 428 }
 429
 430 /*****************************************************************************/
 431 /**
 432 *
 433 * API to set high speed in card and host. Changes clock in host accordingly.
 434 *
 435 *
 436 * @param        InstancePtr is a pointer to the XSdPs instance.
 437 *
 438 * @return
 439 *               - XST_SUCCESS if successful.
 440 *               - XST_FAILURE if fail.
 441 *
 442 * @note         None.
 443 *
 444 ******************************************************************************/
 445 int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 446 {
 447         u32 Status = 0;
 448         u32 StatusReg = 0x0;
 449         u32 Arg = 0;
 450
 451 #ifndef MMC_CARD
 452         u32 ClockReg;
 453         u8 ReadBuff[64];
 454         u16 BlkCnt;
 455         u16 BlkSize;
 456 #endif
 457
 458         Xil_AssertNonvoid(InstancePtr != NULL);
 459         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 460
 461 #ifndef MMC_CARD
 462
 463         BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
 464         BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
 465         BlkSize &= XSDPS_BLK_SIZE_MASK;
 466         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 467                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 468
 469         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 470
 471         Xil_DCacheInvalidateRange(ReadBuff, 64);
 472
 473         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 474                         XSDPS_XFER_MODE_OFFSET,
 475                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 476
 477         Arg = XSDPS_SWITCH_CMD_HS_SET;
 478         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
 479         if (Status != XST_SUCCESS) {
 480                 Status = XST_FAILURE;
 481                 goto RETURN_PATH;
 482         }
 483
 484         /*
 485          * Check for transfer complete
 486          * Polling for response for now
 487          */
 488         do {
 489                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 490                                         XSDPS_NORM_INTR_STS_OFFSET);
 491                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 492                         /*
 493                          * Write to clear error bits
 494                          */
 495                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 496                                         XSDPS_ERR_INTR_STS_OFFSET,
 497                                         XSDPS_ERROR_INTR_ALL_MASK);
 498                         Status = XST_FAILURE;
 499                         goto RETURN_PATH;
 500                 }
 501         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 502
 503         /*
 504          * Write to clear bit
 505          */
 506         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 507                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 508
 509         /*
 510          * Change the clock frequency to 50 MHz
 511          */
 512         Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ);
 513         if (Status != XST_SUCCESS) {
 514                         Status = XST_FAILURE;
 515                         goto RETURN_PATH;
 516         }
 517
 518         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 519                                         XSDPS_HOST_CTRL1_OFFSET);
 520         StatusReg |= XSDPS_HC_SPEED_MASK;
 521         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 522                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 523
 524         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 525                         XSDPS_RESP0_OFFSET);
 526
 527 #else
 528
 529         Arg = XSDPS_MMC_HIGH_SPEED_ARG;
 530         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0);
 531         if (Status != XST_SUCCESS) {
 532                 Status = XST_FAILURE;
 533                 goto RETURN_PATH;
 534         }
 535
 536 #ifdef __arm__
 537
 538         usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 539
 540 #endif
 541
 542 #ifdef __MICROBLAZE__
 543
 544         /* 2 msec delay */
 545         MB_Sleep(2);
 546
 547 #endif
 548
 549         XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
 550
 551         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 552                                         XSDPS_HOST_CTRL1_OFFSET);
 553         StatusReg |= XSDPS_HC_SPEED_MASK;
 554         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 555                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 556
 557         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 558                         XSDPS_RESP0_OFFSET);
 559 #endif
 560
 561         Status = XST_SUCCESS;
 562
 563         RETURN_PATH:
 564                 return Status;
 565
 566 }
 567
 568 /*****************************************************************************/
 569 /**
 570 *
 571 * API to change clock freq to given value.
 572 *
 573 *
 574 * @param        InstancePtr is a pointer to the XSdPs instance.
 575 * @param        SelFreq - Clock frequency in Hz.
 576 *
 577 * @return       None
 578 *
 579 * @note         This API will change clock frequency to the value less than
 580 *               or equal to the given value using the permissible dividors.
 581 *
 582 ******************************************************************************/
 583 int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 584 {
 585         u16 ClockReg;
 586         int DivCnt;
 587         u16 Divisor;
 588         u16 ClkLoopCnt;
 589         int Status;
 590
 591         Xil_AssertNonvoid(InstancePtr != NULL);
 592         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 593
 594         /*
 595          * Disable clock
 596          */
 597         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 598                         XSDPS_CLK_CTRL_OFFSET);
 599         ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
 600
 601         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 602                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 603
 604         /*
 605          * Calculate divisor
 606          */
 607         DivCnt = 0x1;
 608         for(ClkLoopCnt = 0; ClkLoopCnt < XSDPS_CC_MAX_NUM_OF_DIV;
 609                 ClkLoopCnt++) {
 610                 if( ((InstancePtr->Config.InputClockHz)/DivCnt) <= SelFreq) {
 611                         Divisor = DivCnt/2;
 612                         Divisor = Divisor << XSDPS_CC_DIV_SHIFT;
 613                         break;
 614                 }
 615                 DivCnt = DivCnt << 1;
 616         }
 617
 618         if(ClkLoopCnt == 9) {
 619
 620                 /*
 621                  * No valid divisor found for given frequency
 622                  */
 623                 Status = XST_FAILURE;
 624                 goto RETURN_PATH;
 625         }
 626
 627         /*
 628          * Set clock divisor
 629          */
 630         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 631                         XSDPS_CLK_CTRL_OFFSET);
 632         ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
 633
 634         ClockReg |= Divisor | XSDPS_CC_INT_CLK_EN_MASK;
 635         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 636                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 637
 638         /*
 639          * Wait for internal clock to stabilize
 640          */
 641         while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 642                 XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
 643
 644         /*
 645          * Enable SD clock
 646          */
 647         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 648                         XSDPS_CLK_CTRL_OFFSET);
 649         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 650                         XSDPS_CLK_CTRL_OFFSET,
 651                         ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
 652
 653         Status = XST_SUCCESS;
 654
 655         RETURN_PATH:
 656                 return Status;
 657
 658 }
 659
 660 /*****************************************************************************/
 661 /**
 662 *
 663 * API to send pullup command to card before using DAT line 3(using 4-bit bus)
 664 *
 665 *
 666 * @param        InstancePtr is a pointer to the XSdPs instance.
 667 *
 668 * @return
 669 *               - XST_SUCCESS if successful.
 670 *               - XST_FAILURE if fail.
 671 *
 672 * @note         None.
 673 *
 674 ******************************************************************************/
 675 int XSdPs_Pullup(XSdPs *InstancePtr)
 676 {
 677         u32 Status = 0;
 678
 679         Xil_AssertNonvoid(InstancePtr != NULL);
 680         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 681
 682         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 683                         InstancePtr->RelCardAddr, 0);
 684         if (Status != XST_SUCCESS) {
 685                 Status = XST_FAILURE;
 686                 goto RETURN_PATH;
 687         }
 688
 689         Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0);
 690         if (Status != XST_SUCCESS) {
 691                 Status = XST_FAILURE;
 692                 goto RETURN_PATH;
 693         }
 694
 695         Status = XST_SUCCESS;
 696
 697         RETURN_PATH:
 698                 return Status;
 699
 700 }
 701
 702 /*****************************************************************************/
 703 /**
 704 *
 705 * API to get EXT_CSD register of eMMC.
 706 *
 707 *
 708 * @param        InstancePtr is a pointer to the XSdPs instance.
 709 * @param        ReadBuff - buffer to store EXT_CSD
 710 *
 711 * @return
 712 *               - XST_SUCCESS if successful.
 713 *               - XST_FAILURE if fail.
 714 *
 715 * @note         None.
 716 *
 717 ******************************************************************************/
 718 int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 719 {
 720         u32 Status = 0;
 721         u32 StatusReg = 0x0;
 722         u32 Arg = 0;
 723         u16 BlkCnt;
 724         u16 BlkSize;
 725         int LoopCnt;
 726
 727         Xil_AssertNonvoid(InstancePtr != NULL);
 728         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 729
 730         for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
 731                 ReadBuff[LoopCnt] = 0;
 732         }
 733
 734         BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
 735         BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
 736         BlkSize &= XSDPS_BLK_SIZE_MASK;
 737         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 738                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 739
 740         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 741
 742         Xil_DCacheInvalidateRange(ReadBuff, 512);
 743
 744         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 745                         XSDPS_XFER_MODE_OFFSET,
 746                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 747
 748         Arg = 0;
 749
 750         /*
 751          * Send SEND_EXT_CSD command
 752          */
 753         Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1);
 754         if (Status != XST_SUCCESS) {
 755                 Status = XST_FAILURE;
 756                 goto RETURN_PATH;
 757         }
 758
 759         /*
 760          * Check for transfer complete
 761          * Polling for response for now
 762          */
 763         do {
 764                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 765                                         XSDPS_NORM_INTR_STS_OFFSET);
 766                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 767                         /*
 768                          * Write to clear error bits
 769                          */
 770                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 771                                         XSDPS_ERR_INTR_STS_OFFSET,
 772                                         XSDPS_ERROR_INTR_ALL_MASK);
 773                         Status = XST_FAILURE;
 774                         goto RETURN_PATH;
 775                 }
 776         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 777
 778         /*
 779          * Write to clear bit
 780          */
 781         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 782                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 783
 784         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 785                         XSDPS_RESP0_OFFSET);
 786
 787         Status = XST_SUCCESS;
 788
 789         RETURN_PATH:
 790                 return Status;
 791
 792 }