1 /**************************************************************************//**
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2 * @file efm32gg980f512.h
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3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
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6 ******************************************************************************
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8 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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9 ******************************************************************************
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11 * Permission is granted to anyone to use this software for any purpose,
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12 * including commercial applications, and to alter it and redistribute it
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13 * freely, subject to the following restrictions:
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15 * 1. The origin of this software must not be misrepresented; you must not
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16 * claim that you wrote the original software.@n
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17 * 2. Altered source versions must be plainly marked as such, and must not be
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18 * misrepresented as being the original software.@n
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19 * 3. This notice may not be removed or altered from any source distribution.
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21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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23 * providing the Software "AS IS", with no express or implied warranties of any
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24 * kind, including, but not limited to, any implied warranties of
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25 * merchantability or fitness for any particular purpose or warranties against
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26 * infringement of any proprietary rights of a third party.
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28 * Silicon Laboratories, Inc. will not be liable for any consequential,
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29 * incidental, or special damages, or any other relief, or for any claim by
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30 * any third party, arising from your use of this Software.
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32 *****************************************************************************/
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34 #ifndef __SILICON_LABS_EFM32GG980F512_H__
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35 #define __SILICON_LABS_EFM32GG980F512_H__
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41 /**************************************************************************//**
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44 *****************************************************************************/
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46 /**************************************************************************//**
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47 * @defgroup EFM32GG980F512 EFM32GG980F512
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49 *****************************************************************************/
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51 /** Interrupt Number Definition */
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54 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/
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55 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
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56 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
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57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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58 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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59 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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60 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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62 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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63 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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65 /****** EFM32G Peripheral Interrupt Numbers **********************************************/
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66 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
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67 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
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68 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
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69 USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
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70 USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
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71 USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
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72 ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
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73 ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
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74 DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
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75 I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
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76 I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
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77 GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
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78 TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
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79 TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
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80 TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
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81 USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
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82 USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
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83 LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
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84 USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
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85 USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
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86 UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
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87 UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
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88 UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
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89 UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
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90 LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
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91 LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
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92 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
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93 PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
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94 PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
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95 PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
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96 RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
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97 BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
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98 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
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99 VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
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100 LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
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101 MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
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102 AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
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103 EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
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104 EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
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107 /**************************************************************************//**
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108 * @defgroup EFM32GG980F512_Core EFM32GG980F512 Core
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110 * @brief Processor and Core Peripheral Section
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111 *****************************************************************************/
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112 #define __MPU_PRESENT 1 /**< Presence of MPU */
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113 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
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114 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
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116 /** @} End of group EFM32GG980F512_Core */
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118 /**************************************************************************//**
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119 * @defgroup EFM32GG980F512_Part EFM32GG980F512 Part
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121 ******************************************************************************/
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124 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
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125 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
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126 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
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127 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
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129 /* If part number is not defined as compiler option, define it */
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130 #if !defined(EFM32GG980F512)
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131 #define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */
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134 /** Configure part number */
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135 #define PART_NUMBER "EFM32GG980F512" /**< Part Number */
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137 /** Memory Base addresses and limits */
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138 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
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139 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
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140 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
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141 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
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142 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
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143 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
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144 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
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145 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
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146 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
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147 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
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148 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
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149 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
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150 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
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151 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
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152 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
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153 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
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154 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
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155 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
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156 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
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157 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
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158 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
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159 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
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160 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
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161 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
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162 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
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163 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
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164 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
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165 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
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166 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
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167 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
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168 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
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169 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
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171 /** Bit banding area */
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172 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
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173 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
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175 /** Flash and SRAM limits for EFM32GG980F512 */
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176 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
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177 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
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178 #define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
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179 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
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180 #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
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181 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
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182 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
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183 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
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185 /** AF channels connect the different on-chip peripherals with the af-mux */
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186 #define AFCHAN_MAX 163
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187 #define AFCHANLOC_MAX 7
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188 /** Analog AF channels */
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189 #define AFACHAN_MAX 53
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191 /* Part number capabilities */
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193 #define LETIMER_PRESENT /**< LETIMER is available in this part */
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194 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
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195 #define USART_PRESENT /**< USART is available in this part */
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196 #define USART_COUNT 3 /**< 3 USARTs available */
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197 #define UART_PRESENT /**< UART is available in this part */
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198 #define UART_COUNT 2 /**< 2 UARTs available */
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199 #define TIMER_PRESENT /**< TIMER is available in this part */
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200 #define TIMER_COUNT 4 /**< 4 TIMERs available */
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201 #define ACMP_PRESENT /**< ACMP is available in this part */
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202 #define ACMP_COUNT 2 /**< 2 ACMPs available */
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203 #define I2C_PRESENT /**< I2C is available in this part */
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204 #define I2C_COUNT 2 /**< 2 I2Cs available */
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205 #define LEUART_PRESENT /**< LEUART is available in this part */
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206 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
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207 #define PCNT_PRESENT /**< PCNT is available in this part */
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208 #define PCNT_COUNT 3 /**< 3 PCNTs available */
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209 #define ADC_PRESENT /**< ADC is available in this part */
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210 #define ADC_COUNT 1 /**< 1 ADCs available */
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211 #define DAC_PRESENT /**< DAC is available in this part */
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212 #define DAC_COUNT 1 /**< 1 DACs available */
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213 #define DMA_PRESENT
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214 #define DMA_COUNT 1
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215 #define AES_PRESENT
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216 #define AES_COUNT 1
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217 #define USBC_PRESENT
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218 #define USBC_COUNT 1
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219 #define USB_PRESENT
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220 #define USB_COUNT 1
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223 #define MSC_PRESENT
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224 #define MSC_COUNT 1
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225 #define EMU_PRESENT
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226 #define EMU_COUNT 1
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227 #define RMU_PRESENT
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228 #define RMU_COUNT 1
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229 #define CMU_PRESENT
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230 #define CMU_COUNT 1
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231 #define LESENSE_PRESENT
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232 #define LESENSE_COUNT 1
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233 #define RTC_PRESENT
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234 #define RTC_COUNT 1
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235 #define EBI_PRESENT
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236 #define EBI_COUNT 1
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237 #define GPIO_PRESENT
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238 #define GPIO_COUNT 1
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239 #define VCMP_PRESENT
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240 #define VCMP_COUNT 1
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241 #define PRS_PRESENT
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242 #define PRS_COUNT 1
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243 #define OPAMP_PRESENT
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244 #define OPAMP_COUNT 1
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247 #define LCD_PRESENT
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248 #define LCD_COUNT 1
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249 #define BURTC_PRESENT
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250 #define BURTC_COUNT 1
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251 #define HFXTAL_PRESENT
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252 #define HFXTAL_COUNT 1
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253 #define LFXTAL_PRESENT
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254 #define LFXTAL_COUNT 1
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255 #define WDOG_PRESENT
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256 #define WDOG_COUNT 1
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257 #define DBG_PRESENT
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258 #define DBG_COUNT 1
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259 #define ETM_PRESENT
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260 #define ETM_COUNT 1
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261 #define BOOTLOADER_PRESENT
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262 #define BOOTLOADER_COUNT 1
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263 #define ANALOG_PRESENT
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264 #define ANALOG_COUNT 1
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266 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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267 #include "system_efm32gg.h" /* System Header */
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269 /** @} End of group EFM32GG980F512_Part */
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271 /**************************************************************************//**
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272 * @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs
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274 * @brief Device Specific Peripheral Register Structures
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275 *****************************************************************************/
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277 #include "efm32gg_dma_ch.h"
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278 #include "efm32gg_dma.h"
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279 #include "efm32gg_aes.h"
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280 #include "efm32gg_usb_hc.h"
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281 #include "efm32gg_usb_diep.h"
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282 #include "efm32gg_usb_doep.h"
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283 #include "efm32gg_usb.h"
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284 #include "efm32gg_msc.h"
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285 #include "efm32gg_emu.h"
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286 #include "efm32gg_rmu.h"
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287 #include "efm32gg_cmu.h"
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288 #include "efm32gg_lesense_st.h"
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289 #include "efm32gg_lesense_buf.h"
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290 #include "efm32gg_lesense_ch.h"
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291 #include "efm32gg_lesense.h"
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292 #include "efm32gg_rtc.h"
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293 #include "efm32gg_letimer.h"
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294 #include "efm32gg_ebi.h"
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295 #include "efm32gg_usart.h"
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296 #include "efm32gg_timer_cc.h"
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297 #include "efm32gg_timer.h"
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298 #include "efm32gg_acmp.h"
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299 #include "efm32gg_i2c.h"
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300 #include "efm32gg_gpio_p.h"
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301 #include "efm32gg_gpio.h"
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302 #include "efm32gg_vcmp.h"
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303 #include "efm32gg_prs_ch.h"
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304 #include "efm32gg_prs.h"
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305 #include "efm32gg_leuart.h"
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306 #include "efm32gg_pcnt.h"
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307 #include "efm32gg_adc.h"
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308 #include "efm32gg_dac.h"
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309 #include "efm32gg_lcd.h"
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310 #include "efm32gg_burtc_ret.h"
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311 #include "efm32gg_burtc.h"
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312 #include "efm32gg_wdog.h"
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313 #include "efm32gg_etm.h"
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314 #include "efm32gg_dma_descriptor.h"
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315 #include "efm32gg_devinfo.h"
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316 #include "efm32gg_romtable.h"
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317 #include "efm32gg_calibrate.h"
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319 /** @} End of group EFM32GG980F512_Peripheral_TypeDefs */
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321 /**************************************************************************//**
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322 * @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map
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324 *****************************************************************************/
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326 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
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327 #define AES_BASE (0x400E0000UL) /**< AES base address */
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328 #define USB_BASE (0x400C4000UL) /**< USB base address */
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329 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
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330 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
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331 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
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332 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
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333 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
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334 #define RTC_BASE (0x40080000UL) /**< RTC base address */
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335 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
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336 #define EBI_BASE (0x40008000UL) /**< EBI base address */
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337 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
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338 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
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339 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
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340 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
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341 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
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342 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
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343 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
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344 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
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345 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
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346 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
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347 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
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348 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
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349 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
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350 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
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351 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
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352 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
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353 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
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354 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
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355 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
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356 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
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357 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
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358 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
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359 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
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360 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
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361 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
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362 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
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363 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
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364 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
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365 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
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366 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
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367 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
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368 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
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370 /** @} End of group EFM32GG980F512_Peripheral_Base */
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372 /**************************************************************************//**
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373 * @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations
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375 *****************************************************************************/
\r
377 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
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378 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
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379 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
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380 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
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381 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
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382 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
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383 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
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384 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
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385 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
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386 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
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387 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
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388 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
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389 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
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390 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
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391 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
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392 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
\r
393 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
\r
394 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
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395 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
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396 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
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397 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
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398 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
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399 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
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400 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
\r
401 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
\r
402 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
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403 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
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404 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
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405 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
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406 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
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407 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
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408 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
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409 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
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410 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
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411 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
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412 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
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413 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
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414 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
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415 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
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416 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
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417 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
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419 /** @} End of group EFM32GG980F512_Peripheral_Declaration */
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421 /**************************************************************************//**
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422 * @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields
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424 *****************************************************************************/
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426 #include "efm32gg_prs_signals.h"
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427 #include "efm32gg_dmareq.h"
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428 #include "efm32gg_dmactrl.h"
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429 #include "efm32gg_uart.h"
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431 /**************************************************************************//**
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432 * @defgroup EFM32GG980F512_UNLOCK EFM32GG980F512 Unlock Codes
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434 *****************************************************************************/
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435 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
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436 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
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437 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
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438 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
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439 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
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440 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
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442 /** @} End of group EFM32GG980F512_UNLOCK */
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444 /** @} End of group EFM32GG980F512_BitFields */
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446 /**************************************************************************//**
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447 * @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function
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449 *****************************************************************************/
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451 #include "efm32gg_af_ports.h"
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452 #include "efm32gg_af_pins.h"
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454 /** @} End of group EFM32GG980F512_Alternate_Function */
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456 /**************************************************************************//**
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457 * @brief Set the value of a bit field within a register.
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460 * The register to update
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462 * The mask for the bit field to update
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464 * The value to write to the bit field
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466 * The number of bits that the field is offset within the register.
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467 * 0 (zero) means LSB.
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468 *****************************************************************************/
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469 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
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470 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
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472 /** @} End of group EFM32GG980F512 */
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474 /** @} End of group Parts */
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479 #endif /* __SILICON_LABS_EFM32GG980F512_H__ */
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projects / freertos / blob