2 * @brief CAN registers and control functions
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5 * Copyright(C) NXP Semiconductors, 2012
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6 * All rights reserved.
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * LPC products. This software is supplied "AS IS" without any warranties of
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12 * any kind, and NXP Semiconductors and its licensor disclaim any and
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13 * all warranties, express or implied, including all implied warranties of
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14 * merchantability, fitness for a particular purpose and non-infringement of
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15 * intellectual property rights. NXP Semiconductors assumes no responsibility
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16 * or liability for the use of the software, conveys no license or rights under any
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17 * patent, copyright, mask work right, or any other intellectual property rights in
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18 * or to any products. NXP Semiconductors reserves the right to make changes
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19 * in the software without notification. NXP Semiconductors also makes no
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20 * representation or warranty that such application will be suitable for the
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21 * specified use without further testing or modification.
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24 * Permission to use, copy, modify, and distribute this software and its
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25 * documentation is hereby granted, under NXP Semiconductors' and its
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26 * licensor's relevant copyrights in the software, without fee, provided that it
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27 * is used in conjunction with NXP Semiconductors microcontrollers. This
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28 * copyright, permission, and disclaimer notice must appear in all copies of
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32 #ifndef __CAN_001_H_
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33 #define __CAN_001_H_
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35 #include "sys_config.h"
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42 /** @defgroup IP_CAN_001 IP: CAN register block and driver
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43 * @ingroup IP_Drivers
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44 * Controller Area Network
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48 /** The number of entry in AF RAM region */
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49 #define CANAF_RAM_ENTRY_NUM 512
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52 * @brief CAN AF RAM section definitions
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54 typedef enum IP_CAN_AF_RAM_SECTION {
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55 CANAF_RAM_FULLCAN_SEC, /*!<FullCAN Section*/
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56 CANAF_RAM_SFF_SEC, /*!<Standard ID Section*/
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57 CANAF_RAM_SFF_GRP_SEC, /*!<Group Standard ID Section*/
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58 CANAF_RAM_EFF_SEC, /*!<Extended ID Section*/
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59 CANAF_RAM_EFF_GRP_SEC, /*!<Group Extended ID Section*/
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60 CANAF_RAM_SECTION_NUM,
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61 } IP_CAN_AF_RAM_SECTION_T;
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64 * @brief CAN acceptance filter RAM register block structure
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66 typedef struct /*!< AF RAM Mask Table */
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68 __IO uint32_t MASK[CANAF_RAM_ENTRY_NUM]; /*!< Acceptance Filter RAM ID mask register */
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69 } IP_CAN_001_AF_RAM_T;
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72 * @brief CAN acceptance filter register block structure
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74 typedef struct /*!< CAN AF structure */
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76 __IO uint32_t AFMR; /*!< Acceptance Filter Register */
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77 __IO uint32_t ENDADDR[CANAF_RAM_SECTION_NUM]; /*!< Start/End Address Registers */
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78 __I uint32_t LUTERRAD; /*!< LUT Error Address Register */
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79 __I uint32_t LUTERR; /*!< LUT Error Register */
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80 __IO uint32_t FCANIE; /*!< Global FullCANInterrupt Enable Register */
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81 __IO uint32_t FCANIC[2]; /*!< FullCAN Interrupt and Capture Registers */
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85 * @brief Central CAN register block structure
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87 typedef struct /*!< Central CAN structure */
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89 __I uint32_t TXSR; /*!< CAN Central Transmit Status Register */
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90 __I uint32_t RXSR; /*!< CAN Central Receive Status Register */
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91 __I uint32_t MSR; /*!< CAN Central Miscellaneous Register */
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95 * @brief CAN Transmit register block structure
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97 typedef struct /*!< CAN Transmit structure */
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99 __IO uint32_t TFI; /*!< CAN Transmit Frame Information register*/
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100 __IO uint32_t TID; /*!< CAN Transfer Identifier register*/
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101 __IO uint32_t TD[2]; /*!<CAN Transmit Data register*/
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105 * @brief CAN Receive register block structure
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107 typedef struct /*!< CAN Receive Frame structure */
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109 __IO uint32_t RFS; /*!< Characteristic of the received frame. It includes the following characteristics:
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110 CAN_RFS_BP: indicate that the current message is received in Bypass mode.
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111 * CAN_RFS_RTR: indicate the value of Remote Transmission Request bit in the current message.
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112 * CAN_RFS_FF: indicate that the identifier in the current message is 11-bit or 29-bit identifier.
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113 Use CAN_RFS_ID_INDEX(RFS value) to get the ID Index of the matched entry in the Lookup Table RAM.
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114 Use CAN_RFS_DLC(RFS value) to get the Data Length Code field of the current received message.
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116 __IO uint32_t RID; /*!<Identifier in the received message. Use RFS field to determine if it is 11-bit or 29-bit identifier.*/
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117 __IO uint32_t RD[2]; /*!< Data bytes of the received message. Use DLC value in RFS fied to determine the number of data bytes.*/
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121 * @brief CAN register block structure
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123 typedef struct /*!< CANn structure */
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125 __IO uint32_t MOD; /*!< CAN Mode Register */
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126 __O uint32_t CMR; /*!< CAN Command Register */
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127 __IO uint32_t GSR; /*!< CAN Global Status Register */
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128 __I uint32_t ICR; /*!< CAN Interrupt and Capture Register */
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129 __IO uint32_t IER; /*!< CAN Interrupt Enable Register*/
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130 __IO uint32_t BTR; /*!< CAN Bus Timing Register*/
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131 __IO uint32_t EWL; /*!< CAN Error Warning Limit Register*/
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132 __I uint32_t SR; /*!< CAN Status Register*/
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133 __IO IP_CAN_001_RX_T RX; /*!< CAN Receive Registers*/
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134 __IO IP_CAN_001_TX_T TX[3]; /*!< CAN Transmit Registers*/
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138 * @brief CAN Mode register definitions
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140 /** CAN Mode Register Bitmask */
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141 #define CAN_MOD_BITMASK (0xBF)
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143 /** CAN Operationg Mode */
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144 #define CAN_MOD_OPERATION ((uint32_t) 0)
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146 /** CAN Reset mode */
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147 #define CAN_MOD_RM ((uint32_t) (1 << 0))
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149 /** CAN Listen Only Mode (Don't send ACK/Message)*/
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150 #define CAN_MOD_LOM ((uint32_t) (1 << 1))
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152 /** CAN Self Test mode (Don't care ACK after sending message)*/
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153 #define CAN_MOD_STM ((uint32_t) (1 << 2))
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155 /** CAN Transmit Priority mode (Determine the transmit priority basing on Tx Priority Register)*/
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156 #define CAN_MOD_TPM ((uint32_t) (1 << 3))
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158 /** CAN Sleep mode */
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159 #define CAN_MOD_SM ((uint32_t) (1 << 4))
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161 /** CAN Receive Polarity mode (Determine RD is active Low or High).*/
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162 #define CAN_MOD_RPM ((uint32_t) (1 << 5))
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164 /** CAN Test mode (TD pin will reflects the bit detected on RD pin)*/
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165 #define CAN_MOD_TM ((uint32_t) (1 << 7))
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168 * @brief CAN Command register definitions
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170 /** CAN Command Register Bitmask */
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171 #define CAN_CMR_BITMASK (0xFF)
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173 /** Request to Send message which is available in selected Transmit Buffer*/
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174 #define CAN_CMR_TR ((uint32_t) (1))
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176 /** Cancel the current transmission or the pending transmission request*/
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177 #define CAN_CMR_AT ((uint32_t) (1 << 1))
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179 /** Release the information in Receive Buffer */
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180 #define CAN_CMR_RRB ((uint32_t) (1 << 2))
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182 /** Clear the Data Overrun bit in Status Register(s)*/
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183 #define CAN_CMR_CDO ((uint32_t) (1 << 3))
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185 /** Self Reception Request.The message sent is received simultaneously. */
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186 #define CAN_CMR_SRR ((uint32_t) (1 << 4))
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188 /** Select one or multi transmit buffer(s).( n = 0/1/2) */
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189 #define CAN_CMR_STB(n) ((uint32_t) (1 << (n + 5)))
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192 * @brief CAN Global Status register definitions
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194 /** CAN Global Status Register Bitmask */
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195 #define CAN_GSR_BITMASK (0xFFFF00FF)
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197 /** CAN Receive Buffer Status (At least one complete message is received) */
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198 #define CAN_GSR_RBS ((uint32_t) (1))
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200 /** CAN Data Overrun Status */
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201 #define CAN_GSR_DOS ((uint32_t) (1 << 1))
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203 /** CAN Transmit Buffer Status (All 3 Transmit Buffers are available)*/
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204 #define CAN_GSR_TBS ((uint32_t) (1 << 2))
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206 /** CAN Transmit Complete Status (All requested transmission(s) has (have) been successfully completed)*/
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207 #define CAN_GSR_TCS ((uint32_t) (1 << 3))
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209 /** CAN Receive Status (The CAN controller is receiving a message)*/
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210 #define CAN_GSR_RS ((uint32_t) (1 << 4))
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212 /** CAN Transmit Status (The CAN controller is sending a message)*/
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213 #define CAN_GSR_TS ((uint32_t) (1 << 5))
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215 /** CAN Error Status */
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216 #define CAN_GSR_ES ((uint32_t) (1 << 6))
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218 /** CAN Bus Status (CAN Controller is involed in bus activity or not*/
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219 #define CAN_GSR_BS ((uint32_t) (1 << 7))
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221 /** CAN Current value of the Rx Error Counter */
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222 #define CAN_GSR_RXERR(n) ((uint32_t) ((n >> 16) & 0xFF)
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224 /** CAN Current value of the Tx Error Counter */
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225 #define CAN_GSR_TXERR(n) ((uint32_t) ((n >> 24) & 0xFF)
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228 * @brief CAN Interrupt and Capture register definitions
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230 /** CAN Interrupt and Capture Registe Bitmask */
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231 #define CAN_ICR_BITMASK (0xFFFF07FF)
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233 /** CAN Receive Interrupt (A new message was received)*/
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234 #define CAN_ICR_RI ((uint32_t) (1))
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236 /** CAN Transmit Interrupt (Transmit buffer 1 is available) */
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237 #define CAN_ICR_TI1 ((uint32_t) (1 << 1))
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239 /** CAN Error Warning Interrupt */
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240 #define CAN_ICR_EI ((uint32_t) (1 << 2))
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242 /** CAN Data Overrun Interrupt */
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243 #define CAN_ICR_DOI ((uint32_t) (1 << 3))
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245 /** CAN Wake-Up Interrupt */
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246 #define CAN_ICR_WUI ((uint32_t) (1 << 4))
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248 /** CAN Error Passive Interrupt */
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249 #define CAN_ICR_EPI ((uint32_t) (1 << 5))
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251 /** CAN Arbitration Lost Interrupt */
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252 #define CAN_ICR_ALI ((uint32_t) (1 << 6))
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254 /** CAN Bus Error Interrupt */
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255 #define CAN_ICR_BEI ((uint32_t) (1 << 7))
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257 /** CAN ID Ready Interrupt */
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258 #define CAN_ICR_IDI ((uint32_t) (1 << 8))
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260 /** CAN Transmit Interrupt 2 (Transmit buffer 2 is available) */
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261 #define CAN_ICR_TI2 ((uint32_t) (1 << 9))
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263 /** CAN Transmit Interrupt 3 (Transmit buffer 3 is available)*/
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264 #define CAN_ICR_TI3 ((uint32_t) (1 << 10))
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266 /** CAN Error Code Capture (Error Location)*/
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267 #define CAN_ICR_ERRBIT_VAL(n) ((uint32_t) (((n) >> 16) & 0x1F))
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268 /** Start of Frame error value */
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269 #define CAN_ICR_ERR_SOF (3)
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270 /** ID28...ID21 Error value */
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271 #define CAN_ICR_ERR_ID28_ID21 (2)
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272 /** ID28...ID21 Error value */
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273 #define CAN_ICR_ERR_ID20_ID18 (6)
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274 /**SRTR Bit Error value */
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275 #define CAN_ICR_ERR_SRTR (4)
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276 /**IDE Bit Error value */
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277 #define CAN_ICR_ERR_IDE (5)
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278 /** ID17...ID13 Error value */
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279 #define CAN_ICR_ERR_ID17_ID13 (7)
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280 /** ID12...ID15 Error value */
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281 #define CAN_ICR_ERR_ID12_ID5 (0x0F)
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282 /** ID4...ID0 Error value */
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283 #define CAN_ICR_ERR_ID4_ID0 (0x0E)
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284 /**RTR Bit Error value */
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285 #define CAN_ICR_ERR_RTR (0x0C)
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286 /**Reserved Bit 1 Error value */
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287 #define CAN_ICR_ERR_ReservedBit_1 (0x0D)
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288 /**Reserved Bit 0 Error value */
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289 #define CAN_ICR_ERR_ReservedBit_0 (0x09)
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290 /** DLC Error value */
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291 #define CAN_ICR_ERR_DLC (0x0B)
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292 /** Data Field Error value */
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293 #define CAN_ICR_ERR_DATA_FIELD (0x0A)
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294 /** CRC Sequence Error value */
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295 #define CAN_ICR_ERR_CRC_SEQ (0x08)
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296 /** CRC Delimiter Error value */
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297 #define CAN_ICR_ERR_CRC_DELIMITER (0x18)
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298 /** ACK Error value */
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299 #define CAN_ICR_ERR_ACK (0x19)
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300 /** ACK Delimiter Error value */
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301 #define CAN_ICR_ERR_ACK_DELIMITER (0x1B)
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302 /** EOF Error value */
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303 #define CAN_ICR_ERR_EOF (0x1A)
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304 /** Intermission Error value */
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305 #define CAN_ICR_ERR_INTERMISSION (0x12)
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307 /** CAN Error Direction */
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308 #define CAN_ICR_ERRDIR_RECEIVE ((uint32_t) (1 << 21))
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310 /** CAN Error Type Capture */
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311 #define CAN_ICR_ERRC_VAL(n) ((uint32_t) (((n) >> 22) & 0x3))
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312 #define CAN_ICR_BIT_ERROR (0)
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313 #define CAN_ICR_FORM_ERROR (1)
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314 #define CAN_ICR_STUFF_ERROR (2)
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315 #define CAN_ICR_OTHER_ERROR (3)
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317 /** CAN Arbitration Lost Capture */
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318 #define CAN_ICR_ALCBIT_VAL(n) ((uint32_t) (((n) >> 24) & 0xFF))
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321 * @brief CAN Interrupt Enable register definitions
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323 /** CAN Interrupt Enable Register Bitmask */
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324 #define CAN_IER_BITMASK (0x7FF)
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326 /** CAN Receive Interrupt Enable */
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327 #define CAN_IER_RIE ((uint32_t) (1))
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329 /** CAN Transmit Interrupt Enable for buffer 1 */
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330 #define CAN_IER_TIE1 ((uint32_t) (1 << 1))
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332 /** CAN Error Warning Interrupt Enable */
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333 #define CAN_IER_EIE ((uint32_t) (1 << 2))
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335 /** CAN Data Overrun Interrupt Enable */
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336 #define CAN_IER_DOIE ((uint32_t) (1 << 3))
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338 /** CAN Wake-Up Interrupt Enable */
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339 #define CAN_IER_WUIE ((uint32_t) (1 << 4))
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341 /** CAN Error Passive Interrupt Enable */
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342 #define CAN_IER_EPIE ((uint32_t) (1 << 5))
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344 /** CAN Arbitration Lost Interrupt Enable */
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345 #define CAN_IER_ALIE ((uint32_t) (1 << 6))
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347 /** CAN Bus Error Interrupt Enable */
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348 #define CAN_IER_BEIE ((uint32_t) (1 << 7))
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350 /** CAN ID Ready Interrupt Enable */
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351 #define CAN_IER_IDIE ((uint32_t) (1 << 8))
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353 /** CAN Transmit Enable Interrupt for Buffer 2 */
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354 #define CAN_IER_TIE2 ((uint32_t) (1 << 9))
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356 /** CAN Transmit Enable Interrupt for Buffer 3 */
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357 #define CAN_IER_TIE3 ((uint32_t) (1 << 10))
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360 * @brief CAN Bus Timing register definitions
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362 /** CAN Bus Timing Register Bitmask */
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363 #define CAN_BTR_BITMASK (0xFFC3FF)
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365 /** CAN Baudrate Prescaler */
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366 #define CAN_BTR_BRP(n) ((uint32_t) ((n) & 0x3FF))
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368 /** CAN Synchronization Jump Width */
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369 #define CAN_BTR_SJW(n) ((uint32_t) (((n) & 0x3) << 14))
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371 /** CAN Time Segment 1 */
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372 #define CAN_BTR_TESG1(n) ((uint32_t) (((n) & 0xF) << 16))
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374 /** CAN Time Segment 2 */
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375 #define CAN_BTR_TESG2(n) ((uint32_t) (((n) & 0xF) << 20))
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377 /** CAN Sampling */
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378 #define CAN_BTR_SAM ((uint32_t) (1 << 23))
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381 * @brief CAN Error Warning Limit register definitions
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383 /** CAN Error Warning Limit Register Bitmask */
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384 #define CAN_EWL_BITMASK (0xFF)
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386 /** CAN Error Warning Limit */
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387 #define CAN_EWL_VAL(n) ((uint32_t) ((n) & 0xFF))
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390 * @brief CAN Status Registe definitions
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392 /** CAN Status Registe Bitmask */
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393 #define CAN_SR_BITMASK (0xFFFFFF)
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395 /** CAN Receive Buffer Status (Bit 0, 8, 16 are the same)*/
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396 #define CAN_SR_RBS(n) ((uint32_t) (1 << ((n) * 8)))
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398 /** CAN Data Overrun Status (Bit 1, 9, 17 are the same)*/
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399 #define CAN_SR_DOS(n) ((uint32_t) (1 << (1 + (n) * 8)))
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401 /** CAN Transmit Buffer Status (Tx Buffer n=0/1/2 is available)*/
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402 #define CAN_SR_TBS(n) ((uint32_t) (1 << (2 + (n) * 8)))
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404 /** CAN Transmission Complete Status (The request on Tx Buffer n=0/1/2 has been completed) */
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405 #define CAN_SR_TCS(n) ((uint32_t) (1 << (3 + (n) * 8)))
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407 /** CAN Receive Status (Bit 4, 12, 20 are the same)*/
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408 #define CAN_SR_RS(n) ((uint32_t) (1 << (4 + (n) * 8)))
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410 /** CAN Transmit Status (The CAN controller is sending a message in Tx Buffer n=0/1/2) */
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411 #define CAN_SR_TS(n) ((uint32_t) (1 << (5 + (n) * 8)))
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413 /** CAN Error Status (Bit 6, 14, 22 are the same)*/
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414 #define CAN_SR_ES(n) ((uint32_t) (1 << (6 + (n) * 8)))
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416 /** CAN Bus Status (Bit 7, 15, 23 are the same)*/
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417 #define CAN_SR_BS(n) ((uint32_t) (1 << (7 + (n) * 8)))
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420 * @brief CAN Receive Frame Status register definitions
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422 /** CAN Receive Frame Status Register Bitmask */
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423 #define CAN_RFS_BITMASK (0xC00F07FF)
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425 /** CAN ID Index */
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426 #define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))
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429 #define CAN_RFS_BP ((uint32_t) (1 << 10))
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431 /** CAN Data Length Code */
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432 #define CAN_RFS_DLC(n) ((uint32_t) ((n >> 16) & 0x0F))
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434 /** CAN Remote Transmission Request */
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435 #define CAN_RFS_RTR ((uint32_t) (1 << 30))
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437 /** CAN control 11 bit or 29 bit Identifier */
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438 #define CAN_RFS_FF ((uint32_t) ((uint32_t) 1 << 31))
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441 * @brief CAN Receive Identifier Register definitions
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443 /** CAN 11 bit Identifier */
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444 #define CAN_RID_ID_11(n) ((uint32_t) ((n) & 0x7FF))
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446 /** CAN 29 bit Identifier */
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447 #define CAN_RID_ID_29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
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450 * @brief CAN Transmit Frame Information register definitions
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452 /** CAN Transmit Frame Information Register Bitmask */
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453 #define CAN_TFI_BITMASK (0xC00F00FF)
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455 /** CAN Priority */
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456 #define CAN_TFI_PRIO(n) ((uint32_t) ((n) & 0xFF))
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458 /** CAN Data Length Code */
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459 #define CAN_TFI_DLC(n) ((uint32_t) (((n) & 0xF) << 16))
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461 /** CAN Remote Frame Transmission */
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462 #define CAN_TFI_RTR ((uint32_t) (1 << 30))
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464 /** CAN control 11-bit or 29-bit Identifier */
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465 #define CAN_TFI_FF ((uint32_t) ((uint32_t) 1 << 31))
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468 * @brief CAN Transfer Identifier register definitions
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470 /** CAN 11-bit Identifier */
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471 #define CAN_TID_ID11(n) ((uint32_t) ((n) & 0x7FF))
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473 /** CAN 11-bit Identifier */
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474 #define CAN_TID_ID29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
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477 * @brief CAN Central transmit Status register definitions
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479 /** CAN Central transmit Status Register Bitmask */
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480 #define CAN_TSR_BITMASK (0x30303)
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482 /** Bit indicate CAN n (0/1) is sending a message */
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483 #define CAN_TSR_TS(n) ((uint32_t) (1 << (n + 0)))
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485 /** Bit indicate all 3 Tx buffer of CAN n (0/1) are available */
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486 #define CAN_TSR_TBS(n) ((uint32_t) (1 << (n + 8)))
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488 /** Bit indicate all requested transmissions have been completed successfully by the CAN n(0/1) */
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489 #define CAN_TSR_TCS(n) ((uint32_t) (1 << (n + 16)))
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492 * @brief CAN Central Receive Status register definitions
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494 /** CAN Central Receive Status Register Bitmask */
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495 #define CAN_RSR_BITMASK (0x30303)
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497 /** Bit indicate CAN n (0/1) is receiving a message */
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498 #define CAN_RSR_RS(n) ((uint32_t) (1 << (n + 0)))
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500 /** Bit indicate a received message is available in CAN n (0/1) */
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501 #define CAN_RSR_RBS(n) ((uint32_t) (1 << (n + 8)))
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503 /** Bit indicate a message was lost because the preceding message to CAN n(0/1) controller was not
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504 read out quickly enough*/
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505 #define CAN_RSR_DOS(n) ((uint32_t) (1 << (n + 16)))
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508 * @brief CAN Central Miscellaneous Status register definitions
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510 /** CAN Central Receive Status Register Bitmask */
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511 #define CAN_MSR_BITMASK (0x303)
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513 /** Bit indicate Tx/Rx Error Counter has reached the limit set in CAN n (0/1) */
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514 #define CAN_MSR_E(n) ((uint32_t) (1 << (n + 0)))
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516 /** Bit indicate CAN n (0/1) is currently involved in bus activities*/
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517 #define CAN_MSR_BS(n) ((uint32_t) (1 << (n + 8)))
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520 * @brief Acceptance Filter Mode register definitions
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522 /** CAN Acceptance Filter Operation mode */
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523 #define CANAF_AFMR_OPERATION ((uint32_t) (0))
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525 /** CAN Acceptance Filter Off mode */
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526 #define CANAF_AFMR_ACCOFF ((uint32_t) (1))
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528 /** CAN Acceptance File Bypass mode */
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529 #define CANAF_AFMR_ACCBP ((uint32_t) (1 << 1))
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531 /** FullCAN Mode Enhancements */
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532 #define CANAF_AFMR_EFCAN ((uint32_t) (1 << 2))
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535 * @brief Extended Frame Group Start Address register definitions
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537 /** The start address of the table of grouped Extended Identifier */
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538 #define CANAF_ENDADDR(n) ((uint32_t) (((n) & 0x3FF) << 2))
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539 #define CANAF_ENDADDR_VAL(n) ((uint32_t) ((n >> 2) & 0x3FF))
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542 * @brief LUT Error Address register definitions
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544 /** CAN Look-Up Table Error Address */
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545 #define CANAF_LUTERRAD(n) ((uint32_t) (((n) & 0x1FF) << 2))
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548 * @brief LUT Error register definitions
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550 /** CAN Look-Up Table Error */
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551 #define CANAF_LUTERR ((uint32_t) (1))
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554 * @brief Global FullCANInterrupt Enable register definitions
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556 /** Global FullCANInterrupt Enable Register Bitmask */
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557 #define CANAF_FCANIE_BITMASK (0x01)
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559 /** Global FullCANInterrupt Enable */
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560 #define CANAF_FCANIE ((uint32_t) (1))
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563 * @brief FullCAN Message Layout definitions
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566 /** FF Bit Position*/
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567 #define CANAF_FULLCAN_MSG_FF_POS (31)
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568 /** RTR Bit Position*/
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569 #define CANAF_FULLCAN_MSG_RTR_POS (30)
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570 /** Message Lost Bit Position*/
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571 #define CANAF_FULLCAN_MSG_LOST_POS (26)
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572 /** SEM Bit Position*/
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573 #define CANAF_FULLCAN_MSG_SEM_POS (24)
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575 #define CANAF_FULLCAN_MSG_SEM_BITMASK (0x03)
\r
576 /** DLC Bit Position*/
\r
577 #define CANAF_FULLCAN_MSG_DLC_POS (16)
\r
579 #define CANAF_FULLCAN_MSG_DLC_BITMASK (0x0F)
\r
580 /** SCC Bit Position*/
\r
581 #define CANAF_FULLCAN_MSG_SCC_POS (13)
\r
583 #define CANAF_FULLCAN_MSG_SCC_BITMASK (0x07)
\r
584 /** 11bit-ID Bit Position*/
\r
585 #define CANAF_FULLCAN_MSG_ID11_POS (0)
\r
586 /** 11bit-ID Bit Mask*/
\r
587 #define CANAF_FULLCAN_MSG_ID11_BITMASK (0x7FF)
\r
590 * @brief FullCAN Message Status
\r
592 /** AF is updating FullCAN Message*/
\r
593 #define CANAF_FULCAN_MSG_AF_UPDATING (0x01)
\r
594 /** AF has finished updating FullCAN Message*/
\r
595 #define CANAF_FULCAN_MSG_AF_FINISHED (0x03)
\r
596 /** CPU is in process of reading FullCAN Message*/
\r
597 #define CANAF_FULCAN_MSG_CPU_READING (0x0)
\r
600 * @brief FullCAN Interrupt and Capture register definitions
\r
602 /** FullCAN Interrupt and Capture (0-31)*/
\r
603 #define CANAF_FCAN_IC_INTPND(n) ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))
\r
606 * @brief Standard ID Entry definitions
\r
608 /** Start position of Controller Number Bits */
\r
609 #define CAN_STD_ENTRY_CTRL_NO_POS (13 )
\r
610 /** Mask of Controller Number Bits */
\r
611 #define CAN_STD_ENTRY_CTRL_NO_MASK (0x07)
\r
612 /** Start position of Disable bit */
\r
613 #define CAN_STD_ENTRY_DISABLE_POS (12 )
\r
614 /** Mask of Disable Bit */
\r
615 #define CAN_STD_ENTRY_DISABLE_MASK (0x01)
\r
616 /** Start position of Interrupt Enable bit (FullCAN entry only)*/
\r
617 #define CAN_STD_ENTRY_IE_POS (11 )
\r
618 /** Mask of Interrupt Enable bit (FullCAN entry only)*/
\r
619 #define CAN_STD_ENTRY_IE_MASK (0x01)
\r
620 /** Start position of ID bit */
\r
621 #define CAN_STD_ENTRY_ID_POS (0 )
\r
622 /** Mask of ID Bit */
\r
623 #define CAN_STD_ENTRY_ID_MASK (0x7FF)
\r
626 * @brief Extended ID Entry definitions
\r
628 /** Start position of Controller Number Bits */
\r
629 #define CAN_EXT_ENTRY_CTRL_NO_POS (29 )
\r
630 /** Mask of Controller Number Bits */
\r
631 #define CAN_EXT_ENTRY_CTRL_NO_MASK (0x07)
\r
632 /** Start position of ID bit */
\r
633 #define CAN_EXT_ENTRY_ID_POS (0 )
\r
634 /** Mask of ID Bit */
\r
635 #define CAN_EXT_ENTRY_ID_MASK (0x1FFFFFFF)
\r
638 * @brief CAN Message Type definitions
\r
641 /** Remote Message */
\r
642 #define CAN_REMOTE_MSG ((uint32_t) (1 << 0))
\r
644 /** Message use Extend ID*/
\r
645 #define CAN_EXTEND_ID_USAGE ((uint32_t) (1 << 30))
\r
647 /** The maximum data length in CAN Message */
\r
648 #define CAN_MSG_MAX_DATA_LEN (8)
\r
651 * @brief CAN Buffer ID definition
\r
653 typedef enum IP_CAN_BUFFER_ID {
\r
654 CAN_BUFFER_1 = 0, /*!< Buffer 1 */
\r
655 CAN_BUFFER_2, /*!< Buffer 2 */
\r
656 CAN_BUFFER_3, /*!< Buffer 3 */
\r
657 CAN_BUFFER_LAST, /*!< Last Buffer */
\r
658 } IP_CAN_BUFFER_ID_T;
\r
661 * @brief CAN Message Object Structure
\r
663 typedef struct /*!< Message structure */
\r
665 uint32_t ID; /*!< Message Identifier. If 30th-bit is set, this is 29-bit ID, othewise 11-bit ID */
\r
666 uint32_t Type; /*!< Message Type. which can include: - CAN_REMOTE_MSG type*/
\r
667 uint32_t DLC; /*!< Message Data Length: 0~8 */
\r
668 uint8_t Data[CAN_MSG_MAX_DATA_LEN];/*!< Message Data */
\r
672 * @brief CAN Bus Timing Structure
\r
674 typedef struct /*!< Bus Timing structure */
\r
676 uint16_t BRP; /*!< Baud Rate Prescaler */
\r
677 uint8_t SJW; /*!< SJW value*/
\r
678 uint8_t TESG1; /*!< TESG1 value */
\r
679 uint8_t TESG2; /*!< TESG2 value */
\r
680 uint8_t SAM; /*!<0: The bus is sampled once, 1: sampled 3 times */
\r
681 } IP_CAN_BUS_TIMING_T;
\r
684 * @brief Standard ID Entry structure
\r
687 uint8_t CtrlNo; /*!<Controller Number: 0 for CAN1 and 1 for CAN2*/
\r
688 uint8_t Disable; /*!< 0(ENABLE)/1(DISABLE): Response On/Off dynamically*/
\r
689 uint16_t ID_11; /*!< Standard ID, should be 11-bit value */
\r
690 } IP_CAN_STD_ID_Entry_T;
\r
693 * @brief Standard ID Range structure
\r
696 IP_CAN_STD_ID_Entry_T LowerID; /*!< Lower ID Bound, should be in 11-bit value*/
\r
697 IP_CAN_STD_ID_Entry_T UpperID; /*!< Upper ID Bound, should be in 11-bit value*/
\r
698 } IP_CAN_STD_ID_RANGE_Entry_T;
\r
701 * @brief Extended ID Entry structure
\r
704 uint8_t CtrlNo; /*!<Controller Number: 0 for CAN1 and 1 for CAN2*/
\r
705 uint32_t ID_29; /*!< Extend ID, shoud be 29-bit value */
\r
706 } IP_CAN_EXT_ID_Entry_T;
\r
709 * @brief Extended ID Range structure
\r
712 IP_CAN_EXT_ID_Entry_T LowerID; /*!< Lower ID Bound, should be in 29-bit value*/
\r
713 IP_CAN_EXT_ID_Entry_T UpperID; /*!< Upper ID Bound, should be in 29-bit value*/
\r
714 } IP_CAN_EXT_ID_RANGE_Entry_T;
\r
717 * @brief Acceptance Filter Section Table structure
\r
720 IP_CAN_STD_ID_Entry_T *FullCANSec; /*!< The pointer to fullCAN section */
\r
721 uint16_t FullCANEntryNum; /*!< FullCAN Entry Number */
\r
722 IP_CAN_STD_ID_Entry_T *SffSec; /*!< The pointer to individual Standard ID Section */
\r
723 uint16_t SffEntryNum; /*!< Standard ID Entry Number */
\r
724 IP_CAN_STD_ID_RANGE_Entry_T *SffGrpSec; /*!< The pointer to Group Standard ID Section */
\r
725 uint16_t SffGrpEntryNum; /*!< Group Standard ID Entry Number */
\r
726 IP_CAN_EXT_ID_Entry_T *EffSec; /*!< The pointer to Extended ID Section */
\r
727 uint16_t EffEntryNum; /*!< Extended ID Entry Number */
\r
728 IP_CAN_EXT_ID_RANGE_Entry_T *EffGrpSec; /*!< The pointer to Group Extended ID Section */
\r
729 uint16_t EffGrpEntryNum; /*!< Group Extended ID Entry Number */
\r
733 * @brief De-initialize the CAN peripheral
\r
734 * @param pCAN : Pointer to CAN peripheral block
\r
737 STATIC INLINE void IP_CAN_DeInit(IP_CAN_001_T *pCAN)
\r
741 * @brief Get current mode register settings of the CAN controller
\r
742 * @param pCAN : Pointer to CAN peripheral block
\r
743 * @return Current Mode register value of the CAN Controller (Bit values of CAN_MOD_*)
\r
745 STATIC INLINE uint32_t IP_CAN_GetMode(IP_CAN_001_T *pCAN)
\r
747 return pCAN->MOD & CAN_MOD_BITMASK;
\r
751 * @brief Set the CAN command request
\r
752 * @param pCAN : Pointer to CAN peripheral block
\r
753 * @param command : Command request (Or'ed bit values of CAN_CMR_*).
\r
756 STATIC INLINE void IP_CAN_SetCmd(IP_CAN_001_T *pCAN, uint32_t command)
\r
758 pCAN->CMR = command;
\r
762 * @brief Set Error Warning Limit for the CAN Controller
\r
763 * @param pCAN : Pointer to CAN peripheral block
\r
764 * @param ewl : expected limit
\r
767 STATIC INLINE void IP_CAN_SetEWL(IP_CAN_001_T *pCAN, uint32_t ewl)
\r
769 pCAN->EWL = ewl & CAN_EWL_BITMASK;
\r
773 * @brief Get Error Warning Limit of the CAN Controller
\r
774 * @param pCAN : Pointer to CAN peripheral block
\r
775 * @return Error warning limit value
\r
777 STATIC INLINE uint8_t IP_CAN_GetEWL(IP_CAN_001_T *pCAN)
\r
779 return CAN_EWL_VAL(pCAN->EWL);
\r
783 * @brief Get global status register contents of the CAN Controller
\r
784 * @param pCAN : Pointer to CAN peripheral block
\r
785 * @return Gloabl Status register contents (Or'ed bit values of CAN_GSR_*)
\r
787 STATIC INLINE uint32_t IP_CAN_GetGlobalStatus(IP_CAN_001_T *pCAN)
\r
793 * @brief Get the status of the CAN Controller
\r
794 * @param pCAN : Pointer to CAN peripheral block
\r
795 * @return Status (Or'ed bit values of CAN_SR_*(n) with n = CAN_BUFFER_1/2/3).
\r
797 STATIC INLINE uint32_t IP_CAN_GetStatus(IP_CAN_001_T *pCAN)
\r
803 * @brief Enable the given interrupt of the CAN Controller
\r
804 * @param pCAN : Pointer to CAN peripheral block
\r
805 * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).
\r
808 STATIC INLINE void IP_CAN_IntEnable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
\r
809 pCAN->IER |= IntMask;
\r
813 * @brief Disable the given interrupt of the CAN Controller
\r
814 * @param pCAN : Pointer to CAN peripheral block
\r
815 * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).
\r
818 STATIC INLINE void IP_CAN_IntDisable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
\r
819 pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;
\r
823 * @brief Get the interrupt status of the CAN Controller
\r
824 * @param pCAN : Pointer to CAN peripheral block
\r
825 * @return Interrupt status (Or'ed bit values of CAN_ICR_* )
\r
827 STATIC INLINE uint32_t IP_CAN_GetIntStatus(IP_CAN_001_T *pCAN)
\r
833 * @brief Set CAN AF Mode
\r
834 * @param pCanAF : Pointer to CAN AF Register block
\r
835 * @param AFMode : Mode selected (Bit values of CANAF_AFMR_*)
\r
838 STATIC INLINE void IP_CAN_AF_SetMode(IP_CAN_001_AF_T *pCanAF, uint32_t AFMode)
\r
840 pCanAF->AFMR = AFMode;
\r
844 * @brief Get CAN AF Mode
\r
845 * @param pCanAF : Pointer to CAN AF Register block
\r
848 STATIC INLINE uint32_t IP_CAN_AF_GetMode(IP_CAN_001_AF_T *pCanAF)
\r
850 return pCanAF->AFMR;
\r
854 * @brief Initialize the CAN peripheral
\r
855 * @param pCAN : Pointer to CAN peripheral block
\r
858 void IP_CAN_Init(IP_CAN_001_T *pCAN);
\r
861 * @brief Enable/Disable the specified mode in CAN controller
\r
862 * @param pCAN : Pointer to CAN peripheral block
\r
863 * @param Mode : Mode selected (Bit values of CAN_MOD_*)
\r
864 * @param NewState : ENABLE: Enable, DISABLE: Disable
\r
867 void IP_CAN_SetMode(IP_CAN_001_T *pCAN, uint32_t Mode, FunctionalState NewState);
\r
870 * @brief Set Bus Timing for the CAN Controller
\r
871 * @param pCAN : Pointer to CAN peripheral block
\r
872 * @param pBusTiming : Bus Timing information
\r
875 void IP_CAN_SetBusTiming(IP_CAN_001_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming);
\r
878 * @brief Get message received by the CAN Controller
\r
879 * @param pCAN : Pointer to CAN peripheral block
\r
880 * @param pMsg : Pointer to the buffer to store the received message
\r
881 * @return SUCCESS (message information saved) or ERROR (no message received)
\r
883 Status IP_CAN_Receive(IP_CAN_001_T *pCAN, IP_CAN_MSG_T *pMsg);
\r
886 * @brief Request the CAN Controller to send message
\r
887 * @param pCAN : Pointer to CAN peripheral block
\r
888 * @param TxBufID : ID of buffer which will be used for transmit
\r
889 * @param pMsg : Pointer to the buffer of message which will be sent
\r
890 * @return SUCCESS (message information saved) or ERROR (no message received)
\r
892 Status IP_CAN_Send(IP_CAN_001_T *pCAN, IP_CAN_BUFFER_ID_T TxBufID, IP_CAN_MSG_T *pMsg);
\r
895 * @brief Initialize CAN Acceptance Filter
\r
896 * @param pCanAF : Pointer to CAN AF Register block
\r
897 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
900 void IP_CAN_AF_Init(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
\r
903 * @brief Enable/Disable the interrupts of the CAN Controller in FullCAN Mode
\r
904 * @param pCanAF : Pointer to CAN AF Register block
\r
905 * @param NewState : ENABLE to enable/DISABLE to Disable
\r
908 void IP_CAN_FullCANIntConfig(IP_CAN_001_AF_T *pCanAF, FunctionalState NewState);
\r
911 * @brief Get FullCAN interrupt status of the object
\r
912 * @param pCanAF : Pointer to CAN AF Register block
\r
913 * @param ObjID : Object ID
\r
914 * @return Interrupt Status
\r
916 uint32_t IP_CAN_GetFullCANIntStatus(IP_CAN_001_AF_T *pCanAF, uint8_t ObjID);
\r
919 * @brief Get FULLCANmessage automatically received by the AF
\r
920 * @param pCanAF : Pointer to CAN AF Register block
\r
921 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
922 * @param ObjID : Object ID
\r
923 * @param pMsg : Pointer to the buffer storing the received message
\r
924 * @param pSCC : Pointer to the buffer storing the controller ID of the received message
\r
925 * @return SUCCESS (message information saved) or ERROR (no message received)
\r
927 Status IP_CAN_FullCANReceive(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
928 uint8_t ObjID, IP_CAN_MSG_T *pMsg, uint8_t *pSCC);
\r
931 * @brief Clear CAN AF LUT
\r
932 * @param pCanAF : Pointer to CAN AF Register block
\r
933 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
936 void IP_CAN_ClearAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
\r
939 * @brief Set CAN AF LUT
\r
940 * @param pCanAF : Pointer to CAN AF Register block
\r
941 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
942 * @param pAFSections : Pointer to buffer storing AF Section Data
\r
943 * @return SUCCESS/ERROR
\r
945 Status IP_CAN_SetAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam, IP_CAN_AF_LUT_T *pAFSections);
\r
948 * @brief Insert a FullCAN Entry into the current LUT
\r
949 * @param pCanAF : Pointer to CAN AF Register block
\r
950 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
951 * @param pEntry : Pointer to the entry which will be inserted
\r
952 * @return SUCCESS/ERROR
\r
954 Status IP_CAN_InsertFullCANEntry(IP_CAN_001_AF_T *pCanAF,
\r
955 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
956 IP_CAN_STD_ID_Entry_T *pEntry);
\r
959 * @brief Insert an individual Standard Entry into the current LUT
\r
960 * @param pCanAF : Pointer to CAN AF Register block
\r
961 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
962 * @param pEntry : Pointer to the entry which will be inserted
\r
963 * @return SUCCESS/ERROR
\r
965 Status IP_CAN_InsertIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
966 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
967 IP_CAN_STD_ID_Entry_T *pEntry);
\r
970 * @brief Insert an Group Standard Entry into the current LUT
\r
971 * @param pCanAF : Pointer to CAN AF Register block
\r
972 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
973 * @param pEntry : Pointer to the entry which will be inserted
\r
974 * @return SUCCESS/ERROR
\r
976 Status IP_CAN_InsertGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
977 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
978 IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
\r
981 * @brief Insert an individual Extended Entry into the current LUT
\r
982 * @param pCanAF : Pointer to CAN AF Register block
\r
983 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
984 * @param pEntry : Pointer to the entry which will be inserted
\r
985 * @return SUCCESS/ERROR
\r
987 Status IP_CAN_InsertIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
988 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
989 IP_CAN_EXT_ID_Entry_T *pEntry);
\r
992 * @brief Insert an Group Extended Entry into the current LUT
\r
993 * @param pCanAF : Pointer to CAN AF Register block
\r
994 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
995 * @param pEntry : Pointer to the entry which will be inserted
\r
996 * @return SUCCESS/ERROR
\r
998 Status IP_CAN_InsertGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
999 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1000 IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
\r
1003 * @brief Remove a FullCAN Entry from the current LUT
\r
1004 * @param pCanAF : Pointer to CAN AF Register block
\r
1005 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1006 * @param Position : Position of the entry in the Full CAN section (started from 0)
\r
1007 * @return SUCCESS/ERROR
\r
1009 Status IP_CAN_RemoveFullCANEntry(IP_CAN_001_AF_T *pCanAF,
\r
1010 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1011 int16_t Position);
\r
1014 * @brief Remove an individual Standard Entry from the current LUT
\r
1015 * @param pCanAF : Pointer to CAN AF Register block
\r
1016 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1017 * @param Position : Position of the entry in the Individual STD section (started from 0)
\r
1018 * @return SUCCESS/ERROR
\r
1020 Status IP_CAN_RemoveIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
1021 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1022 int16_t Position);
\r
1025 * @brief Remove an Group Standard Entry from the current LUT
\r
1026 * @param pCanAF : Pointer to CAN AF Register block
\r
1027 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1028 * @param Position : Position of the entry in the Group STD section (started from 0)
\r
1029 * @return SUCCESS/ERROR
\r
1031 Status IP_CAN_RemoveGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
1032 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1033 int16_t Position);
\r
1036 * @brief Remove an individual Extended Entry from the current LUT
\r
1037 * @param pCanAF : Pointer to CAN AF Register block
\r
1038 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1039 * @param Position : Position of the entry in the Individual EXT section (started from 0)
\r
1040 * @return SUCCESS/ERROR
\r
1042 Status IP_CAN_RemoveIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
1043 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1044 int16_t Position);
\r
1047 * @brief Remove an Group Extended Entry from the current LUT
\r
1048 * @param pCanAF : Pointer to CAN AF Register block
\r
1049 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1050 * @param Position : Position of the entry in the Group EXT section (started from 0)
\r
1051 * @return SUCCESS/ERROR
\r
1053 Status IP_CAN_RemoveGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
1054 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1055 int16_t Position);
\r
1058 * @brief Get the number of entries of the given section
\r
1059 * @param pCanAF : Pointer to CAN AF Register block
\r
1060 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1061 * @param SectionID : Section ID
\r
1062 * @return Number of entries
\r
1064 uint16_t IP_CAN_GetEntriesNum(IP_CAN_001_AF_T *pCanAF,
\r
1065 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1066 IP_CAN_AF_RAM_SECTION_T SectionID);
\r
1069 * @brief Read a FullCAN Entry into from current LUT
\r
1070 * @param pCanAF : Pointer to CAN AF Register block
\r
1071 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1072 * @param Position : Position of the entry in the given section (started from 0)
\r
1073 * @param pEntry : Pointer to the entry which will be inserted
\r
1074 * @return SUCCESS/ERROR
\r
1076 Status IP_CAN_ReadFullCANEntry(IP_CAN_001_AF_T *pCanAF,
\r
1077 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1078 uint16_t Position,
\r
1079 IP_CAN_STD_ID_Entry_T *pEntry);
\r
1082 * @brief Read an individual Standard Entry from the current LUT
\r
1083 * @param pCanAF : Pointer to CAN AF Register block
\r
1084 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1085 * @param Position : Position of the entry in the given section (started from 0)
\r
1086 * @param pEntry : Pointer to the entry which will be inserted
\r
1087 * @return SUCCESS/ERROR
\r
1089 Status IP_CAN_ReadIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
1090 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1091 uint16_t Position,
\r
1092 IP_CAN_STD_ID_Entry_T *pEntry);
\r
1095 * @brief Read an Group Standard Entry from the current LUT
\r
1096 * @param pCanAF : Pointer to CAN AF Register block
\r
1097 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1098 * @param Position : Position of the entry in the given section (started from 0)
\r
1099 * @param pEntry : Pointer to the entry which will be inserted
\r
1100 * @return SUCCESS/ERROR
\r
1102 Status IP_CAN_ReadGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
\r
1103 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1104 uint16_t Position,
\r
1105 IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
\r
1108 * @brief Read an individual Extended Entry from the current LUT
\r
1109 * @param pCanAF : Pointer to CAN AF Register block
\r
1110 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1111 * @param Position : Position of the entry in the given section (started from 0)
\r
1112 * @param pEntry : Pointer to the entry which will be inserted
\r
1113 * @return SUCCESS/ERROR
\r
1115 Status IP_CAN_ReadIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
1116 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1117 uint16_t Position,
\r
1118 IP_CAN_EXT_ID_Entry_T *pEntry);
\r
1121 * @brief Read an Group Extended Entry from the current LUT
\r
1122 * @param pCanAF : Pointer to CAN AF Register block
\r
1123 * @param pCanAFRam : Pointer to CAN AF RAM Register block
\r
1124 * @param Position : Position of the entry in the given section (started from 0)
\r
1125 * @param pEntry : Pointer to the entry which will be inserted
\r
1126 * @return SUCCESS/ERROR
\r
1128 Status IP_CAN_ReadGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
\r
1129 IP_CAN_001_AF_RAM_T *pCanAFRam,
\r
1130 uint16_t Position,
\r
1131 IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
\r
1137 #ifdef __cplusplus
\r
1141 #endif /* __CAN_001_H_ */
\r
projects / freertos / blob