1 /***************************************************************************//**
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3 * @brief Clock management unit (CMU) API
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5 *******************************************************************************
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7 * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
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8 *******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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21 * obligation to support this Software. Silicon Labs is providing the
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22 * Software "AS IS", with no express or implied warranties of any kind,
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23 * including, but not limited to, any implied warranties of merchantability
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24 * or fitness for any particular purpose or warranties against infringement
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25 * of any proprietary rights of a third party.
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27 * Silicon Labs will not be liable for any consequential, incidental, or
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28 * special damages, or any other relief, or for any claim by any third party,
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29 * arising from your use of this Software.
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31 ******************************************************************************/
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34 #ifndef __SILICON_LABS_EM_CMU_H_
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35 #define __SILICON_LABS_EM_CMU_H_
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37 #include "em_device.h"
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38 #if defined( CMU_PRESENT )
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40 #include <stdbool.h>
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41 #include "em_bitband.h"
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47 /***************************************************************************//**
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48 * @addtogroup EM_Library
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50 ******************************************************************************/
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52 /***************************************************************************//**
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55 ******************************************************************************/
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57 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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59 /* Select register ids, for internal use */
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60 #define CMU_NOSEL_REG 0
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61 #define CMU_HFCLKSEL_REG 1
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62 #define CMU_LFACLKSEL_REG 2
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63 #define CMU_LFBCLKSEL_REG 3
\r
64 #define CMU_DBGCLKSEL_REG 4
\r
65 #if defined( _CMU_CMD_USBCCLKSEL_MASK )
\r
66 #define CMU_USBCCLKSEL_REG 5
\r
68 #if defined( _CMU_LFCLKSEL_LFC_MASK )
\r
69 #define CMU_LFCCLKSEL_REG 6
\r
72 #define CMU_SEL_REG_POS 0
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73 #define CMU_SEL_REG_MASK 0xf
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75 /* Divisor register ids, for internal use */
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76 #define CMU_NODIV_REG 0
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77 #define CMU_HFPERCLKDIV_REG 1
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78 #define CMU_HFCORECLKDIV_REG 2
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79 #define CMU_LFAPRESC0_REG 3
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80 #define CMU_LFBPRESC0_REG 4
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81 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
\r
82 #define CMU_HFCLKDIV_REG 5
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84 #define CMU_DIV_REG_POS 4
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85 #define CMU_DIV_REG_MASK 0xf
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87 /* Enable register ids, for internal use */
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88 #define CMU_NO_EN_REG 0
\r
89 #define CMU_HFPERCLKDIV_EN_REG 1
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90 #define CMU_HFPERCLKEN0_EN_REG 2
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91 #define CMU_HFCORECLKEN0_EN_REG 3
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92 #define CMU_LFACLKEN0_EN_REG 4
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93 #define CMU_LFBCLKEN0_EN_REG 5
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94 #define CMU_PCNT_EN_REG 6
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95 #if defined( _CMU_LFCCLKEN0_MASK )
\r
96 #define CMU_LFCCLKEN0_EN_REG 7
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99 #define CMU_EN_REG_POS 8
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100 #define CMU_EN_REG_MASK 0xf
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102 /* Enable register bit position, for internal use */
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103 #define CMU_EN_BIT_POS 12
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104 #define CMU_EN_BIT_MASK 0x1f
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106 /* Clock branch bitfield position, for internal use */
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107 #define CMU_HF_CLK_BRANCH 0
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108 #define CMU_HFPER_CLK_BRANCH 1
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109 #define CMU_HFCORE_CLK_BRANCH 2
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110 #define CMU_LFA_CLK_BRANCH 3
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111 #define CMU_RTC_CLK_BRANCH 4
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112 #define CMU_LETIMER_CLK_BRANCH 5
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113 #define CMU_LCDPRE_CLK_BRANCH 6
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114 #define CMU_LCD_CLK_BRANCH 7
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115 #define CMU_LESENSE_CLK_BRANCH 8
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116 #define CMU_LFB_CLK_BRANCH 9
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117 #define CMU_LEUART0_CLK_BRANCH 10
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118 #define CMU_LEUART1_CLK_BRANCH 11
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119 #define CMU_DBG_CLK_BRANCH 12
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120 #define CMU_AUX_CLK_BRANCH 13
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121 #define CMU_USBC_CLK_BRANCH 14
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122 #define CMU_LFC_CLK_BRANCH 15
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123 #define CMU_USBLE_CLK_BRANCH 16
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125 #define CMU_CLK_BRANCH_POS 17
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126 #define CMU_CLK_BRANCH_MASK 0x1f
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130 /*******************************************************************************
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131 ******************************** ENUMS ************************************
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132 ******************************************************************************/
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134 /** Clock divisors. These values are valid for prescalers. */
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135 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
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136 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
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137 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
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138 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
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139 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
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140 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
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141 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
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142 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
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143 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
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144 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
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145 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
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146 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
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147 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
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148 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
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149 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
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150 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
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152 /** Clock divider configuration */
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153 typedef uint32_t CMU_ClkDiv_TypeDef;
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155 /** High frequency RC bands. */
\r
158 /** 1MHz RC band. */
\r
159 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
\r
160 /** 7MHz RC band. */
\r
161 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
\r
162 /** 11MHz RC band. */
\r
163 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
\r
164 /** 14MHz RC band. */
\r
165 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
\r
166 /** 21MHz RC band. */
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167 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
\r
168 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
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169 /** 28MHz RC band. */
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170 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
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172 } CMU_HFRCOBand_TypeDef;
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175 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
\r
176 /** AUX High frequency RC bands. */
\r
179 /** 1MHz RC band. */
\r
180 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
\r
181 /** 7MHz RC band. */
\r
182 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
\r
183 /** 11MHz RC band. */
\r
184 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
\r
185 /** 14MHz RC band. */
\r
186 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
\r
187 /** 21MHz RC band. */
\r
188 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
\r
189 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
\r
190 /** 28MHz RC band. */
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191 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ
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193 } CMU_AUXHFRCOBand_TypeDef;
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196 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
\r
197 /** USB High frequency RC bands. */
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200 /** 24MHz RC band. */
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201 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
\r
202 /** 48MHz RC band. */
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203 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
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204 } CMU_USHFRCOBand_TypeDef;
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208 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
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211 /*******************/
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212 /* HF clock branch */
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213 /*******************/
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215 /** High frequency clock */
\r
216 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
\r
217 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) |
\r
218 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
\r
219 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
220 (0 << CMU_EN_BIT_POS) |
\r
221 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
223 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
224 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
\r
225 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
226 (0 << CMU_EN_BIT_POS) |
\r
227 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
231 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
232 (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) |
\r
233 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
234 (0 << CMU_EN_BIT_POS) |
\r
235 (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
238 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
239 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
240 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
241 (0 << CMU_EN_BIT_POS) |
\r
242 (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
244 /**********************************/
\r
245 /* HF peripheral clock sub-branch */
\r
246 /**********************************/
\r
248 /** High frequency peripheral clock */
\r
249 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
\r
250 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
251 (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
\r
252 (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) |
\r
253 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
255 #if defined(_CMU_HFPERCLKEN0_USART0_MASK)
\r
256 /** Universal sync/async receiver/transmitter 0 clock. */
\r
257 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
258 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
259 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
260 (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) |
\r
261 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
264 #if defined(_CMU_HFPERCLKEN0_USARTRF0_MASK)
\r
265 /** Universal sync/async receiver/transmitter 0 clock. */
\r
266 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
267 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
268 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
269 (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) |
\r
270 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
273 #if defined(_CMU_HFPERCLKEN0_USART1_MASK)
\r
274 /** Universal sync/async receiver/transmitter 1 clock. */
\r
275 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
276 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
277 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
278 (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) |
\r
279 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
282 #if defined(_CMU_HFPERCLKEN0_USART2_MASK)
\r
283 /** Universal sync/async receiver/transmitter 2 clock. */
\r
284 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
285 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
286 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
287 (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) |
\r
288 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
291 #if defined(_CMU_HFPERCLKEN0_UART0_MASK)
\r
292 /** Universal async receiver/transmitter 0 clock. */
\r
293 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
294 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
295 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
296 (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) |
\r
297 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
300 #if defined(_CMU_HFPERCLKEN0_UART1_MASK)
\r
301 /** Universal async receiver/transmitter 1 clock. */
\r
302 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
303 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
304 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
305 (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) |
\r
306 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
309 #if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)
\r
310 /** Timer 0 clock. */
\r
311 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
312 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
313 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
314 (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) |
\r
315 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
318 #if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)
\r
319 /** Timer 1 clock. */
\r
320 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
321 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
322 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
323 (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) |
\r
324 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
327 #if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)
\r
328 /** Timer 2 clock. */
\r
329 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
330 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
331 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
332 (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) |
\r
333 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
336 #if defined(_CMU_HFPERCLKEN0_TIMER3_MASK)
\r
337 /** Timer 3 clock. */
\r
338 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
339 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
340 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
341 (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) |
\r
342 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
345 #if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)
\r
346 /** Analog comparator 0 clock. */
\r
347 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
348 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
349 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
350 (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) |
\r
351 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
354 #if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)
\r
355 /** Analog comparator 1 clock. */
\r
356 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
357 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
358 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
359 (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) |
\r
360 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
363 #if defined(_CMU_HFPERCLKEN0_PRS_MASK)
\r
364 /** Peripheral reflex system clock. */
\r
365 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
366 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
367 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
368 (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) |
\r
369 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
372 #if defined(_CMU_HFPERCLKEN0_DAC0_MASK)
\r
373 /** Digital to analog converter 0 clock. */
\r
374 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
375 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
376 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
377 (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) |
\r
378 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
381 #if defined(_CMU_HFPERCLKEN0_IDAC0_MASK)
\r
382 /** Digital to analog converter 0 clock. */
\r
383 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
384 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
385 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
386 (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) |
\r
387 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
390 #if defined(GPIO_PRESENT)
\r
391 /** General purpose input/output clock. */
\r
392 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
393 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
394 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
395 (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) |
\r
396 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
399 #if defined(VCMP_PRESENT)
\r
400 /** Voltage comparator clock. */
\r
401 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
402 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
403 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
404 (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) |
\r
405 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
408 #if defined(_CMU_HFPERCLKEN0_ADC0_MASK)
\r
409 /** Analog to digital converter 0 clock. */
\r
410 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
411 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
412 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
413 (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) |
\r
414 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
417 #if defined(_CMU_HFPERCLKEN0_I2C0_MASK)
\r
418 /** I2C 0 clock. */
\r
419 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
420 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
421 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
422 (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) |
\r
423 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
426 #if defined(_CMU_HFPERCLKEN0_I2C1_MASK)
\r
427 /** I2C 1 clock. */
\r
428 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
429 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
430 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
431 (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) |
\r
432 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
435 /**********************/
\r
436 /* HF core sub-branch */
\r
437 /**********************/
\r
440 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
\r
441 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
442 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
443 (0 << CMU_EN_BIT_POS) |
\r
444 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
446 #if defined(AES_PRESENT)
\r
447 /** Advanced encryption standard accelerator clock. */
\r
448 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
449 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
450 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
451 (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) |
\r
452 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
455 #if defined(DMA_PRESENT)
\r
456 /** Direct memory access controller clock. */
\r
457 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
458 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
459 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
460 (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) |
\r
461 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
463 /** Low energy clocking module clock. */
\r
464 cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
465 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
466 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
467 (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) |
\r
468 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
470 #if defined(EBI_PRESENT)
\r
471 /** External bus interface clock. */
\r
472 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
473 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
474 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
475 (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) |
\r
476 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
479 #if defined(USB_PRESENT)
\r
480 /** USB Core clock. */
\r
481 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
482 (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
\r
483 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
484 (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
\r
485 (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
489 #if defined(USB_PRESENT)
\r
491 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
492 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
493 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
494 (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |
\r
495 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
502 /** Low frequency A clock */
\r
503 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
504 (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
\r
505 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
506 (0 << CMU_EN_BIT_POS) |
\r
507 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
509 #if defined(RTC_PRESENT)
\r
510 /** Real time counter clock. */
\r
511 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
\r
512 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
513 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
514 (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) |
\r
515 (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
518 #if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
\r
519 /** Low energy timer 0 clock. */
\r
520 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
\r
521 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
522 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
523 (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) |
\r
524 (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
527 #if defined(_CMU_LFACLKEN0_LCD_MASK)
\r
528 /** Liquid crystal display, pre FDIV clock. */
\r
529 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
\r
530 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
531 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
532 (0 << CMU_EN_BIT_POS) |
\r
533 (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
535 /** Liquid crystal display clock. Please notice that FDIV prescaler
\r
536 * must be set by special API. */
\r
537 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
538 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
539 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
540 (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) |
\r
541 (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
544 #if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
\r
545 /** Pulse counter 0 clock. */
\r
546 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
547 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
548 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
\r
549 (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) |
\r
550 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
553 #if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
\r
554 /** Pulse counter 1 clock. */
\r
555 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
556 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
557 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
\r
558 (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) |
\r
559 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
562 #if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
\r
563 /** Pulse counter 2 clock. */
\r
564 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
565 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
566 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
\r
567 (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) |
\r
568 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
570 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
\r
571 /** LESENSE clock. */
\r
572 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
\r
573 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
574 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
575 (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) |
\r
576 (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
583 /** Low frequency B clock */
\r
584 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
585 (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
\r
586 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
587 (0 << CMU_EN_BIT_POS) |
\r
588 (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
590 #if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
\r
591 /** Low energy universal asynchronous receiver/transmitter 0 clock. */
\r
592 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
\r
593 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
594 (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
595 (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) |
\r
596 (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
599 #if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
\r
600 /** Low energy universal asynchronous receiver/transmitter 1 clock. */
\r
601 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
\r
602 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
\r
603 (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
604 (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) |
\r
605 (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
612 /** Low frequency C clock */
\r
613 #if defined( _CMU_LFCLKSEL_LFC_MASK )
\r
614 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
615 (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
\r
616 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
\r
617 (0 << CMU_EN_BIT_POS) |
\r
618 (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
621 #if defined(_CMU_LFCCLKEN0_USBLE_MASK)
\r
622 /** USB LE clock. */
\r
623 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
\r
624 (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
\r
625 (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) |
\r
626 (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) |
\r
627 (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
\r
630 } CMU_Clock_TypeDef;
\r
633 /** Oscillator types. */
\r
636 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
\r
637 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
\r
638 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
\r
639 cmuOsc_HFRCO, /**< High frequency RC oscillator. */
\r
640 cmuOsc_AUXHFRCO, /**< Auxiliary high frequency RC oscillator. */
\r
641 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
\r
642 cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */
\r
644 #if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
\r
645 cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */
\r
650 /** Selectable clock sources. */
\r
653 cmuSelect_Error, /**< Usage error. */
\r
654 cmuSelect_Disabled, /**< Clock selector disabled. */
\r
655 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
\r
656 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
\r
657 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
\r
658 cmuSelect_HFRCO, /**< High frequency RC oscillator. */
\r
659 cmuSelect_CORELEDIV2, /**< Core low energy clock divided by 2. */
\r
660 cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */
\r
661 cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko) */
\r
662 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
\r
663 cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */
\r
665 #if defined( _CMU_CMD_HFCLKSEL_USHFRCODIV2 )
\r
666 cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */
\r
668 #if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
\r
669 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
\r
671 } CMU_Select_TypeDef;
\r
674 /*******************************************************************************
\r
675 ***************************** PROTOTYPES **********************************
\r
676 ******************************************************************************/
\r
678 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
\r
679 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
\r
680 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
\r
681 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
\r
682 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
\r
683 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
\r
685 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
\r
686 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
\r
688 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
\r
689 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
\r
690 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
\r
693 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
\r
694 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
\r
695 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
\r
698 void CMU_HFRCOStartupDelaySet(uint32_t delay);
\r
699 uint32_t CMU_HFRCOStartupDelayGet(void);
\r
701 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
\r
702 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
\r
703 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
\r
705 bool CMU_PCNTClockExternalGet(unsigned int inst);
\r
706 void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
\r
708 uint32_t CMU_LCDClkFDIVGet(void);
\r
709 void CMU_LCDClkFDIVSet(uint32_t div);
\r
711 void CMU_FreezeEnable(bool enable);
\r
712 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
\r
714 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
\r
715 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
\r
716 CMU_Osc_TypeDef upSel);
\r
719 /***************************************************************************//**
\r
721 * Clear one or more pending CMU interrupts.
\r
724 * CMU interrupt sources to clear.
\r
725 ******************************************************************************/
\r
726 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
\r
732 /***************************************************************************//**
\r
734 * Disable one or more CMU interrupts.
\r
737 * CMU interrupt sources to disable.
\r
738 ******************************************************************************/
\r
739 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
\r
741 CMU->IEN &= ~flags;
\r
745 /***************************************************************************//**
\r
747 * Enable one or more CMU interrupts.
\r
750 * Depending on the use, a pending interrupt may already be set prior to
\r
751 * enabling the interrupt. Consider using CMU_IntClear() prior to enabling
\r
752 * if such a pending interrupt should be ignored.
\r
755 * CMU interrupt sources to enable.
\r
756 ******************************************************************************/
\r
757 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
\r
763 /***************************************************************************//**
\r
765 * Get pending CMU interrupts.
\r
768 * CMU interrupt sources pending.
\r
769 ******************************************************************************/
\r
770 __STATIC_INLINE uint32_t CMU_IntGet(void)
\r
776 /***************************************************************************//**
\r
778 * Get enabled and pending CMU interrupt flags.
\r
781 * Useful for handling more interrupt sources in the same interrupt handler.
\r
784 * The event bits are not cleared by the use of this function.
\r
787 * Pending and enabled CMU interrupt sources.
\r
788 * The return value is the bitwise AND combination of
\r
789 * - the OR combination of enabled interrupt sources in CMU_IEN_nnn
\r
790 * register (CMU_IEN_nnn) and
\r
791 * - the OR combination of valid interrupt flags of the CMU module
\r
793 ******************************************************************************/
\r
794 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
\r
799 /* Store LESENSE->IEN in temporary variable in order to define explicit order
\r
800 * of volatile accesses. */
\r
803 /* Bitwise AND of pending and enabled interrupts */
\r
804 return CMU->IF & tmp;
\r
808 /**************************************************************************//**
\r
810 * Set one or more pending CMU interrupts from SW.
\r
813 * CMU interrupt sources to set to pending.
\r
814 *****************************************************************************/
\r
815 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
\r
821 /***************************************************************************//**
\r
823 * Lock the CMU in order to protect some of its registers against unintended
\r
827 * Please refer to the reference manual for CMU registers that will be
\r
831 * If locking the CMU registers, they must be unlocked prior to using any
\r
832 * CMU API functions modifying CMU registers protected by the lock.
\r
833 ******************************************************************************/
\r
834 __STATIC_INLINE void CMU_Lock(void)
\r
836 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
\r
840 /***************************************************************************//**
\r
842 * Unlock the CMU so that writing to locked registers again is possible.
\r
843 ******************************************************************************/
\r
844 __STATIC_INLINE void CMU_Unlock(void)
\r
846 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
\r
850 /***************************************************************************//**
\r
852 * Get calibration count register
\r
854 * If continuous calibrartion mode is active, calibration busy will allmost
\r
855 * always be on, and we just need to read the value, where the normal case
\r
856 * would be that this function call has been triggered by the CALRDY
\r
859 * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
\r
860 * in the period of DOWNSEL oscillator clock cycles configured by a previous
\r
861 * write operation to CMU->CALCNT
\r
862 ******************************************************************************/
\r
863 __STATIC_INLINE uint32_t CMU_CalibrateCountGet(void)
\r
865 /* Wait until calibration completes, UNLESS continuous calibration mode is */
\r
867 #if defined( CMU_CALCTRL_CONT )
\r
868 if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))
\r
870 while (CMU->STATUS & CMU_STATUS_CALBSY)
\r
874 while (CMU->STATUS & CMU_STATUS_CALBSY)
\r
877 return CMU->CALCNT;
\r
881 /***************************************************************************//**
\r
883 * Starts calibration
\r
885 * This call is usually invoked after CMU_CalibrateConfig() and possibly
\r
886 * CMU_CalibrateCont()
\r
887 ******************************************************************************/
\r
888 __STATIC_INLINE void CMU_CalibrateStart(void)
\r
890 CMU->CMD = CMU_CMD_CALSTART;
\r
894 #if defined( CMU_CMD_CALSTOP )
\r
895 /***************************************************************************//**
\r
897 * Stop the calibration counters
\r
898 ******************************************************************************/
\r
899 __STATIC_INLINE void CMU_CalibrateStop(void)
\r
901 CMU->CMD = CMU_CMD_CALSTOP;
\r
906 #if defined( CMU_CALCTRL_CONT )
\r
907 /***************************************************************************//**
\r
909 * Configures continuous calibration mode
\r
910 * @param[in] enable
\r
911 * If true, enables continuous calibration, if false disables continuous
\r
913 ******************************************************************************/
\r
914 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
\r
916 BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
\r
920 /** @} (end addtogroup CMU) */
\r
921 /** @} (end addtogroup EM_Library) */
\r
927 #endif /* defined( CMU_PRESENT ) */
\r
928 #endif /* __SILICON_LABS_EM_CMU_H_ */
\r
projects / freertos / blob