1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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5 * @date 22. August 2014
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2014 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #if defined ( __ICCARM__ )
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39 #pragma system_include /* treat file as system include file for MISRA check */
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42 #ifndef __CORE_CM3_H_GENERIC
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43 #define __CORE_CM3_H_GENERIC
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49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 CMSIS violates the following MISRA-C:2004 rules:
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52 \li Required Rule 8.5, object/function definition in header file.<br>
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53 Function definitions in header files are used to allow 'inlining'.
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55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 Unions are used for effective representation of core registers.
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58 \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \ingroup Cortex_M3
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70 /* CMSIS CM3 definitions */
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71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
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74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
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79 #if defined ( __CC_ARM )
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80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 #define __STATIC_INLINE static __inline
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84 #elif defined ( __GNUC__ )
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85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 #define __STATIC_INLINE static inline
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89 #elif defined ( __ICCARM__ )
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90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 #define __STATIC_INLINE static inline
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94 #elif defined ( __TMS470__ )
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95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 #define __STATIC_INLINE static inline
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98 #elif defined ( __TASKING__ )
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99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 #define __STATIC_INLINE static inline
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103 #elif defined ( __CSMC__ )
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105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 #define __STATIC_INLINE static inline
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111 /** __FPU_USED indicates whether an FPU is used or not.
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112 This core does not support an FPU at all
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114 #define __FPU_USED 0
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116 #if defined ( __CC_ARM )
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117 #if defined __TARGET_FPU_VFP
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118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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121 #elif defined ( __GNUC__ )
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122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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126 #elif defined ( __ICCARM__ )
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127 #if defined __ARMVFP__
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128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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131 #elif defined ( __TMS470__ )
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132 #if defined __TI__VFP_SUPPORT____
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133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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136 #elif defined ( __TASKING__ )
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137 #if defined __FPU_VFP__
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138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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141 #elif defined ( __CSMC__ ) /* Cosmic */
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142 #if ( __CSMC__ & 0x400) // FPU present for parser
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143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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147 #include <stdint.h> /* standard types definitions */
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148 #include <core_cmInstr.h> /* Core Instruction Access */
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149 #include <core_cmFunc.h> /* Core Function Access */
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155 #endif /* __CORE_CM3_H_GENERIC */
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157 #ifndef __CMSIS_GENERIC
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159 #ifndef __CORE_CM3_H_DEPENDANT
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160 #define __CORE_CM3_H_DEPENDANT
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166 /* check device defines and use defaults */
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167 #if defined __CHECK_DEVICE_DEFINES
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169 #define __CM3_REV 0x0200
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170 #warning "__CM3_REV not defined in device header file; using default!"
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173 #ifndef __MPU_PRESENT
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174 #define __MPU_PRESENT 0
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175 #warning "__MPU_PRESENT not defined in device header file; using default!"
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178 #ifndef __NVIC_PRIO_BITS
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179 #define __NVIC_PRIO_BITS 4
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180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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183 #ifndef __Vendor_SysTickConfig
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184 #define __Vendor_SysTickConfig 0
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185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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189 /* IO definitions (access restrictions to peripheral registers) */
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191 \defgroup CMSIS_glob_defs CMSIS Global Defines
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193 <strong>IO Type Qualifiers</strong> are used
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194 \li to specify the access to peripheral variables.
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195 \li for automatic generation of peripheral register debug information.
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198 #define __I volatile /*!< Defines 'read only' permissions */
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200 #define __I volatile const /*!< Defines 'read only' permissions */
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202 #define __O volatile /*!< Defines 'write only' permissions */
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203 #define __IO volatile /*!< Defines 'read / write' permissions */
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205 /*@} end of group Cortex_M3 */
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209 /*******************************************************************************
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210 * Register Abstraction
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211 Core Register contain:
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213 - Core NVIC Register
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214 - Core SCB Register
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215 - Core SysTick Register
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216 - Core Debug Register
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217 - Core MPU Register
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218 ******************************************************************************/
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219 /** \defgroup CMSIS_core_register Defines and Type Definitions
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220 \brief Type definitions and defines for Cortex-M processor based devices.
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223 /** \ingroup CMSIS_core_register
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224 \defgroup CMSIS_CORE Status and Control Registers
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225 \brief Core Register type definitions.
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229 /** \brief Union type to access the Application Program Status Register (APSR).
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235 #if (__CORTEX_M != 0x04)
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236 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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238 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
\r
239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
240 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
\r
242 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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243 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
244 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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245 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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246 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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247 } b; /*!< Structure used for bit access */
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248 uint32_t w; /*!< Type used for word access */
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252 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
\r
258 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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259 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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260 } b; /*!< Structure used for bit access */
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261 uint32_t w; /*!< Type used for word access */
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265 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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271 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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272 #if (__CORTEX_M != 0x04)
\r
273 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
\r
275 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
\r
276 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
277 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
279 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
\r
280 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
\r
281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
\r
282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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286 } b; /*!< Structure used for bit access */
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287 uint32_t w; /*!< Type used for word access */
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291 /** \brief Union type to access the Control Registers (CONTROL).
\r
297 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
\r
298 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
\r
299 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
\r
300 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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301 } b; /*!< Structure used for bit access */
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302 uint32_t w; /*!< Type used for word access */
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305 /*@} end of group CMSIS_CORE */
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308 /** \ingroup CMSIS_core_register
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309 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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310 \brief Type definitions for the NVIC Registers
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314 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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318 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
\r
319 uint32_t RESERVED0[24];
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320 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
\r
321 uint32_t RSERVED1[24];
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322 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
\r
323 uint32_t RESERVED2[24];
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324 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
\r
325 uint32_t RESERVED3[24];
\r
326 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
\r
327 uint32_t RESERVED4[56];
\r
328 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
\r
329 uint32_t RESERVED5[644];
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330 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
\r
333 /* Software Triggered Interrupt Register Definitions */
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334 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
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335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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337 /*@} end of group CMSIS_NVIC */
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340 /** \ingroup CMSIS_core_register
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341 \defgroup CMSIS_SCB System Control Block (SCB)
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342 \brief Type definitions for the System Control Block Registers
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346 /** \brief Structure type to access the System Control Block (SCB).
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350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
\r
351 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
352 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
353 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
354 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
355 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
356 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
357 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
358 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
359 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
\r
360 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
361 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
\r
362 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
\r
363 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
364 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
\r
365 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
366 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
367 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
368 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
\r
369 uint32_t RESERVED0[5];
\r
370 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
\r
373 /* SCB CPUID Register Definitions */
\r
374 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
\r
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
377 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
\r
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
380 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
\r
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
383 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
\r
384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
386 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
\r
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
\r
389 /* SCB Interrupt Control State Register Definitions */
\r
390 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
\r
391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
\r
393 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
\r
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
396 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
\r
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
399 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
\r
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
402 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
\r
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
405 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
\r
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
408 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
\r
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
411 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
\r
412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
414 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
\r
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
417 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
\r
418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
\r
420 /* SCB Vector Table Offset Register Definitions */
\r
421 #if (__CM3_REV < 0x0201) /* core r2p1 */
\r
422 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
\r
423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
\r
425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
\r
426 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
428 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
\r
429 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
432 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
433 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
\r
434 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
436 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
437 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
439 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
\r
440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
442 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
\r
443 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
445 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
\r
446 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
448 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
449 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
451 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
\r
452 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
\r
454 /* SCB System Control Register Definitions */
\r
455 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
\r
456 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
458 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
\r
459 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
461 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
\r
462 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
464 /* SCB Configuration Control Register Definitions */
\r
465 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
\r
466 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
468 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
\r
469 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
471 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
\r
472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
474 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
\r
475 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
477 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
\r
478 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
480 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
\r
481 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
483 /* SCB System Handler Control and State Register Definitions */
\r
484 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
\r
485 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
487 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
\r
488 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
490 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
\r
491 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
493 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
\r
494 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
496 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
497 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
499 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
500 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
502 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
503 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
505 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
\r
506 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
508 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
\r
509 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
511 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
\r
512 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
514 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
\r
515 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
517 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
\r
518 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
520 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
\r
521 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
523 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
\r
524 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
526 /* SCB Configurable Fault Status Registers Definitions */
\r
527 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
\r
528 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
530 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
\r
531 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
533 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
534 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
536 /* SCB Hard Fault Status Registers Definitions */
\r
537 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
\r
538 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
540 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
\r
541 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
543 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
\r
544 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
546 /* SCB Debug Fault Status Register Definitions */
\r
547 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
\r
548 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
550 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
\r
551 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
553 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
\r
554 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
556 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
\r
557 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
559 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
\r
560 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
\r
562 /*@} end of group CMSIS_SCB */
\r
565 /** \ingroup CMSIS_core_register
\r
566 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\r
567 \brief Type definitions for the System Control and ID Register not in the SCB
\r
571 /** \brief Structure type to access the System Control and ID Register not in the SCB.
\r
575 uint32_t RESERVED0[1];
\r
576 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
\r
577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
\r
578 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
580 uint32_t RESERVED1[1];
\r
584 /* Interrupt Controller Type Register Definitions */
\r
585 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
\r
586 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
\r
588 /* Auxiliary Control Register Definitions */
\r
590 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
\r
591 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
\r
593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
\r
594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
\r
596 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
\r
597 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
\r
599 /*@} end of group CMSIS_SCnotSCB */
\r
602 /** \ingroup CMSIS_core_register
\r
603 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
604 \brief Type definitions for the System Timer Registers.
\r
608 /** \brief Structure type to access the System Timer (SysTick).
\r
612 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
613 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
614 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
615 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
618 /* SysTick Control / Status Register Definitions */
\r
619 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
\r
620 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
622 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
623 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
625 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
626 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
628 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
629 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
\r
631 /* SysTick Reload Register Definitions */
\r
632 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
633 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
\r
635 /* SysTick Current Register Definitions */
\r
636 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
637 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
\r
639 /* SysTick Calibration Register Definitions */
\r
640 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
641 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
643 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
644 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
646 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
647 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
\r
649 /*@} end of group CMSIS_SysTick */
\r
652 /** \ingroup CMSIS_core_register
\r
653 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\r
654 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
\r
658 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
664 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
665 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
666 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
667 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
668 uint32_t RESERVED0[864];
\r
669 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
\r
670 uint32_t RESERVED1[15];
\r
671 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
\r
672 uint32_t RESERVED2[15];
\r
673 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
\r
674 uint32_t RESERVED3[29];
\r
675 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
\r
676 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
\r
677 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
\r
678 uint32_t RESERVED4[43];
\r
679 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
\r
680 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
\r
681 uint32_t RESERVED5[6];
\r
682 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
\r
683 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
\r
684 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
\r
685 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
\r
686 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
\r
687 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
\r
688 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
\r
689 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
\r
690 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
\r
691 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
\r
692 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
\r
693 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
\r
696 /* ITM Trace Privilege Register Definitions */
\r
697 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
\r
698 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
\r
700 /* ITM Trace Control Register Definitions */
\r
701 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
\r
702 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
704 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
\r
705 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
\r
707 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
\r
708 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
\r
710 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
\r
711 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
\r
713 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
\r
714 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
716 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
\r
717 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
719 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
\r
720 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
722 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
\r
723 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
725 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
\r
726 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
\r
728 /* ITM Integration Write Register Definitions */
\r
729 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
\r
730 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
\r
732 /* ITM Integration Read Register Definitions */
\r
733 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
\r
734 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
\r
736 /* ITM Integration Mode Control Register Definitions */
\r
737 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
\r
738 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
\r
740 /* ITM Lock Status Register Definitions */
\r
741 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
\r
742 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
744 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
\r
745 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
747 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
\r
748 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
\r
750 /*@}*/ /* end of group CMSIS_ITM */
\r
753 /** \ingroup CMSIS_core_register
\r
754 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
755 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
759 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
763 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
764 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
\r
765 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
\r
766 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
\r
767 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
\r
768 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
\r
769 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
\r
770 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
771 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
772 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
\r
773 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
774 uint32_t RESERVED0[1];
\r
775 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
776 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
\r
777 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
778 uint32_t RESERVED1[1];
\r
779 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
780 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
\r
781 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
782 uint32_t RESERVED2[1];
\r
783 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
784 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
\r
785 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
788 /* DWT Control Register Definitions */
\r
789 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
\r
790 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
792 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
\r
793 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
795 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
\r
796 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
798 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
\r
799 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
801 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
\r
802 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
804 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
\r
805 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
\r
807 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
\r
808 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
\r
810 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
\r
811 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
\r
813 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
\r
814 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
\r
816 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
\r
817 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
\r
819 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
\r
820 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
\r
822 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
\r
823 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
\r
825 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
\r
826 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
\r
828 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
\r
829 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
\r
831 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
\r
832 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
\r
834 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
\r
835 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
\r
837 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
\r
838 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
\r
840 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
\r
841 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
\r
843 /* DWT CPI Count Register Definitions */
\r
844 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
\r
845 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
\r
847 /* DWT Exception Overhead Count Register Definitions */
\r
848 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
\r
849 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
\r
851 /* DWT Sleep Count Register Definitions */
\r
852 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
\r
853 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
\r
855 /* DWT LSU Count Register Definitions */
\r
856 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
\r
857 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
\r
859 /* DWT Folded-instruction Count Register Definitions */
\r
860 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
\r
861 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
\r
863 /* DWT Comparator Mask Register Definitions */
\r
864 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
\r
865 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
\r
867 /* DWT Comparator Function Register Definitions */
\r
868 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
\r
869 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
871 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
\r
872 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
\r
874 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
\r
875 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
\r
877 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
\r
878 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
880 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
\r
881 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
\r
883 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
\r
884 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
\r
886 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
\r
887 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
\r
889 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
\r
890 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
\r
892 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
\r
893 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
\r
895 /*@}*/ /* end of group CMSIS_DWT */
\r
898 /** \ingroup CMSIS_core_register
\r
899 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
900 \brief Type definitions for the Trace Port Interface (TPI)
\r
904 /** \brief Structure type to access the Trace Port Interface Register (TPI).
\r
908 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
909 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
910 uint32_t RESERVED0[2];
\r
911 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
912 uint32_t RESERVED1[55];
\r
913 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
914 uint32_t RESERVED2[131];
\r
915 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
916 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
917 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
918 uint32_t RESERVED3[759];
\r
919 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
920 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
921 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
922 uint32_t RESERVED4[1];
\r
923 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
924 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
925 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
926 uint32_t RESERVED5[39];
\r
927 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
928 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
929 uint32_t RESERVED7[8];
\r
930 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
931 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
934 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
935 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
\r
936 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
\r
938 /* TPI Selected Pin Protocol Register Definitions */
\r
939 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
\r
940 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
\r
942 /* TPI Formatter and Flush Status Register Definitions */
\r
943 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
\r
944 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
946 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
\r
947 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
949 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
\r
950 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
952 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
\r
953 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
\r
955 /* TPI Formatter and Flush Control Register Definitions */
\r
956 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
\r
957 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
959 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
\r
960 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
962 /* TPI TRIGGER Register Definitions */
\r
963 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
\r
964 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
\r
966 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
967 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
\r
968 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
970 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
\r
971 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
973 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
\r
974 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
976 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
\r
977 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
979 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
\r
980 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
982 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
\r
983 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
985 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
\r
986 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
\r
988 /* TPI ITATBCTR2 Register Definitions */
\r
989 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
\r
990 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
992 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
993 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
\r
994 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
996 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
\r
997 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
999 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
\r
1000 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
1002 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
\r
1003 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
1005 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
\r
1006 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
1008 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
\r
1009 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
1011 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
\r
1012 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
\r
1014 /* TPI ITATBCTR0 Register Definitions */
\r
1015 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
\r
1016 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
1018 /* TPI Integration Mode Control Register Definitions */
\r
1019 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
\r
1020 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
\r
1022 /* TPI DEVID Register Definitions */
\r
1023 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
\r
1024 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
1026 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
\r
1027 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
1029 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
\r
1030 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
1032 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
\r
1033 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
1035 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
\r
1036 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
1038 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
\r
1039 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
\r
1041 /* TPI DEVTYPE Register Definitions */
\r
1042 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
\r
1043 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
\r
1045 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
\r
1046 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
1048 /*@}*/ /* end of group CMSIS_TPI */
\r
1051 #if (__MPU_PRESENT == 1)
\r
1052 /** \ingroup CMSIS_core_register
\r
1053 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
1054 \brief Type definitions for the Memory Protection Unit (MPU)
\r
1058 /** \brief Structure type to access the Memory Protection Unit (MPU).
\r
1062 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
1063 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
1064 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
1065 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
1066 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
1067 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
\r
1068 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
\r
1069 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
\r
1070 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
\r
1071 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
\r
1072 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
\r
1075 /* MPU Type Register */
\r
1076 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
\r
1077 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
1079 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
\r
1080 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
1082 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
\r
1083 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
\r
1085 /* MPU Control Register */
\r
1086 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
\r
1087 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
1089 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
\r
1090 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
1092 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
\r
1093 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
\r
1095 /* MPU Region Number Register */
\r
1096 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
\r
1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
\r
1099 /* MPU Region Base Address Register */
\r
1100 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
\r
1101 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
1103 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
\r
1104 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
1106 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
\r
1107 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
\r
1109 /* MPU Region Attribute and Size Register */
\r
1110 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
\r
1111 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
\r
1113 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
\r
1114 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
\r
1116 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
\r
1117 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
\r
1119 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
\r
1120 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
\r
1122 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
\r
1123 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
\r
1125 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
\r
1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
\r
1128 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
\r
1129 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
\r
1131 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
\r
1132 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
1134 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
\r
1135 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
1137 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
\r
1138 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
\r
1140 /*@} end of group CMSIS_MPU */
\r
1144 /** \ingroup CMSIS_core_register
\r
1145 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1146 \brief Type definitions for the Core Debug Registers
\r
1150 /** \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1154 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1155 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1156 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1157 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1160 /* Debug Halting Control and Status Register */
\r
1161 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1162 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1164 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1165 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1170 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1171 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1173 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1174 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1176 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
\r
1177 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1179 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1180 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
1183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
1185 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1186 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1188 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
\r
1189 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1191 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
\r
1192 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1197 /* Debug Core Register Selector Register */
\r
1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
\r
1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1201 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
\r
1202 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1204 /* Debug Exception and Monitor Control Register */
\r
1205 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
\r
1206 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
1208 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
\r
1209 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
1211 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
\r
1212 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
1214 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
\r
1215 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
1217 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
\r
1218 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
1220 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1221 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1223 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
1224 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
1226 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
1227 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
1229 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
1230 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
1232 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
1233 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
1235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
1236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
1238 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
1239 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
1241 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1242 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1244 /*@} end of group CMSIS_CoreDebug */
\r
1247 /** \ingroup CMSIS_core_register
\r
1248 \defgroup CMSIS_core_base Core Definitions
\r
1249 \brief Definitions for base addresses, unions, and structures.
\r
1253 /* Memory mapping of Cortex-M3 Hardware */
\r
1254 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1255 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
1256 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1257 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1258 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1259 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1260 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1261 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1263 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
\r
1264 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1265 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1266 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1267 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
\r
1268 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1269 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1270 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
\r
1272 #if (__MPU_PRESENT == 1)
\r
1273 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1274 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1281 /*******************************************************************************
\r
1282 * Hardware Abstraction Layer
\r
1283 Core Function Interface contains:
\r
1284 - Core NVIC Functions
\r
1285 - Core SysTick Functions
\r
1286 - Core Debug Functions
\r
1287 - Core Register Access Functions
\r
1288 ******************************************************************************/
\r
1289 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1294 /* ########################## NVIC functions #################################### */
\r
1295 /** \ingroup CMSIS_Core_FunctionInterface
\r
1296 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1297 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1301 /** \brief Set Priority Grouping
\r
1303 The function sets the priority grouping field using the required unlock sequence.
\r
1304 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
1305 Only values from 0..7 are used.
\r
1306 In case of a conflict between priority grouping and available
\r
1307 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1309 \param [in] PriorityGroup Priority grouping field.
\r
1311 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
1313 uint32_t reg_value;
\r
1314 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
\r
1316 reg_value = SCB->AIRCR; /* read old register configuration */
\r
1317 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
\r
1318 reg_value = (reg_value |
\r
1319 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
\r
1320 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
\r
1321 SCB->AIRCR = reg_value;
\r
1325 /** \brief Get Priority Grouping
\r
1327 The function reads the priority grouping field from the NVIC Interrupt Controller.
\r
1329 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
\r
1331 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
\r
1333 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
\r
1337 /** \brief Enable External Interrupt
\r
1339 The function enables a device-specific interrupt in the NVIC interrupt controller.
\r
1341 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1343 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
\r
1349 /** \brief Disable External Interrupt
\r
1351 The function disables a device-specific interrupt in the NVIC interrupt controller.
\r
1353 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1355 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1357 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
\r
1361 /** \brief Get Pending Interrupt
\r
1363 The function reads the pending register in the NVIC and returns the pending bit
\r
1364 for the specified interrupt.
\r
1366 \param [in] IRQn Interrupt number.
\r
1368 \return 0 Interrupt status is not pending.
\r
1369 \return 1 Interrupt status is pending.
\r
1371 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1373 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
\r
1377 /** \brief Set Pending Interrupt
\r
1379 The function sets the pending bit of an external interrupt.
\r
1381 \param [in] IRQn Interrupt number. Value cannot be negative.
\r
1383 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1385 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
\r
1389 /** \brief Clear Pending Interrupt
\r
1391 The function clears the pending bit of an external interrupt.
\r
1393 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1395 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1397 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
\r
1401 /** \brief Get Active Interrupt
\r
1403 The function reads the active register in NVIC and returns the active bit.
\r
1405 \param [in] IRQn Interrupt number.
\r
1407 \return 0 Interrupt status is not active.
\r
1408 \return 1 Interrupt status is active.
\r
1410 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\r
1412 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
\r
1416 /** \brief Set Interrupt Priority
\r
1418 The function sets the priority of an interrupt.
\r
1420 \note The priority cannot be set for every core interrupt.
\r
1422 \param [in] IRQn Interrupt number.
\r
1423 \param [in] priority Priority to set.
\r
1425 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1428 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
\r
1430 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
\r
1434 /** \brief Get Interrupt Priority
\r
1436 The function reads the priority of an interrupt. The interrupt
\r
1437 number can be positive to specify an external (device specific)
\r
1438 interrupt, or negative to specify an internal (core) interrupt.
\r
1441 \param [in] IRQn Interrupt number.
\r
1442 \return Interrupt Priority. Value is aligned automatically to the implemented
\r
1443 priority bits of the microcontroller.
\r
1445 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
1449 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
\r
1451 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
\r
1455 /** \brief Encode Priority
\r
1457 The function encodes the priority for an interrupt with the given priority group,
\r
1458 preemptive priority value, and subpriority value.
\r
1459 In case of a conflict between priority grouping and available
\r
1460 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1462 \param [in] PriorityGroup Used priority group.
\r
1463 \param [in] PreemptPriority Preemptive priority value (starting from 0).
\r
1464 \param [in] SubPriority Subpriority value (starting from 0).
\r
1465 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
\r
1467 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
1469 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1470 uint32_t PreemptPriorityBits;
\r
1471 uint32_t SubPriorityBits;
\r
1473 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1474 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1477 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
\r
1478 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
\r
1483 /** \brief Decode Priority
\r
1485 The function decodes an interrupt priority value with a given priority group to
\r
1486 preemptive priority value and subpriority value.
\r
1487 In case of a conflict between priority grouping and available
\r
1488 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
1490 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\r
1491 \param [in] PriorityGroup Used priority group.
\r
1492 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\r
1493 \param [out] pSubPriority Subpriority value (starting from 0).
\r
1495 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
\r
1497 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1498 uint32_t PreemptPriorityBits;
\r
1499 uint32_t SubPriorityBits;
\r
1501 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1502 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1504 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
\r
1505 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
\r
1509 /** \brief System Reset
\r
1511 The function initiates a system reset request to reset the MCU.
\r
1513 __STATIC_INLINE void NVIC_SystemReset(void)
\r
1515 __DSB(); /* Ensure all outstanding memory accesses included
\r
1516 buffered write are completed before reset */
\r
1517 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
\r
1518 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
\r
1519 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
\r
1520 __DSB(); /* Ensure completion of memory access */
\r
1521 while(1); /* wait until reset */
\r
1524 /*@} end of CMSIS_Core_NVICFunctions */
\r
1528 /* ################################## SysTick function ############################################ */
\r
1529 /** \ingroup CMSIS_Core_FunctionInterface
\r
1530 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
1531 \brief Functions that configure the System.
\r
1535 #if (__Vendor_SysTickConfig == 0)
\r
1537 /** \brief System Tick Configuration
\r
1539 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
1540 Counter is in free running mode to generate periodic interrupts.
\r
1542 \param [in] ticks Number of ticks between two interrupts.
\r
1544 \return 0 Function succeeded.
\r
1545 \return 1 Function failed.
\r
1547 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
1548 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
1549 must contain a vendor-specific implementation of this function.
\r
1552 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
1554 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
\r
1556 SysTick->LOAD = ticks - 1; /* set reload register */
\r
1557 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
\r
1558 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
1559 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
1560 SysTick_CTRL_TICKINT_Msk |
\r
1561 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
1562 return (0); /* Function successful */
\r
1567 /*@} end of CMSIS_Core_SysTickFunctions */
\r
1571 /* ##################################### Debug In/Output function ########################################### */
\r
1572 /** \ingroup CMSIS_Core_FunctionInterface
\r
1573 \defgroup CMSIS_core_DebugFunctions ITM Functions
\r
1574 \brief Functions that access the ITM debug interface.
\r
1578 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
\r
1579 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
\r
1582 /** \brief ITM Send Character
\r
1584 The function transmits a character via the ITM channel 0, and
\r
1585 \li Just returns when no debugger is connected that has booked the output.
\r
1586 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\r
1588 \param [in] ch Character to transmit.
\r
1590 \returns Character to transmit.
\r
1592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
\r
1594 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
\r
1595 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
\r
1597 while (ITM->PORT[0].u32 == 0);
\r
1598 ITM->PORT[0].u8 = (uint8_t) ch;
\r
1604 /** \brief ITM Receive Character
\r
1606 The function inputs a character via the external variable \ref ITM_RxBuffer.
\r
1608 \return Received character.
\r
1609 \return -1 No character pending.
\r
1611 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
\r
1612 int32_t ch = -1; /* no character available */
\r
1614 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
\r
1615 ch = ITM_RxBuffer;
\r
1616 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
\r
1623 /** \brief ITM Check Character
\r
1625 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\r
1627 \return 0 No character available.
\r
1628 \return 1 Character available.
\r
1630 __STATIC_INLINE int32_t ITM_CheckChar (void) {
\r
1632 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
\r
1633 return (0); /* no character available */
\r
1635 return (1); /* character available */
\r
1639 /*@} end of CMSIS_core_DebugFunctions */
\r
1644 #ifdef __cplusplus
\r
1648 #endif /* __CORE_CM3_H_DEPENDANT */
\r
1650 #endif /* __CMSIS_GENERIC */
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projects / freertos / blob