1 /**************************************************************************//**
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2 * @file efm32wg_lcd.h
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3 * @brief EFM32WG_LCD register and bit field definitions
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5 ******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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33 * @defgroup EFM32WG_LCD
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35 * @brief EFM32WG_LCD Register Declaration
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36 *****************************************************************************/
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39 __IO uint32_t CTRL; /**< Control Register */
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40 __IO uint32_t DISPCTRL; /**< Display Control Register */
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41 __IO uint32_t SEGEN; /**< Segment Enable Register */
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42 __IO uint32_t BACTRL; /**< Blink and Animation Control Register */
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43 __I uint32_t STATUS; /**< Status Register */
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44 __IO uint32_t AREGA; /**< Animation Register A */
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45 __IO uint32_t AREGB; /**< Animation Register B */
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46 __I uint32_t IF; /**< Interrupt Flag Register */
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47 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
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48 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
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49 __IO uint32_t IEN; /**< Interrupt Enable Register */
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51 uint32_t RESERVED0[5]; /**< Reserved for future use **/
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52 __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
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53 __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
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54 __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
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55 __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
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56 __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
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57 __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
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58 __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
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59 __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
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61 __IO uint32_t FREEZE; /**< Freeze Register */
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62 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
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64 uint32_t RESERVED1[19]; /**< Reserved for future use **/
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65 __IO uint32_t SEGD4H; /**< Segment Data High Register 4 */
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66 __IO uint32_t SEGD5H; /**< Segment Data High Register 5 */
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67 __IO uint32_t SEGD6H; /**< Segment Data High Register 6 */
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68 __IO uint32_t SEGD7H; /**< Segment Data High Register 7 */
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69 uint32_t RESERVED2[2]; /**< Reserved for future use **/
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70 __IO uint32_t SEGD4L; /**< Segment Data Low Register 4 */
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71 __IO uint32_t SEGD5L; /**< Segment Data Low Register 5 */
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72 __IO uint32_t SEGD6L; /**< Segment Data Low Register 6 */
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73 __IO uint32_t SEGD7L; /**< Segment Data Low Register 7 */
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74 } LCD_TypeDef; /** @} */
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76 /**************************************************************************//**
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77 * @defgroup EFM32WG_LCD_BitFields
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79 *****************************************************************************/
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81 /* Bit fields for LCD CTRL */
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82 #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
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83 #define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
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84 #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
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85 #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
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86 #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
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87 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
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88 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
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89 #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
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90 #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
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91 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
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92 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
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93 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
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94 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
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95 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
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96 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
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97 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
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98 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
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99 #define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
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100 #define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
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101 #define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
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102 #define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
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103 #define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
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105 /* Bit fields for LCD DISPCTRL */
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106 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */
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107 #define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */
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108 #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
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109 #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */
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110 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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111 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
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112 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
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113 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
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114 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
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115 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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116 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
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117 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
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118 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
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119 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
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120 #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */
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121 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */
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122 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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123 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
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124 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
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125 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
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126 #define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
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127 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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128 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */
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129 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
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130 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
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131 #define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
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132 #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
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133 #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
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134 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
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135 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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136 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
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137 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
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138 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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139 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
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140 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
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141 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */
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142 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */
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143 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */
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144 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */
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145 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */
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146 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */
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147 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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148 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */
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149 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */
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150 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */
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151 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */
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152 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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153 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */
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154 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */
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155 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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156 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */
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157 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */
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158 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */
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159 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */
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160 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */
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161 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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162 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */
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163 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */
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164 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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165 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */
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166 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */
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167 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */
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168 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */
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169 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */
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170 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */
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171 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */
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172 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */
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173 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */
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174 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */
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175 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */
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176 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */
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177 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */
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178 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */
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179 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */
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180 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */
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181 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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182 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */
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183 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */
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184 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */
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185 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */
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186 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */
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187 #define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */
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188 #define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */
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189 #define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */
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190 #define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
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191 #define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */
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192 #define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */
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193 #define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
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194 #define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */
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195 #define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */
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197 /* Bit fields for LCD SEGEN */
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198 #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
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199 #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */
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200 #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
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201 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */
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202 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
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203 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
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205 /* Bit fields for LCD BACTRL */
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206 #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
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207 #define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
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208 #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
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209 #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
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210 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
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211 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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212 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
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213 #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
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214 #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
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215 #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
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216 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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217 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
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218 #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
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219 #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
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220 #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
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221 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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222 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
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223 #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
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224 #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
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225 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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226 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
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227 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
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228 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
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229 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
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230 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
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231 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
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232 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
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233 #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
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234 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
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235 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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236 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
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237 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
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238 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
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239 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
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240 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
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241 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
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242 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
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243 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
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244 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
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245 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
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246 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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247 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
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248 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
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249 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
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250 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
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251 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
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252 #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
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253 #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
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254 #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
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255 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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256 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
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257 #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
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258 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
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259 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
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260 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
\r
261 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
\r
262 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
\r
263 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
\r
264 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
\r
265 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
\r
266 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
\r
267 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
\r
268 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
\r
269 #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
\r
270 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
\r
271 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
\r
272 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
\r
273 #define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
\r
274 #define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
\r
275 #define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
\r
276 #define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
\r
277 #define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
\r
278 #define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
\r
279 #define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
\r
280 #define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
\r
281 #define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
\r
283 /* Bit fields for LCD STATUS */
\r
284 #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
\r
285 #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
\r
286 #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
\r
287 #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
\r
288 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
\r
289 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
\r
290 #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
\r
291 #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
\r
292 #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
\r
293 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
\r
294 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
\r
296 /* Bit fields for LCD AREGA */
\r
297 #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
\r
298 #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
\r
299 #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
\r
300 #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
\r
301 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
\r
302 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
\r
304 /* Bit fields for LCD AREGB */
\r
305 #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
\r
306 #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
\r
307 #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
\r
308 #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
\r
309 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
\r
310 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
\r
312 /* Bit fields for LCD IF */
\r
313 #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
\r
314 #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
\r
315 #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
\r
316 #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
\r
317 #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
\r
318 #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
\r
319 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
\r
321 /* Bit fields for LCD IFS */
\r
322 #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
\r
323 #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
\r
324 #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
\r
325 #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
\r
326 #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
\r
327 #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
\r
328 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
\r
330 /* Bit fields for LCD IFC */
\r
331 #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
\r
332 #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
\r
333 #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
\r
334 #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
\r
335 #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
\r
336 #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
\r
337 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
\r
339 /* Bit fields for LCD IEN */
\r
340 #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
\r
341 #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
\r
342 #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
\r
343 #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
\r
344 #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
\r
345 #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
\r
346 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
\r
348 /* Bit fields for LCD SEGD0L */
\r
349 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
\r
350 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
\r
351 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
\r
352 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
\r
353 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
\r
354 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
\r
356 /* Bit fields for LCD SEGD1L */
\r
357 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
\r
358 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
\r
359 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
\r
360 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
\r
361 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
\r
362 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
\r
364 /* Bit fields for LCD SEGD2L */
\r
365 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
\r
366 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
\r
367 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
\r
368 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
\r
369 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
\r
370 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
\r
372 /* Bit fields for LCD SEGD3L */
\r
373 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
\r
374 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
\r
375 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
\r
376 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
\r
377 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
\r
378 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
\r
380 /* Bit fields for LCD SEGD0H */
\r
381 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
\r
382 #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
\r
383 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
\r
384 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
\r
385 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
\r
386 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
\r
388 /* Bit fields for LCD SEGD1H */
\r
389 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
\r
390 #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
\r
391 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
\r
392 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
\r
393 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
\r
394 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
\r
396 /* Bit fields for LCD SEGD2H */
\r
397 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
\r
398 #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
\r
399 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
\r
400 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
\r
401 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
\r
402 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
\r
404 /* Bit fields for LCD SEGD3H */
\r
405 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
\r
406 #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
\r
407 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
\r
408 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
\r
409 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
\r
410 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
\r
412 /* Bit fields for LCD FREEZE */
\r
413 #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
\r
414 #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */
\r
415 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
\r
416 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
\r
417 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
\r
418 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
\r
419 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
\r
420 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
\r
421 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
\r
422 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
\r
423 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
\r
425 /* Bit fields for LCD SYNCBUSY */
\r
426 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
\r
427 #define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
\r
428 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
\r
429 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
\r
430 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
\r
431 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
432 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
433 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
\r
434 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
\r
435 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
\r
436 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
437 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
438 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
\r
439 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
\r
440 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
\r
441 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
442 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
443 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
\r
444 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
\r
445 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
\r
446 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
447 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
448 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
\r
449 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
\r
450 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
\r
451 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
452 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
453 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
\r
454 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
\r
455 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
\r
456 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
457 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
458 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
\r
459 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
\r
460 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
\r
461 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
462 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
463 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
\r
464 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
\r
465 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
\r
466 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
467 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
468 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
\r
469 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
\r
470 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
\r
471 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
472 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
473 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
\r
474 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
\r
475 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
\r
476 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
477 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
478 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
\r
479 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
\r
480 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
\r
481 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
482 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
483 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
\r
484 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
\r
485 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
\r
486 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
487 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
488 #define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */
\r
489 #define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */
\r
490 #define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */
\r
491 #define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
492 #define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
493 #define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */
\r
494 #define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */
\r
495 #define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */
\r
496 #define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
497 #define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
498 #define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */
\r
499 #define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */
\r
500 #define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */
\r
501 #define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
\r
502 #define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
\r
503 #define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */
\r
504 #define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */
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505 #define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */
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506 #define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
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507 #define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
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508 #define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */
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509 #define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */
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510 #define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */
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511 #define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
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512 #define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
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513 #define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */
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514 #define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */
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515 #define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */
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516 #define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
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517 #define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
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518 #define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */
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519 #define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */
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520 #define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */
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521 #define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
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522 #define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
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523 #define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */
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524 #define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */
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525 #define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */
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526 #define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
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527 #define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
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529 /* Bit fields for LCD SEGD4H */
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530 #define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
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531 #define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
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532 #define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
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533 #define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
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534 #define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
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535 #define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
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537 /* Bit fields for LCD SEGD5H */
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538 #define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
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539 #define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
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540 #define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
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541 #define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
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542 #define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
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543 #define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
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545 /* Bit fields for LCD SEGD6H */
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546 #define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
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547 #define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
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548 #define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
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549 #define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
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550 #define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
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551 #define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
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553 /* Bit fields for LCD SEGD7H */
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554 #define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
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555 #define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
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556 #define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
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557 #define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
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558 #define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
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559 #define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
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561 /* Bit fields for LCD SEGD4L */
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562 #define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
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563 #define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
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564 #define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
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565 #define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
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566 #define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
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567 #define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
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569 /* Bit fields for LCD SEGD5L */
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570 #define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
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571 #define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
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572 #define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
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573 #define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
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574 #define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
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575 #define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
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577 /* Bit fields for LCD SEGD6L */
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578 #define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
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579 #define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
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580 #define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
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581 #define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
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582 #define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
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583 #define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
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585 /* Bit fields for LCD SEGD7L */
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586 #define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
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587 #define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
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588 #define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
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589 #define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
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590 #define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
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591 #define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
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593 /** @} End of group EFM32WG_LCD */
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projects / freertos / blob