1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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5 * @date 19. April 2017
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef __CORE_CM7_H_GENERIC
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32 #define __CORE_CM7_H_GENERIC
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41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 CMSIS violates the following MISRA-C:2004 rules:
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44 \li Required Rule 8.5, object/function definition in header file.<br>
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45 Function definitions in header files are used to allow 'inlining'.
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47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 Unions are used for effective representation of core registers.
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50 \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 Function-like macros are used to allow more efficient code.
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55 /*******************************************************************************
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57 ******************************************************************************/
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63 #include "cmsis_version.h"
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65 /* CMSIS CM7 definitions */
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66 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
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67 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
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68 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
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69 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
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71 #define __CORTEX_M (7U) /*!< Cortex-M Core */
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73 /** __FPU_USED indicates whether an FPU is used or not.
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74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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76 #if defined ( __CC_ARM )
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77 #if defined __TARGET_FPU_VFP
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78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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79 #define __FPU_USED 1U
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81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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82 #define __FPU_USED 0U
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85 #define __FPU_USED 0U
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88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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89 #if defined __ARM_PCS_VFP
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90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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91 #define __FPU_USED 1U
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93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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94 #define __FPU_USED 0U
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97 #define __FPU_USED 0U
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100 #elif defined ( __GNUC__ )
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101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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103 #define __FPU_USED 1U
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105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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106 #define __FPU_USED 0U
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109 #define __FPU_USED 0U
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112 #elif defined ( __ICCARM__ )
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113 #if defined __ARMVFP__
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114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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115 #define __FPU_USED 1U
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117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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118 #define __FPU_USED 0U
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121 #define __FPU_USED 0U
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124 #elif defined ( __TI_ARM__ )
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125 #if defined __TI_VFP_SUPPORT__
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126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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127 #define __FPU_USED 1U
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129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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130 #define __FPU_USED 0U
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133 #define __FPU_USED 0U
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136 #elif defined ( __TASKING__ )
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137 #if defined __FPU_VFP__
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138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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139 #define __FPU_USED 1U
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141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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142 #define __FPU_USED 0U
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145 #define __FPU_USED 0U
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148 #elif defined ( __CSMC__ )
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149 #if ( __CSMC__ & 0x400U)
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150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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151 #define __FPU_USED 1U
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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154 #define __FPU_USED 0U
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157 #define __FPU_USED 0U
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162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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169 #endif /* __CORE_CM7_H_GENERIC */
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171 #ifndef __CMSIS_GENERIC
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173 #ifndef __CORE_CM7_H_DEPENDANT
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174 #define __CORE_CM7_H_DEPENDANT
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180 /* check device defines and use defaults */
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181 #if defined __CHECK_DEVICE_DEFINES
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183 #define __CM7_REV 0x0000U
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184 #warning "__CM7_REV not defined in device header file; using default!"
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187 #ifndef __FPU_PRESENT
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188 #define __FPU_PRESENT 0U
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189 #warning "__FPU_PRESENT not defined in device header file; using default!"
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192 #ifndef __MPU_PRESENT
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193 #define __MPU_PRESENT 0U
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194 #warning "__MPU_PRESENT not defined in device header file; using default!"
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197 #ifndef __ICACHE_PRESENT
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198 #define __ICACHE_PRESENT 0U
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199 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
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202 #ifndef __DCACHE_PRESENT
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203 #define __DCACHE_PRESENT 0U
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204 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
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207 #ifndef __DTCM_PRESENT
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208 #define __DTCM_PRESENT 0U
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209 #warning "__DTCM_PRESENT not defined in device header file; using default!"
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212 #ifndef __NVIC_PRIO_BITS
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213 #define __NVIC_PRIO_BITS 3U
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214 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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217 #ifndef __Vendor_SysTickConfig
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218 #define __Vendor_SysTickConfig 0U
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219 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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223 /* IO definitions (access restrictions to peripheral registers) */
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225 \defgroup CMSIS_glob_defs CMSIS Global Defines
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227 <strong>IO Type Qualifiers</strong> are used
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228 \li to specify the access to peripheral variables.
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229 \li for automatic generation of peripheral register debug information.
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232 #define __I volatile /*!< Defines 'read only' permissions */
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234 #define __I volatile const /*!< Defines 'read only' permissions */
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236 #define __O volatile /*!< Defines 'write only' permissions */
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237 #define __IO volatile /*!< Defines 'read / write' permissions */
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239 /* following defines should be used for structure members */
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240 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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241 #define __OM volatile /*! Defines 'write only' structure member permissions */
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242 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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244 /*@} end of group Cortex_M7 */
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248 /*******************************************************************************
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249 * Register Abstraction
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250 Core Register contain:
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252 - Core NVIC Register
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253 - Core SCB Register
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254 - Core SysTick Register
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255 - Core Debug Register
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256 - Core MPU Register
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257 - Core FPU Register
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258 ******************************************************************************/
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260 \defgroup CMSIS_core_register Defines and Type Definitions
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261 \brief Type definitions and defines for Cortex-M processor based devices.
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265 \ingroup CMSIS_core_register
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266 \defgroup CMSIS_CORE Status and Control Registers
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267 \brief Core Register type definitions.
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272 \brief Union type to access the Application Program Status Register (APSR).
\r
278 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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279 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
280 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
\r
281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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286 } b; /*!< Structure used for bit access */
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287 uint32_t w; /*!< Type used for word access */
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290 /* APSR Register Definitions */
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291 #define APSR_N_Pos 31U /*!< APSR: N Position */
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292 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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294 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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295 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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297 #define APSR_C_Pos 29U /*!< APSR: C Position */
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298 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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300 #define APSR_V_Pos 28U /*!< APSR: V Position */
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301 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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303 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
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304 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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306 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
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307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
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311 \brief Union type to access the Interrupt Program Status Register (IPSR).
\r
317 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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318 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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319 } b; /*!< Structure used for bit access */
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320 uint32_t w; /*!< Type used for word access */
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323 /* IPSR Register Definitions */
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324 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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329 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
\r
335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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336 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
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337 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
\r
338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
340 uint32_t T:1; /*!< bit: 24 Thumb bit */
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341 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
\r
342 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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343 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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344 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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345 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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346 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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347 } b; /*!< Structure used for bit access */
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348 uint32_t w; /*!< Type used for word access */
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351 /* xPSR Register Definitions */
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352 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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353 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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355 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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358 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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359 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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361 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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362 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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364 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
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365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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367 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
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368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
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370 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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371 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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373 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
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374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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376 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
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377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
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379 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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384 \brief Union type to access the Control Registers (CONTROL).
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390 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
\r
391 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
\r
392 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
\r
393 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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394 } b; /*!< Structure used for bit access */
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395 uint32_t w; /*!< Type used for word access */
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398 /* CONTROL Register Definitions */
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399 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
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400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
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402 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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405 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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408 /*@} end of group CMSIS_CORE */
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412 \ingroup CMSIS_core_register
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413 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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414 \brief Type definitions for the NVIC Registers
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419 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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423 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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424 uint32_t RESERVED0[24U];
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425 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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426 uint32_t RSERVED1[24U];
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427 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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428 uint32_t RESERVED2[24U];
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429 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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430 uint32_t RESERVED3[24U];
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431 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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432 uint32_t RESERVED4[56U];
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433 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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434 uint32_t RESERVED5[644U];
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435 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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438 /* Software Triggered Interrupt Register Definitions */
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439 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
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440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
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442 /*@} end of group CMSIS_NVIC */
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446 \ingroup CMSIS_core_register
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447 \defgroup CMSIS_SCB System Control Block (SCB)
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448 \brief Type definitions for the System Control Block Registers
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453 \brief Structure type to access the System Control Block (SCB).
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457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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458 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
459 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
460 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
461 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
462 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
463 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
464 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
465 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
466 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
\r
467 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
468 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
\r
469 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
\r
470 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
471 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
\r
472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
473 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
474 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
475 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
\r
476 uint32_t RESERVED0[1U];
\r
477 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
\r
478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
\r
479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
\r
480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
\r
481 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
\r
482 uint32_t RESERVED3[93U];
\r
483 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
\r
484 uint32_t RESERVED4[15U];
\r
485 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
\r
486 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
\r
487 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
\r
488 uint32_t RESERVED5[1U];
\r
489 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
\r
490 uint32_t RESERVED6[1U];
\r
491 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
\r
492 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
\r
493 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
\r
494 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
\r
495 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
\r
496 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
\r
497 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
\r
498 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
\r
499 uint32_t RESERVED7[6U];
\r
500 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
\r
501 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
\r
502 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
\r
503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
\r
504 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
\r
505 uint32_t RESERVED8[1U];
\r
506 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
\r
509 /* SCB CPUID Register Definitions */
\r
510 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
\r
511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
513 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
\r
514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
516 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
\r
517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
519 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
\r
520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
522 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
\r
523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
\r
525 /* SCB Interrupt Control State Register Definitions */
\r
526 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
\r
527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
\r
529 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
\r
530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
532 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
\r
533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
535 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
\r
536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
538 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
\r
539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
541 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
\r
542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
544 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
\r
545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
547 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
\r
548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
550 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
\r
551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
553 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
\r
554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
556 /* SCB Vector Table Offset Register Definitions */
\r
557 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
\r
558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
560 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
561 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
\r
562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
567 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
\r
568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
570 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
\r
571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
\r
574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
579 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
\r
580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
\r
582 /* SCB System Control Register Definitions */
\r
583 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
\r
584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
586 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
\r
587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
589 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
\r
590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
592 /* SCB Configuration Control Register Definitions */
\r
593 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
\r
594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
\r
596 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
\r
597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
\r
599 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
\r
600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
\r
602 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
\r
603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
605 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
\r
606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
608 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
\r
609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
611 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
\r
612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
614 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
\r
615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
617 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
\r
618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
620 /* SCB System Handler Control and State Register Definitions */
\r
621 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
\r
622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
\r
625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
\r
628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
\r
631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
642 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
\r
643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
645 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
\r
646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
648 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
\r
649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
651 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
\r
652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
654 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
\r
655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
\r
658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
\r
661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
663 /* SCB Configurable Fault Status Register Definitions */
\r
664 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
\r
665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
667 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
\r
668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
670 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
\r
674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
\r
675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
\r
677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
\r
678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
\r
680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
\r
681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
\r
683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
\r
684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
\r
686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
\r
687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
\r
689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
\r
690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
\r
692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
\r
693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
\r
694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
\r
696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
\r
697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
\r
699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
\r
700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
\r
702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
\r
703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
\r
705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
\r
706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
\r
708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
\r
709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
\r
711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
\r
712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
\r
714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
\r
715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
\r
716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
\r
718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
\r
719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
\r
721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
\r
722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
\r
724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
\r
725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
\r
727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
\r
728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
\r
730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
\r
731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
\r
733 /* SCB Hard Fault Status Register Definitions */
\r
734 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
\r
735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
737 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
\r
738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
740 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
\r
741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
743 /* SCB Debug Fault Status Register Definitions */
\r
744 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
\r
745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
747 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
\r
748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
750 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
\r
751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
753 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
\r
754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
756 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
\r
757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
\r
759 /* SCB Cache Level ID Register Definitions */
\r
760 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
\r
761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
\r
763 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
\r
764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
\r
766 /* SCB Cache Type Register Definitions */
\r
767 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
\r
768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
\r
770 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
\r
771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
\r
773 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
\r
774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
\r
776 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
\r
777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
\r
779 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
\r
780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
\r
782 /* SCB Cache Size ID Register Definitions */
\r
783 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
\r
784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
\r
786 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
\r
787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
\r
789 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
\r
790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
\r
792 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
\r
793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
\r
795 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
\r
796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
\r
798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
\r
799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
\r
801 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
\r
802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
\r
804 /* SCB Cache Size Selection Register Definitions */
\r
805 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
\r
806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
\r
808 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
\r
809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
\r
811 /* SCB Software Triggered Interrupt Register Definitions */
\r
812 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
\r
813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
\r
815 /* SCB D-Cache Invalidate by Set-way Register Definitions */
\r
816 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
\r
817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
\r
819 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
\r
820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
\r
822 /* SCB D-Cache Clean by Set-way Register Definitions */
\r
823 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
\r
824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
\r
826 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
\r
827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
\r
829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
\r
830 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
\r
831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
\r
833 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
\r
834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
\r
836 /* Instruction Tightly-Coupled Memory Control Register Definitions */
\r
837 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
\r
838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
\r
840 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
\r
841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
\r
843 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
\r
844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
\r
846 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
\r
847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
\r
849 /* Data Tightly-Coupled Memory Control Register Definitions */
\r
850 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
\r
851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
\r
853 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
\r
854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
\r
856 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
\r
857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
\r
859 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
\r
860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
\r
862 /* AHBP Control Register Definitions */
\r
863 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
\r
864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
\r
866 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
\r
867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
\r
869 /* L1 Cache Control Register Definitions */
\r
870 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
\r
871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
\r
873 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
\r
874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
\r
876 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
\r
877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
\r
879 /* AHBS Control Register Definitions */
\r
880 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
\r
881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
\r
883 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
\r
884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
\r
886 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
\r
887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
\r
889 /* Auxiliary Bus Fault Status Register Definitions */
\r
890 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
\r
891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
\r
893 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
\r
894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
\r
896 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
\r
897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
\r
899 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
\r
900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
\r
902 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
\r
903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
\r
905 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
\r
906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
\r
908 /*@} end of group CMSIS_SCB */
\r
912 \ingroup CMSIS_core_register
\r
913 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\r
914 \brief Type definitions for the System Control and ID Register not in the SCB
\r
919 \brief Structure type to access the System Control and ID Register not in the SCB.
\r
923 uint32_t RESERVED0[1U];
\r
924 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
\r
925 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
928 /* Interrupt Controller Type Register Definitions */
\r
929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
\r
930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
\r
932 /* Auxiliary Control Register Definitions */
\r
933 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
\r
934 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
\r
936 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
\r
937 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
\r
939 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
\r
940 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
\r
942 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
\r
943 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
\r
945 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
\r
946 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
\r
948 /*@} end of group CMSIS_SCnotSCB */
\r
952 \ingroup CMSIS_core_register
\r
953 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
954 \brief Type definitions for the System Timer Registers.
\r
959 \brief Structure type to access the System Timer (SysTick).
\r
963 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
964 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
965 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
966 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
969 /* SysTick Control / Status Register Definitions */
\r
970 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
\r
971 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
973 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
\r
974 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
976 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
\r
977 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
979 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
\r
980 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
982 /* SysTick Reload Register Definitions */
\r
983 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
\r
984 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
986 /* SysTick Current Register Definitions */
\r
987 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
\r
988 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
990 /* SysTick Calibration Register Definitions */
\r
991 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
\r
992 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
994 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
\r
995 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
997 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
\r
998 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
1000 /*@} end of group CMSIS_SysTick */
\r
1004 \ingroup CMSIS_core_register
\r
1005 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\r
1006 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
\r
1011 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
1017 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
1018 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
1019 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
1020 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
1021 uint32_t RESERVED0[864U];
\r
1022 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
\r
1023 uint32_t RESERVED1[15U];
\r
1024 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
\r
1025 uint32_t RESERVED2[15U];
\r
1026 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
\r
1027 uint32_t RESERVED3[29U];
\r
1028 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
\r
1029 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
\r
1030 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
\r
1031 uint32_t RESERVED4[43U];
\r
1032 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
\r
1033 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
\r
1034 uint32_t RESERVED5[6U];
\r
1035 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
\r
1036 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
\r
1037 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
\r
1038 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
\r
1039 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
\r
1040 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
\r
1041 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
\r
1042 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
\r
1043 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
\r
1044 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
\r
1045 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
\r
1046 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
\r
1049 /* ITM Trace Privilege Register Definitions */
\r
1050 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
\r
1051 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
\r
1053 /* ITM Trace Control Register Definitions */
\r
1054 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
\r
1055 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
1057 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
\r
1058 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
\r
1060 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
\r
1061 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
\r
1063 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
\r
1064 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
\r
1066 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
\r
1067 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
1069 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
\r
1070 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
1072 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
\r
1073 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
1075 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
\r
1076 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
1078 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
\r
1079 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
\r
1081 /* ITM Integration Write Register Definitions */
\r
1082 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
\r
1083 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
\r
1085 /* ITM Integration Read Register Definitions */
\r
1086 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
\r
1087 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
\r
1089 /* ITM Integration Mode Control Register Definitions */
\r
1090 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
\r
1091 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
\r
1093 /* ITM Lock Status Register Definitions */
\r
1094 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
\r
1095 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
1097 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
\r
1098 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
1100 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
\r
1101 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
\r
1103 /*@}*/ /* end of group CMSIS_ITM */
\r
1107 \ingroup CMSIS_core_register
\r
1108 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
1109 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
1114 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
1118 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
1119 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
\r
1120 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
\r
1121 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
\r
1122 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
\r
1123 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
\r
1124 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
\r
1125 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
1126 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
1127 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
\r
1128 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
1129 uint32_t RESERVED0[1U];
\r
1130 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
1131 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
\r
1132 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
1133 uint32_t RESERVED1[1U];
\r
1134 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
1135 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
\r
1136 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
1137 uint32_t RESERVED2[1U];
\r
1138 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
1139 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
\r
1140 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
1141 uint32_t RESERVED3[981U];
\r
1142 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
\r
1143 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
\r
1146 /* DWT Control Register Definitions */
\r
1147 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
\r
1148 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
1150 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
\r
1151 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
1153 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
\r
1154 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
1156 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
\r
1157 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
1159 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
\r
1160 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
1162 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
\r
1163 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
\r
1165 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
\r
1166 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
\r
1168 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
\r
1169 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
\r
1171 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
\r
1172 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
\r
1174 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
\r
1175 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
\r
1177 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
\r
1178 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
\r
1180 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
\r
1181 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
\r
1183 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
\r
1184 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
\r
1186 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
\r
1187 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
\r
1189 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
\r
1190 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
\r
1192 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
\r
1193 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
\r
1195 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
\r
1196 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
\r
1198 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
\r
1199 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
\r
1201 /* DWT CPI Count Register Definitions */
\r
1202 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
\r
1203 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
\r
1205 /* DWT Exception Overhead Count Register Definitions */
\r
1206 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
\r
1207 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
\r
1209 /* DWT Sleep Count Register Definitions */
\r
1210 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
\r
1211 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
\r
1213 /* DWT LSU Count Register Definitions */
\r
1214 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
\r
1215 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
\r
1217 /* DWT Folded-instruction Count Register Definitions */
\r
1218 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
\r
1219 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
\r
1221 /* DWT Comparator Mask Register Definitions */
\r
1222 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
\r
1223 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
\r
1225 /* DWT Comparator Function Register Definitions */
\r
1226 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
\r
1227 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
1229 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
\r
1230 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
\r
1232 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
\r
1233 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
\r
1235 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
\r
1236 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
1238 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
\r
1239 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
\r
1241 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
\r
1242 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
\r
1244 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
\r
1245 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
\r
1247 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
\r
1248 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
\r
1250 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
\r
1251 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
\r
1253 /*@}*/ /* end of group CMSIS_DWT */
\r
1257 \ingroup CMSIS_core_register
\r
1258 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
1259 \brief Type definitions for the Trace Port Interface (TPI)
\r
1264 \brief Structure type to access the Trace Port Interface Register (TPI).
\r
1268 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
1269 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
1270 uint32_t RESERVED0[2U];
\r
1271 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
1272 uint32_t RESERVED1[55U];
\r
1273 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
1274 uint32_t RESERVED2[131U];
\r
1275 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
1276 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
1277 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
1278 uint32_t RESERVED3[759U];
\r
1279 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
1280 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
1281 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
1282 uint32_t RESERVED4[1U];
\r
1283 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
1284 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
1285 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
1286 uint32_t RESERVED5[39U];
\r
1287 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
1288 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
1289 uint32_t RESERVED7[8U];
\r
1290 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
1291 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
1294 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
1295 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
\r
1296 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
1298 /* TPI Selected Pin Protocol Register Definitions */
\r
1299 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
\r
1300 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
1302 /* TPI Formatter and Flush Status Register Definitions */
\r
1303 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
\r
1304 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
1306 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
\r
1307 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
1309 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
\r
1310 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
1312 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
\r
1313 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
1315 /* TPI Formatter and Flush Control Register Definitions */
\r
1316 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
\r
1317 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
1319 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
\r
1320 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
1322 /* TPI TRIGGER Register Definitions */
\r
1323 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
\r
1324 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
1326 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
1327 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
\r
1328 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
1330 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
\r
1331 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
1333 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
\r
1334 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
1336 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
\r
1337 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
1339 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
\r
1340 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
1342 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
\r
1343 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
1345 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
\r
1346 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
\r
1348 /* TPI ITATBCTR2 Register Definitions */
\r
1349 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
\r
1350 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
1352 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
1353 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
\r
1354 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
1356 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
\r
1357 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
1359 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
\r
1360 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
1362 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
\r
1363 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
1365 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
\r
1366 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
1368 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
\r
1369 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
1371 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
\r
1372 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
\r
1374 /* TPI ITATBCTR0 Register Definitions */
\r
1375 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
\r
1376 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
1378 /* TPI Integration Mode Control Register Definitions */
\r
1379 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
\r
1380 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
1382 /* TPI DEVID Register Definitions */
\r
1383 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
\r
1384 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
1386 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
\r
1387 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
1389 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
\r
1390 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
1392 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
\r
1393 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
1395 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
\r
1396 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
1398 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
\r
1399 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
1401 /* TPI DEVTYPE Register Definitions */
\r
1402 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
\r
1403 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
1405 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
\r
1406 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
1408 /*@}*/ /* end of group CMSIS_TPI */
\r
1411 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1413 \ingroup CMSIS_core_register
\r
1414 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
1415 \brief Type definitions for the Memory Protection Unit (MPU)
\r
1420 \brief Structure type to access the Memory Protection Unit (MPU).
\r
1424 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
1425 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
1426 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
1427 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
1428 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
1429 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
\r
1430 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
\r
1431 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
\r
1432 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
\r
1433 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
\r
1434 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
\r
1437 /* MPU Type Register Definitions */
\r
1438 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
\r
1439 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
1441 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
\r
1442 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
1444 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
\r
1445 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
1447 /* MPU Control Register Definitions */
\r
1448 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
\r
1449 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
1451 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
\r
1452 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
1454 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
\r
1455 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
1457 /* MPU Region Number Register Definitions */
\r
1458 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
\r
1459 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
1461 /* MPU Region Base Address Register Definitions */
\r
1462 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
\r
1463 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
1465 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
\r
1466 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
1468 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
\r
1469 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
\r
1471 /* MPU Region Attribute and Size Register Definitions */
\r
1472 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
\r
1473 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
\r
1475 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
\r
1476 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
\r
1478 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
\r
1479 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
\r
1481 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
\r
1482 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
\r
1484 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
\r
1485 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
\r
1487 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
\r
1488 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
\r
1490 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
\r
1491 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
\r
1493 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
\r
1494 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
1496 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
\r
1497 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
1499 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
\r
1500 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
\r
1502 /*@} end of group CMSIS_MPU */
\r
1503 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
\r
1507 \ingroup CMSIS_core_register
\r
1508 \defgroup CMSIS_FPU Floating Point Unit (FPU)
\r
1509 \brief Type definitions for the Floating Point Unit (FPU)
\r
1514 \brief Structure type to access the Floating Point Unit (FPU).
\r
1518 uint32_t RESERVED0[1U];
\r
1519 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
\r
1520 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
\r
1521 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
\r
1522 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
\r
1523 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
\r
1524 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
\r
1527 /* Floating-Point Context Control Register Definitions */
\r
1528 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
\r
1529 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
\r
1531 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
\r
1532 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
\r
1534 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
\r
1535 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
\r
1537 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
\r
1538 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
\r
1540 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
\r
1541 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
\r
1543 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
\r
1544 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
\r
1546 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
\r
1547 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
\r
1549 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
\r
1550 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
\r
1552 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
\r
1553 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
\r
1555 /* Floating-Point Context Address Register Definitions */
\r
1556 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
\r
1557 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
\r
1559 /* Floating-Point Default Status Control Register Definitions */
\r
1560 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
\r
1561 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
\r
1563 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
\r
1564 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
\r
1566 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
\r
1567 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
\r
1569 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
\r
1570 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
\r
1572 /* Media and FP Feature Register 0 Definitions */
\r
1573 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
\r
1574 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
\r
1576 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
\r
1577 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
\r
1579 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
\r
1580 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
\r
1582 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
\r
1583 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
\r
1585 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
\r
1586 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
\r
1588 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
\r
1589 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
\r
1591 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
\r
1592 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
\r
1594 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
\r
1595 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
\r
1597 /* Media and FP Feature Register 1 Definitions */
\r
1598 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
\r
1599 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
\r
1601 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
\r
1602 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
\r
1604 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
\r
1605 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
\r
1607 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
\r
1608 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
\r
1610 /* Media and FP Feature Register 2 Definitions */
\r
1612 /*@} end of group CMSIS_FPU */
\r
1616 \ingroup CMSIS_core_register
\r
1617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1618 \brief Type definitions for the Core Debug Registers
\r
1623 \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1627 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1628 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1629 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1630 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1633 /* Debug Halting Control and Status Register Definitions */
\r
1634 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1635 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1637 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1638 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1640 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1641 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1643 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1644 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1646 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1647 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1649 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
\r
1650 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1652 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1653 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1655 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
1656 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
1658 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1659 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1661 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
\r
1662 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1664 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
\r
1665 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1667 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1668 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1670 /* Debug Core Register Selector Register Definitions */
\r
1671 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
\r
1672 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1674 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
\r
1675 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1677 /* Debug Exception and Monitor Control Register Definitions */
\r
1678 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
\r
1679 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
1681 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
\r
1682 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
1684 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
\r
1685 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
1687 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
\r
1688 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
1690 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
\r
1691 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
1693 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1694 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1696 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
1697 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
1699 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
1700 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
1702 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
1703 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
1705 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
1706 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
1708 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
1709 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
1711 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
1712 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
1714 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1715 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1717 /*@} end of group CMSIS_CoreDebug */
\r
1721 \ingroup CMSIS_core_register
\r
1722 \defgroup CMSIS_core_bitfield Core register bit field macros
\r
1723 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
\r
1728 \brief Mask and shift a bit field value for use in a register bit range.
\r
1729 \param[in] field Name of the register bit field.
\r
1730 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\r
1731 \return Masked and shifted value.
\r
1733 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
\r
1736 \brief Mask and shift a register value to extract a bit filed value.
\r
1737 \param[in] field Name of the register bit field.
\r
1738 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\r
1739 \return Masked and shifted bit field value.
\r
1741 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
\r
1743 /*@} end of group CMSIS_core_bitfield */
\r
1747 \ingroup CMSIS_core_register
\r
1748 \defgroup CMSIS_core_base Core Definitions
\r
1749 \brief Definitions for base addresses, unions, and structures.
\r
1753 /* Memory mapping of Core Hardware */
\r
1754 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1755 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
1756 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1757 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1758 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1759 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1760 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1761 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1763 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
\r
1764 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1765 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1766 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1767 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
\r
1768 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1769 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1770 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
\r
1772 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1773 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1774 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1777 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
\r
1778 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
\r
1784 /*******************************************************************************
\r
1785 * Hardware Abstraction Layer
\r
1786 Core Function Interface contains:
\r
1787 - Core NVIC Functions
\r
1788 - Core SysTick Functions
\r
1789 - Core Debug Functions
\r
1790 - Core Register Access Functions
\r
1791 ******************************************************************************/
\r
1793 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1798 /* ########################## NVIC functions #################################### */
\r
1800 \ingroup CMSIS_Core_FunctionInterface
\r
1801 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1802 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1806 #ifdef CMSIS_NVIC_VIRTUAL
\r
1807 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1808 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
\r
1810 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
\r
1812 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
\r
1813 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
\r
1814 #define NVIC_EnableIRQ __NVIC_EnableIRQ
\r
1815 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
\r
1816 #define NVIC_DisableIRQ __NVIC_DisableIRQ
\r
1817 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
\r
1818 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
\r
1819 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
\r
1820 #define NVIC_GetActive __NVIC_GetActive
\r
1821 #define NVIC_SetPriority __NVIC_SetPriority
\r
1822 #define NVIC_GetPriority __NVIC_GetPriority
\r
1823 #define NVIC_SystemReset __NVIC_SystemReset
\r
1824 #endif /* CMSIS_NVIC_VIRTUAL */
\r
1826 #ifdef CMSIS_VECTAB_VIRTUAL
\r
1827 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1828 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
\r
1830 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
\r
1832 #define NVIC_SetVector __NVIC_SetVector
\r
1833 #define NVIC_GetVector __NVIC_GetVector
\r
1834 #endif /* (CMSIS_VECTAB_VIRTUAL) */
\r
1836 #define NVIC_USER_IRQ_OFFSET 16
\r
1841 \brief Set Priority Grouping
\r
1842 \details Sets the priority grouping field using the required unlock sequence.
\r
1843 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
1844 Only values from 0..7 are used.
\r
1845 In case of a conflict between priority grouping and available
\r
1846 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1847 \param [in] PriorityGroup Priority grouping field.
\r
1849 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
1851 uint32_t reg_value;
\r
1852 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1854 reg_value = SCB->AIRCR; /* read old register configuration */
\r
1855 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
\r
1856 reg_value = (reg_value |
\r
1857 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
1858 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
\r
1859 SCB->AIRCR = reg_value;
\r
1864 \brief Get Priority Grouping
\r
1865 \details Reads the priority grouping field from the NVIC Interrupt Controller.
\r
1866 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
\r
1868 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
\r
1870 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
\r
1875 \brief Enable Interrupt
\r
1876 \details Enables a device specific interrupt in the NVIC interrupt controller.
\r
1877 \param [in] IRQn Device specific interrupt number.
\r
1878 \note IRQn must not be negative.
\r
1880 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1882 if ((int32_t)(IRQn) >= 0)
\r
1884 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1890 \brief Get Interrupt Enable status
\r
1891 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\r
1892 \param [in] IRQn Device specific interrupt number.
\r
1893 \return 0 Interrupt is not enabled.
\r
1894 \return 1 Interrupt is enabled.
\r
1895 \note IRQn must not be negative.
\r
1897 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
\r
1899 if ((int32_t)(IRQn) >= 0)
\r
1901 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1911 \brief Disable Interrupt
\r
1912 \details Disables a device specific interrupt in the NVIC interrupt controller.
\r
1913 \param [in] IRQn Device specific interrupt number.
\r
1914 \note IRQn must not be negative.
\r
1916 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1918 if ((int32_t)(IRQn) >= 0)
\r
1920 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1928 \brief Get Pending Interrupt
\r
1929 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\r
1930 \param [in] IRQn Device specific interrupt number.
\r
1931 \return 0 Interrupt status is not pending.
\r
1932 \return 1 Interrupt status is pending.
\r
1933 \note IRQn must not be negative.
\r
1935 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1937 if ((int32_t)(IRQn) >= 0)
\r
1939 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1949 \brief Set Pending Interrupt
\r
1950 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\r
1951 \param [in] IRQn Device specific interrupt number.
\r
1952 \note IRQn must not be negative.
\r
1954 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1956 if ((int32_t)(IRQn) >= 0)
\r
1958 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1964 \brief Clear Pending Interrupt
\r
1965 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\r
1966 \param [in] IRQn Device specific interrupt number.
\r
1967 \note IRQn must not be negative.
\r
1969 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1971 if ((int32_t)(IRQn) >= 0)
\r
1973 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1979 \brief Get Active Interrupt
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1980 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\r
1981 \param [in] IRQn Device specific interrupt number.
\r
1982 \return 0 Interrupt status is not active.
\r
1983 \return 1 Interrupt status is active.
\r
1984 \note IRQn must not be negative.
\r
1986 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\r
1988 if ((int32_t)(IRQn) >= 0)
\r
1990 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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2000 \brief Set Interrupt Priority
\r
2001 \details Sets the priority of a device specific interrupt or a processor exception.
\r
2002 The interrupt number can be positive to specify a device specific interrupt,
\r
2003 or negative to specify a processor exception.
\r
2004 \param [in] IRQn Interrupt number.
\r
2005 \param [in] priority Priority to set.
\r
2006 \note The priority cannot be set for every processor exception.
\r
2008 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
2010 if ((int32_t)(IRQn) >= 0)
\r
2012 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2016 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
2022 \brief Get Interrupt Priority
\r
2023 \details Reads the priority of a device specific interrupt or a processor exception.
\r
2024 The interrupt number can be positive to specify a device specific interrupt,
\r
2025 or negative to specify a processor exception.
\r
2026 \param [in] IRQn Interrupt number.
\r
2027 \return Interrupt Priority.
\r
2028 Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
2030 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\r
2033 if ((int32_t)(IRQn) >= 0)
\r
2035 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
\r
2039 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
\r
2045 \brief Encode Priority
\r
2046 \details Encodes the priority for an interrupt with the given priority group,
\r
2047 preemptive priority value, and subpriority value.
\r
2048 In case of a conflict between priority grouping and available
\r
2049 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
2050 \param [in] PriorityGroup Used priority group.
\r
2051 \param [in] PreemptPriority Preemptive priority value (starting from 0).
\r
2052 \param [in] SubPriority Subpriority value (starting from 0).
\r
2053 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
\r
2055 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
2057 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2058 uint32_t PreemptPriorityBits;
\r
2059 uint32_t SubPriorityBits;
\r
2061 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
2062 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
2065 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
\r
2066 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
\r
2072 \brief Decode Priority
\r
2073 \details Decodes an interrupt priority value with a given priority group to
\r
2074 preemptive priority value and subpriority value.
\r
2075 In case of a conflict between priority grouping and available
\r
2076 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
2077 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\r
2078 \param [in] PriorityGroup Used priority group.
\r
2079 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\r
2080 \param [out] pSubPriority Subpriority value (starting from 0).
\r
2082 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
\r
2084 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
2085 uint32_t PreemptPriorityBits;
\r
2086 uint32_t SubPriorityBits;
\r
2088 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
2089 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
2091 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
\r
2092 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
\r
2097 \brief Set Interrupt Vector
\r
2098 \details Sets an interrupt vector in SRAM based interrupt vector table.
\r
2099 The interrupt number can be positive to specify a device specific interrupt,
\r
2100 or negative to specify a processor exception.
\r
2101 VTOR must been relocated to SRAM before.
\r
2102 \param [in] IRQn Interrupt number
\r
2103 \param [in] vector Address of interrupt handler function
\r
2105 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\r
2107 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
2108 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
\r
2113 \brief Get Interrupt Vector
\r
2114 \details Reads an interrupt vector from interrupt vector table.
\r
2115 The interrupt number can be positive to specify a device specific interrupt,
\r
2116 or negative to specify a processor exception.
\r
2117 \param [in] IRQn Interrupt number.
\r
2118 \return Address of interrupt handler function
\r
2120 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
\r
2122 uint32_t *vectors = (uint32_t *)SCB->VTOR;
\r
2123 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
\r
2128 \brief System Reset
\r
2129 \details Initiates a system reset request to reset the MCU.
\r
2131 __STATIC_INLINE void __NVIC_SystemReset(void)
\r
2133 __DSB(); /* Ensure all outstanding memory accesses included
\r
2134 buffered write are completed before reset */
\r
2135 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
2136 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
\r
2137 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
\r
2138 __DSB(); /* Ensure completion of memory access */
\r
2140 for(;;) /* wait until reset */
\r
2146 /*@} end of CMSIS_Core_NVICFunctions */
\r
2148 /* ########################## MPU functions #################################### */
\r
2150 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
2152 #include "mpu_armv7.h"
\r
2156 /* ########################## FPU functions #################################### */
\r
2158 \ingroup CMSIS_Core_FunctionInterface
\r
2159 \defgroup CMSIS_Core_FpuFunctions FPU Functions
\r
2160 \brief Function that provides FPU type.
\r
2165 \brief get FPU type
\r
2166 \details returns the FPU type
\r
2169 - \b 1: Single precision FPU
\r
2170 - \b 2: Double + Single precision FPU
\r
2172 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
\r
2176 mvfr0 = SCB->MVFR0;
\r
2177 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
\r
2179 return 2U; /* Double + Single precision FPU */
\r
2181 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
\r
2183 return 1U; /* Single precision FPU */
\r
2187 return 0U; /* No FPU */
\r
2192 /*@} end of CMSIS_Core_FpuFunctions */
\r
2196 /* ########################## Cache functions #################################### */
\r
2198 \ingroup CMSIS_Core_FunctionInterface
\r
2199 \defgroup CMSIS_Core_CacheFunctions Cache Functions
\r
2200 \brief Functions that configure Instruction and Data cache.
\r
2204 /* Cache Size ID Register Macros */
\r
2205 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
\r
2206 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
\r
2210 \brief Enable I-Cache
\r
2211 \details Turns on I-Cache
\r
2213 __STATIC_INLINE void SCB_EnableICache (void)
\r
2215 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
\r
2218 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
\r
2221 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
\r
2229 \brief Disable I-Cache
\r
2230 \details Turns off I-Cache
\r
2232 __STATIC_INLINE void SCB_DisableICache (void)
\r
2234 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
\r
2237 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
\r
2238 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
\r
2246 \brief Invalidate I-Cache
\r
2247 \details Invalidates I-Cache
\r
2249 __STATIC_INLINE void SCB_InvalidateICache (void)
\r
2251 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
\r
2254 SCB->ICIALLU = 0UL;
\r
2262 \brief Enable D-Cache
\r
2263 \details Turns on D-Cache
\r
2265 __STATIC_INLINE void SCB_EnableDCache (void)
\r
2267 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2272 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
\r
2275 ccsidr = SCB->CCSIDR;
\r
2277 /* invalidate D-Cache */
\r
2278 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2280 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2282 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
\r
2283 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
\r
2284 #if defined ( __CC_ARM )
\r
2285 __schedule_barrier();
\r
2287 } while (ways-- != 0U);
\r
2288 } while(sets-- != 0U);
\r
2291 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
\r
2300 \brief Disable D-Cache
\r
2301 \details Turns off D-Cache
\r
2303 __STATIC_INLINE void SCB_DisableDCache (void)
\r
2305 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2306 register uint32_t ccsidr;
\r
2307 register uint32_t sets;
\r
2308 register uint32_t ways;
\r
2310 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
\r
2313 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
\r
2316 ccsidr = SCB->CCSIDR;
\r
2318 /* clean & invalidate D-Cache */
\r
2319 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2321 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2323 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
\r
2324 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
\r
2325 #if defined ( __CC_ARM )
\r
2326 __schedule_barrier();
\r
2328 } while (ways-- != 0U);
\r
2329 } while(sets-- != 0U);
\r
2338 \brief Invalidate D-Cache
\r
2339 \details Invalidates D-Cache
\r
2341 __STATIC_INLINE void SCB_InvalidateDCache (void)
\r
2343 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2348 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
\r
2351 ccsidr = SCB->CCSIDR;
\r
2353 /* invalidate D-Cache */
\r
2354 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2356 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2358 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
\r
2359 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
\r
2360 #if defined ( __CC_ARM )
\r
2361 __schedule_barrier();
\r
2363 } while (ways-- != 0U);
\r
2364 } while(sets-- != 0U);
\r
2373 \brief Clean D-Cache
\r
2374 \details Cleans D-Cache
\r
2376 __STATIC_INLINE void SCB_CleanDCache (void)
\r
2378 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2383 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
\r
2386 ccsidr = SCB->CCSIDR;
\r
2388 /* clean D-Cache */
\r
2389 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2391 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2393 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
\r
2394 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
\r
2395 #if defined ( __CC_ARM )
\r
2396 __schedule_barrier();
\r
2398 } while (ways-- != 0U);
\r
2399 } while(sets-- != 0U);
\r
2408 \brief Clean & Invalidate D-Cache
\r
2409 \details Cleans and Invalidates D-Cache
\r
2411 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
\r
2413 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2418 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
\r
2421 ccsidr = SCB->CCSIDR;
\r
2423 /* clean & invalidate D-Cache */
\r
2424 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2426 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2428 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
\r
2429 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
\r
2430 #if defined ( __CC_ARM )
\r
2431 __schedule_barrier();
\r
2433 } while (ways-- != 0U);
\r
2434 } while(sets-- != 0U);
\r
2443 \brief D-Cache Invalidate by address
\r
2444 \details Invalidates D-Cache for the given address
\r
2445 \param[in] addr address (aligned to 32-byte boundary)
\r
2446 \param[in] dsize size of memory block (in number of bytes)
\r
2448 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2450 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2451 int32_t op_size = dsize;
\r
2452 uint32_t op_addr = (uint32_t)addr;
\r
2453 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
\r
2457 while (op_size > 0) {
\r
2458 SCB->DCIMVAC = op_addr;
\r
2459 op_addr += (uint32_t)linesize;
\r
2460 op_size -= linesize;
\r
2470 \brief D-Cache Clean by address
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2471 \details Cleans D-Cache for the given address
\r
2472 \param[in] addr address (aligned to 32-byte boundary)
\r
2473 \param[in] dsize size of memory block (in number of bytes)
\r
2475 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2477 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2478 int32_t op_size = dsize;
\r
2479 uint32_t op_addr = (uint32_t) addr;
\r
2480 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
\r
2484 while (op_size > 0) {
\r
2485 SCB->DCCMVAC = op_addr;
\r
2486 op_addr += (uint32_t)linesize;
\r
2487 op_size -= linesize;
\r
2497 \brief D-Cache Clean and Invalidate by address
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2498 \details Cleans and invalidates D_Cache for the given address
\r
2499 \param[in] addr address (aligned to 32-byte boundary)
\r
2500 \param[in] dsize size of memory block (in number of bytes)
\r
2502 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2504 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
\r
2505 int32_t op_size = dsize;
\r
2506 uint32_t op_addr = (uint32_t) addr;
\r
2507 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
\r
2511 while (op_size > 0) {
\r
2512 SCB->DCCIMVAC = op_addr;
\r
2513 op_addr += (uint32_t)linesize;
\r
2514 op_size -= linesize;
\r
2523 /*@} end of CMSIS_Core_CacheFunctions */
\r
2527 /* ################################## SysTick function ############################################ */
\r
2529 \ingroup CMSIS_Core_FunctionInterface
\r
2530 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
2531 \brief Functions that configure the System.
\r
2535 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
\r
2538 \brief System Tick Configuration
\r
2539 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
2540 Counter is in free running mode to generate periodic interrupts.
\r
2541 \param [in] ticks Number of ticks between two interrupts.
\r
2542 \return 0 Function succeeded.
\r
2543 \return 1 Function failed.
\r
2544 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
2545 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
2546 must contain a vendor-specific implementation of this function.
\r
2548 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
2550 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
\r
2552 return (1UL); /* Reload value impossible */
\r
2555 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
2556 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
2557 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
\r
2558 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
2559 SysTick_CTRL_TICKINT_Msk |
\r
2560 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
2561 return (0UL); /* Function successful */
\r
2566 /*@} end of CMSIS_Core_SysTickFunctions */
\r
2570 /* ##################################### Debug In/Output function ########################################### */
\r
2572 \ingroup CMSIS_Core_FunctionInterface
\r
2573 \defgroup CMSIS_core_DebugFunctions ITM Functions
\r
2574 \brief Functions that access the ITM debug interface.
\r
2578 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
\r
2579 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
\r
2583 \brief ITM Send Character
\r
2584 \details Transmits a character via the ITM channel 0, and
\r
2585 \li Just returns when no debugger is connected that has booked the output.
\r
2586 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\r
2587 \param [in] ch Character to transmit.
\r
2588 \returns Character to transmit.
\r
2590 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
\r
2592 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
\r
2593 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
\r
2595 while (ITM->PORT[0U].u32 == 0UL)
\r
2599 ITM->PORT[0U].u8 = (uint8_t)ch;
\r
2606 \brief ITM Receive Character
\r
2607 \details Inputs a character via the external variable \ref ITM_RxBuffer.
\r
2608 \return Received character.
\r
2609 \return -1 No character pending.
\r
2611 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
\r
2613 int32_t ch = -1; /* no character available */
\r
2615 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
\r
2617 ch = ITM_RxBuffer;
\r
2618 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
\r
2626 \brief ITM Check Character
\r
2627 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\r
2628 \return 0 No character available.
\r
2629 \return 1 Character available.
\r
2631 __STATIC_INLINE int32_t ITM_CheckChar (void)
\r
2634 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
\r
2636 return (0); /* no character available */
\r
2640 return (1); /* character available */
\r
2644 /*@} end of CMSIS_core_DebugFunctions */
\r
2649 #ifdef __cplusplus
\r
2653 #endif /* __CORE_CM7_H_DEPENDANT */
\r
2655 #endif /* __CMSIS_GENERIC */
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projects / freertos / blob