1 /**************************************************************************//**
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2 * @file efm32wg_devinfo.h
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3 * @brief EFM32WG_DEVINFO register and bit field definitions
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5 ******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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33 * @defgroup EFM32WG_DEVINFO
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35 *****************************************************************************/
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38 __I uint32_t CAL; /**< Calibration temperature and checksum */
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39 __I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
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40 __I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
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41 __I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
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42 uint32_t RESERVED0[2]; /**< Reserved */
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43 __I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
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44 __I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
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45 __I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
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46 __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
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47 __I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
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48 __I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
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49 __I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
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50 __I uint32_t MEMINFO; /**< Memory information */
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51 uint32_t RESERVED2[2]; /**< Reserved */
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52 __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
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53 __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
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54 __I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
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55 __I uint32_t PART; /**< Part description */
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56 } DEVINFO_TypeDef; /** @} */
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58 /**************************************************************************//**
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59 * @defgroup EFM32WG_DEVINFO_BitFields
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61 *****************************************************************************/
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62 /* Bit fields for EFM32WG_DEVINFO */
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63 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
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64 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
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65 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
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66 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
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67 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
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68 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
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69 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
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70 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
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71 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
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72 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
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73 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
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74 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
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75 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
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76 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
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77 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
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78 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
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79 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
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80 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
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81 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
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82 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
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83 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
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84 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
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85 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
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86 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
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87 #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
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88 #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
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89 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
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90 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
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91 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
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92 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
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93 #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
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94 #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
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95 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
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96 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
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97 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
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98 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
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99 #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
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100 #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
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101 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
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102 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
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103 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
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104 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
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105 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
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106 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
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107 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
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108 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
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109 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
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110 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
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111 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
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112 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
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113 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
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114 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
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115 #define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
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116 #define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
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117 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
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118 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
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119 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
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120 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
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121 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
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122 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
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123 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
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124 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
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125 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
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126 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
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127 #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
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128 #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
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129 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
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130 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
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131 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
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132 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
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133 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
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134 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
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135 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
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136 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
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137 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
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138 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
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139 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
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140 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
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141 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
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142 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
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143 /* Legacy family #defines */
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144 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
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145 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
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146 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
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147 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
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148 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
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149 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
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150 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
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151 /* New style family #defines */
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152 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
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153 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
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154 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
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155 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
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156 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
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157 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
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158 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
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159 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
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160 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
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161 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
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162 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
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163 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
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165 /** @} End of group EFM32WG_DEVINFO */
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