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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xnandpsu_hw.h
  36 *
  37 * This file contains identifiers and low-level macros/functions for the Arasan
  38 * NAND flash controller driver.
  39 *
  40 * See xnandpsu.h for more information.
  41 *
  42 * @note         None
  43 *
  44 * <pre>
  45 * MODIFICATION HISTORY:
  46 *
  47 * Ver   Who    Date        Changes
  48 * ----- ----   ----------  -----------------------------------------------
  49 * 1.0   nm     05/06/2014  First Release
  50 * 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
  51 *                          XNANDPSU_ECC_HAMMING_BCH_MASK.
  52 * </pre>
  53 *
  54 ******************************************************************************/
  55
  56 #ifndef XNANDPSU_HW_H           /* prevent circular inclusions */
  57 #define XNANDPSU_HW_H           /* by using protection macros */
  58
  59 #ifdef __cplusplus
  60 extern "C" {
  61 #endif
  62
  63 /***************************** Include Files *********************************/
  64 #include "xil_io.h"
  65
  66 /************************** Constant Definitions *****************************/
  67
  68 /************************** Register Offset Definitions **********************/
  69
  70 #define XNANDPSU_PKT_OFFSET             0x00U   /**< Packet Register */
  71 #define XNANDPSU_MEM_ADDR1_OFFSET       0x04U   /**< Memory Address
  72                                                   Register 1 */
  73 #define XNANDPSU_MEM_ADDR2_OFFSET       0x08U   /**< Memory Address
  74                                                   Register 2 */
  75 #define XNANDPSU_CMD_OFFSET             0x0CU   /**< Command Register */
  76 #define XNANDPSU_PROG_OFFSET            0x10U   /**< Program Register */
  77 #define XNANDPSU_INTR_STS_EN_OFFSET     0x14U   /**< Interrupt Status
  78                                                      Enable Register */
  79 #define XNANDPSU_INTR_SIG_EN_OFFSET     0x18U   /**< Interrupt Signal
  80                                                      Enable Register */
  81 #define XNANDPSU_INTR_STS_OFFSET        0x1CU   /**< Interrupt Status
  82                                                   Register */
  83 #define XNANDPSU_READY_BUSY_OFFSET      0x20U   /**< Ready/Busy status
  84                                                   Register */
  85 #define XNANDPSU_FLASH_STS_OFFSET       0x28U   /**< Flash Status Register */
  86 #define XNANDPSU_TIMING_OFFSET          0x2CU   /**< Timing Register */
  87 #define XNANDPSU_BUF_DATA_PORT_OFFSET   0x30U   /**< Buffer Data Port
  88                                                   Register */
  89 #define XNANDPSU_ECC_OFFSET             0x34U   /**< ECC Register */
  90 #define XNANDPSU_ECC_ERR_CNT_OFFSET     0x38U   /**< ECC Error Count
  91                                                   Register */
  92 #define XNANDPSU_ECC_SPR_CMD_OFFSET     0x3CU   /**< ECC Spare Command
  93                                                      Register */
  94 #define XNANDPSU_ECC_CNT_1BIT_OFFSET    0x40U   /**< Error Count 1bit
  95                                                   Register */
  96 #define XNANDPSU_ECC_CNT_2BIT_OFFSET    0x44U   /**< Error Count 2bit
  97                                                   Register */
  98 #define XNANDPSU_ECC_CNT_3BIT_OFFSET    0x48U   /**< Error Count 3bit
  99                                                   Register */
 100 #define XNANDPSU_ECC_CNT_4BIT_OFFSET    0x4CU   /**< Error Count 4bit
 101                                                   Register */
 102 #define XNANDPSU_CPU_REL_OFFSET         0x58U   /**< CPU Release Register */
 103 #define XNANDPSU_ECC_CNT_5BIT_OFFSET    0x5CU   /**< Error Count 5bit
 104                                                   Register */
 105 #define XNANDPSU_ECC_CNT_6BIT_OFFSET    0x60U   /**< Error Count 6bit
 106                                                   Register */
 107 #define XNANDPSU_ECC_CNT_7BIT_OFFSET    0x64U   /**< Error Count 7bit
 108                                                   Register */
 109 #define XNANDPSU_ECC_CNT_8BIT_OFFSET    0x68U   /**< Error Count 8bit
 110                                                   Register */
 111 #define XNANDPSU_DATA_INTF_OFFSET       0x6CU   /**< Data Interface Register */
 112 #define XNANDPSU_DMA_SYS_ADDR0_OFFSET   0x50U   /**< DMA System Address 0
 113                                                   Register */
 114 #define XNANDPSU_DMA_SYS_ADDR1_OFFSET   0x24U   /**< DMA System Address 1
 115                                                   Register */
 116 #define XNANDPSU_DMA_BUF_BND_OFFSET     0x54U   /**< DMA Buffer Boundary
 117                                                   Register */
 118 #define XNANDPSU_SLV_DMA_CONF_OFFSET    0x80U   /**< Slave DMA Configuration
 119                                                   Register */
 120
 121 /** @name Packet Register bit definitions and masks
 122  *  @{
 123  */
 124 #define XNANDPSU_PKT_PKT_SIZE_MASK              0x000007FFU /**< Packet Size */
 125 #define XNANDPSU_PKT_PKT_CNT_MASK               0x00FFF000U /**< Packet Count*/
 126 #define XNANDPSU_PKT_PKT_CNT_SHIFT              12U /**< Packet Count Shift */
 127 /* @} */
 128
 129 /** @name Memory Address Register 1 bit definitions and masks
 130  *  @{
 131  */
 132 #define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK        0x0000FFFFU /**< Column Address
 133                                                              Mask */
 134 #define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK         0xFFFF0000U /**< Page, Block
 135                                                              Address Mask */
 136 #define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT        16U /**< Page Shift */
 137 /* @} */
 138
 139 /** @name Memory Address Register 2 bit definitions and masks
 140  *  @{
 141  */
 142 #define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK        0x000000FFU /**< Memory Address
 143                                                                 */
 144 #define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK       0x01000000U /**< Bus Width */
 145 #define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK    0x0E000000U /**< BCH Mode
 146                                                              Value */
 147 #define XNANDPSU_MEM_ADDR2_MODE_MASK            0x30000000U /**< Flash
 148                                                              Connection Mode */
 149 #define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK        0xC0000000U /**< Chip Select */
 150 #define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT       30U     /**< Chip select
 151                                                         shift */
 152 #define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT      24U     /**< Bus width shift */
 153 #define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT   25U
 154 /* @} */
 155
 156 /** @name Command Register bit definitions and masks
 157  *  @{
 158  */
 159 #define XNANDPSU_CMD_CMD1_MASK                  0x000000FFU /**< 1st Cycle
 160                                                              Command */
 161 #define XNANDPSU_CMD_CMD2_MASK                  0x0000FF00U /**< 2nd Cycle
 162                                                              Command */
 163 #define XNANDPSU_CMD_PG_SIZE_MASK               0x03800000U /**< Page Size */
 164 #define XNANDPSU_CMD_DMA_EN_MASK                0x0C000000U /**< DMA Enable
 165                                                              Mode */
 166 #define XNANDPSU_CMD_ADDR_CYCLES_MASK           0x70000000U /**< Number of
 167                                                              Address Cycles */
 168 #define XNANDPSU_CMD_ECC_ON_MASK                0x80000000U /**< ECC ON/OFF */
 169 #define XNANDPSU_CMD_CMD2_SHIFT                 8U /**< 2nd Cycle Command
 170                                                     Shift */
 171 #define XNANDPSU_CMD_PG_SIZE_SHIFT              23U /**< Page Size Shift */
 172 #define XNANDPSU_CMD_DMA_EN_SHIFT               26U /**< DMA Enable Shift */
 173 #define XNANDPSU_CMD_ADDR_CYCLES_SHIFT          28U /**< Number of Address
 174                                                      Cycles Shift */
 175 #define XNANDPSU_CMD_ECC_ON_SHIFT               31U /**< ECC ON/OFF */
 176 /* @} */
 177
 178 /** @name Program Register bit definitions and masks
 179  *  @{
 180  */
 181 #define XNANDPSU_PROG_RD_MASK                   0x00000001U /**< Read */
 182 #define XNANDPSU_PROG_MUL_DIE_MASK              0x00000002U /**< Multi Die */
 183 #define XNANDPSU_PROG_BLK_ERASE_MASK            0x00000004U /**< Block Erase */
 184 #define XNANDPSU_PROG_RD_STS_MASK               0x00000008U /**< Read Status */
 185 #define XNANDPSU_PROG_PG_PROG_MASK              0x00000010U /**< Page Program */
 186 #define XNANDPSU_PROG_MUL_DIE_RD_MASK           0x00000020U /**< Multi Die Rd */
 187 #define XNANDPSU_PROG_RD_ID_MASK                0x00000040U /**< Read ID */
 188 #define XNANDPSU_PROG_RD_PRM_PG_MASK            0x00000080U /**< Read Param
 189                                                              Page */
 190 #define XNANDPSU_PROG_RST_MASK                  0x00000100U /**< Reset */
 191 #define XNANDPSU_PROG_GET_FEATURES_MASK         0x00000200U /**< Get Features */
 192 #define XNANDPSU_PROG_SET_FEATURES_MASK         0x00000400U /**< Set Features */
 193 #define XNANDPSU_PROG_RD_UNQ_ID_MASK            0x00000800U /**< Read Unique
 194                                                              ID */
 195 #define XNANDPSU_PROG_RD_STS_ENH_MASK           0x00001000U /**< Read Status
 196                                                              Enhanced */
 197 #define XNANDPSU_PROG_RD_INTRLVD_MASK           0x00002000U /**< Read
 198                                                              Interleaved */
 199 #define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK      0x00004000U /**< Change Read
 200                                                                 Column
 201                                                                 Enhanced */
 202 #define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK    0x00008000U /**< Copy Back
 203                                                                 Interleaved */
 204 #define XNANDPSU_PROG_RD_CACHE_START_MASK       0x00010000U /**< Read Cache
 205                                                              Start */
 206 #define XNANDPSU_PROG_RD_CACHE_SEQ_MASK         0x00020000U /**< Read Cache
 207                                                              Sequential */
 208 #define XNANDPSU_PROG_RD_CACHE_RAND_MASK        0x00040000U /**< Read Cache
 209                                                                 Random */
 210 #define XNANDPSU_PROG_RD_CACHE_END_MASK         0x00080000U /**< Read Cache
 211                                                              End */
 212 #define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK      0x00100000U /**< Small Data
 213                                                              Move */
 214 #define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK        0x00200000U /**< Change Row
 215                                                                 Address */
 216 #define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK    0x00400000U /**< Change Row
 217                                                                 Address End */
 218 #define XNANDPSU_PROG_RST_LUN_MASK              0x00800000U /**< Reset LUN */
 219 #define XNANDPSU_PROG_PGM_PG_CLR_MASK           0x01000000U /**< Enhanced
 220                                                              Program Page
 221                                                              Register Clear */
 222 #define XNANDPSU_PROG_VOL_SEL_MASK              0x02000000U /**< Volume Select */
 223 #define XNANDPSU_PROG_ODT_CONF_MASK             0x04000000U /**< ODT Configure */
 224 /* @} */
 225
 226 /** @name Interrupt Status Enable Register bit definitions and masks
 227  *  @{
 228  */
 229 #define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK    0x00000001U /**< Buffer
 230                                                                      Write Ready
 231                                                                      Status
 232                                                                      Enable */
 233 #define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK    0x00000002U /**< Buffer
 234                                                                      Read Ready
 235                                                                      Status
 236                                                                      Enable */
 237 #define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK     0x00000004U /**< Transfer
 238                                                                      Complete
 239                                                                      Status
 240                                                                      Enable */
 241 #define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK    0x00000008U /**< Multi
 242                                                                      Bit Error
 243                                                                      Status
 244                                                                      Enable */
 245 #define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK       0x00000010U /**< Single
 246                                                                      Bit Error
 247                                                                      Status
 248                                                                      Enable,
 249                                                                      BCH Detect
 250                                                                      Error
 251                                                                      Status
 252                                                                      Enable */
 253 #define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK        0x00000040U /**< DMA
 254                                                                      Status
 255                                                                      Enable */
 256 #define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK        0x00000080U /**< Error
 257                                                                      AHB Status
 258                                                                      Enable */
 259 /* @} */
 260
 261 /** @name Interrupt Signal Enable Register bit definitions and masks
 262  *  @{
 263  */
 264 #define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK    0x00000001U /**< Buffer
 265                                                                      Write Ready
 266                                                                      Signal
 267                                                                      Enable */
 268 #define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK    0x00000002U /**< Buffer
 269                                                                      Read Ready
 270                                                                      Signal
 271                                                                      Enable */
 272 #define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK     0x00000004U /**< Transfer
 273                                                                      Complete
 274                                                                      Signal
 275                                                                      Enable */
 276 #define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK    0x00000008U /**< Multi
 277                                                                      Bit Error
 278                                                                      Signal
 279                                                                      Enable */
 280 #define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK       0x00000010U /**< Single
 281                                                                      Bit Error
 282                                                                      Signal
 283                                                                      Enable,
 284                                                                      BCH Detect
 285                                                                      Error
 286                                                                      Signal
 287                                                                      Enable */
 288 #define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK        0x00000040U /**< DMA
 289                                                                      Signal
 290                                                                      Enable */
 291 #define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK        0x00000080U /**< Error
 292                                                                      AHB Signal
 293                                                                      Enable */
 294 /* @} */
 295
 296 /** @name Interrupt Status Register bit definitions and masks
 297  *  @{
 298  */
 299 #define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK       0x00000001U /**< Buffer
 300                                                                      Write
 301                                                                      Ready */
 302 #define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK       0x00000002U /**< Buffer
 303                                                                      Read
 304                                                                      Ready */
 305 #define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK        0x00000004U /**< Transfer
 306                                                                      Complete */
 307 #define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK       0x00000008U /**< Multi
 308                                                                     Bit Error */
 309 #define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK          0x00000010U /**< Single
 310                                                                      Bit Error,
 311                                                                      BCH Detect
 312                                                                      Error */
 313 #define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK           0x00000040U /**< DMA
 314                                                                      Interrupt
 315                                                                      */
 316 #define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK           0x00000080U /**< Error
 317                                                                      AHB */
 318 /* @} */
 319
 320 /** @name Interrupt bit definitions and masks
 321  *  @{
 322  */
 323 #define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK   0x00000001U /**< Buffer Write
 324                                                                 Ready Status
 325                                                                 Enable */
 326 #define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK   0x00000002U /**< Buffer Read
 327                                                                 Ready Status
 328                                                                 Enable */
 329 #define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK    0x00000004U /**< Transfer
 330                                                                 Complete Status
 331                                                                 Enable */
 332 #define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK   0x00000008U /**< Multi Bit Error
 333                                                                 Status Enable */
 334 #define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK      0x00000010U /**< Single Bit Error
 335                                                                 Status Enable,
 336                                                                 BCH Detect Error
 337                                                                 Status Enable */
 338 #define XNANDPSU_INTR_DMA_INT_STS_EN_MASK       0x00000040U /**< DMA Status
 339                                                                 Enable */
 340 #define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK       0x00000080U /**< Error AHB Status
 341                                                                 Enable */
 342 /* @} */
 343
 344 /** @name ID2 Register bit definitions and masks
 345  *  @{
 346  */
 347 #define XNANDPSU_ID2_DEVICE_ID2_MASK            0x000000FFU /**< MSB Device ID */
 348 /* @} */
 349
 350 /** @name Flash Status Register bit definitions and masks
 351  *  @{
 352  */
 353 #define XNANDPSU_FLASH_STS_FLASH_STS_MASK       0x0000FFFFU /**< Flash Status
 354                                                              Value */
 355 /* @} */
 356
 357 /** @name Timing Register bit definitions and masks
 358  *  @{
 359  */
 360 #define XNANDPSU_TIMING_TCCS_TIME_MASK          0x00000003U /**< Change column
 361                                                              setup time */
 362 #define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK     0x00000004U /**< Slow/Fast device
 363                                                              */
 364 #define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK       0x00000078U /**< Write/Read data
 365                                                              transaction value
 366                                                              */
 367 #define XNANDPSU_TIMING_TADL_TIME_MASK          0x00007F80U /**< Address latch
 368                                                              enable to Data
 369                                                              loading time */
 370 /* @} */
 371
 372 /** @name ECC Register bit definitions and masks
 373  *  @{
 374  */
 375 #define XNANDPSU_ECC_ADDR_MASK                  0x0000FFFFU /**< ECC address */
 376 #define XNANDPSU_ECC_SIZE_MASK                  0x01FF0000U /**< ECC size */
 377 #define XNANDPSU_ECC_HAMMING_BCH_MASK           0x02000000U /**< Hamming/BCH
 378                                                              support */
 379 /* @} */
 380
 381 /** @name ECC Error Count Register bit definitions and masks
 382  *  @{
 383  */
 384 #define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK       0x000000FFU /**< Packet
 385                                                                      bound error
 386                                                                      count */
 387 #define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK        0x0000FF00U /**< Page
 388                                                                      bound error
 389                                                                      count */
 390 /* @} */
 391
 392 /** @name ECC Spare Command Register bit definitions and masks
 393  *  @{
 394  */
 395 #define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK               0x000000FFU /**< ECC
 396                                                                      spare
 397                                                                      command */
 398 #define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK       0x70000000U /**< Number
 399                                                                      of ECC/
 400                                                                      spare
 401                                                                      address
 402                                                                      cycles */
 403 /* @} */
 404
 405 /** @name Data Interface Register bit definitions and masks
 406  *  @{
 407  */
 408 #define XNANDPSU_DATA_INTF_SDR_MASK             0x00000007U /**< SDR mode */
 409 #define XNANDPSU_DATA_INTF_NVDDR_MASK           0x00000038U /**< NVDDR mode */
 410 #define XNANDPSU_DATA_INTF_NVDDR2_MASK          0x000001C0U /**< NVDDR2 mode */
 411 #define XNANDPSU_DATA_INTF_DATA_INTF_MASK       0x00000600U /**< Data
 412                                                              Interface */
 413 #define XNANDPSU_DATA_INTF_NVDDR_SHIFT          3U /**< NVDDR mode shift */
 414 #define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT      9U /**< Data Interface Shift */
 415 /* @} */
 416
 417 /** @name DMA Buffer Boundary Register bit definitions and masks
 418  *  @{
 419  */
 420 #define XNANDPSU_DMA_BUF_BND_BND_MASK           0x00000007U /**< DMA buffer
 421                                                              boundary */
 422 #define XNANDPSU_DMA_BUF_BND_4K                 0x0U
 423 #define XNANDPSU_DMA_BUF_BND_8K                 0x1U
 424 #define XNANDPSU_DMA_BUF_BND_16K                0x2U
 425 #define XNANDPSU_DMA_BUF_BND_32K                0x3U
 426 #define XNANDPSU_DMA_BUF_BND_64K                0x4U
 427 #define XNANDPSU_DMA_BUF_BND_128K               0x5U
 428 #define XNANDPSU_DMA_BUF_BND_256K               0x6U
 429 #define XNANDPSU_DMA_BUF_BND_512K               0x7U
 430 /* @} */
 431
 432 /** @name Slave DMA Configuration Register bit definitions and masks
 433  *  @{
 434  */
 435 #define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK           0x00000001U /**< Slave
 436                                                                      DMA
 437                                                                      Transfer
 438                                                                      Direction
 439                                                                      */
 440 #define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK        0x001FFFFEU /**< Slave
 441                                                                      DMA
 442                                                                      Transfer
 443                                                                      Count */
 444 #define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK       0x00E00000U /**< Slave
 445                                                                      DMA
 446                                                                      Burst
 447                                                                      Size */
 448 #define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK    0x0F000000U /**< DMA
 449                                                                      Timeout
 450                                                                      Counter
 451                                                                      Value */
 452 #define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK              0x10000000U /**< Slave
 453                                                                      DMA
 454                                                                      Enable */
 455 /* @} */
 456
 457 /**************************** Type Definitions *******************************/
 458
 459 /***************** Macros (Inline Functions) Definitions *********************/
 460
 461 /****************************************************************************/
 462 /**
 463 *
 464 * This macro reads the given register.
 465 *
 466 * @param        BaseAddress is the base address of controller registers.
 467 * @param        RegOffset is the register offset to be read.
 468 *
 469 * @return       The 32-bit value of the register.
 470 *
 471 * @note         C-style signature:
 472 *               u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
 473 *
 474 *****************************************************************************/
 475 #define XNandPsu_ReadReg(BaseAddress, RegOffset)                        \
 476                         Xil_In32((BaseAddress) + (RegOffset))
 477
 478 /****************************************************************************/
 479 /**
 480 *
 481 * This macro writes the given register.
 482 *
 483 * @param        BaseAddress is the the base address of controller registers.
 484 * @param        RegOffset is the register offset to be written.
 485 * @param        Data is the the 32-bit value to write to the register.
 486 *
 487 * @return       None.
 488 *
 489 * @note         C-style signature:
 490 *               void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
 491 *
 492 ******************************************************************************/
 493 #define XNandPsu_WriteReg(BaseAddress, RegOffset, Data)                 \
 494                         Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
 495
 496 /************************** Function Prototypes ******************************/
 497
 498 /************************** Variable Definitions *****************************/
 499
 500 #ifdef __cplusplus
 501 }
 502 #endif
 503
 504 #endif /* XNANDPSU_HW_H end of protection macro */