1 /* Definition for CPU ID */
\r
2 #define XPAR_CPU_ID 0
\r
4 /* Definitions for peripheral PSU_CORTEXA53_0 */
\r
5 #define XPAR_PSU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014
\r
6 #define XPAR_PSU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999
\r
9 /******************************************************************/
\r
11 /* Canonical definitions for peripheral PSU_CORTEXA53_0 */
\r
12 #define XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014
\r
13 #define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999
\r
16 /******************************************************************/
\r
18 #include "xparameters_ps.h"
\r
20 #define STDIN_BASEADDRESS 0xFF000000
\r
21 #define STDOUT_BASEADDRESS 0xFF000000
\r
23 /******************************************************************/
\r
25 /* Definitions for driver AXIPMON */
\r
26 #define XPAR_XAXIPMON_NUM_INSTANCES 4
\r
28 /* Definitions for peripheral PSU_APM_0 */
\r
29 #define XPAR_PSU_APM_0_DEVICE_ID 0
\r
30 #define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000
\r
31 #define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF
\r
32 #define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32
\r
33 #define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32
\r
34 #define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1
\r
35 #define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6
\r
36 #define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10
\r
37 #define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1
\r
38 #define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0
\r
39 #define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32
\r
40 #define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56
\r
41 #define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1
\r
42 #define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1
\r
43 #define XPAR_PSU_APM_0_ENABLE_ADVANCED 1
\r
44 #define XPAR_PSU_APM_0_ENABLE_PROFILE 0
\r
45 #define XPAR_PSU_APM_0_ENABLE_TRACE 0
\r
46 #define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000
\r
47 #define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000
\r
48 #define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1
\r
51 /* Definitions for peripheral PSU_APM_1 */
\r
52 #define XPAR_PSU_APM_1_DEVICE_ID 1
\r
53 #define XPAR_PSU_APM_1_BASEADDR 0xFFA00000
\r
54 #define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF
\r
55 #define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32
\r
56 #define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32
\r
57 #define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1
\r
58 #define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1
\r
59 #define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3
\r
60 #define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1
\r
61 #define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0
\r
62 #define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32
\r
63 #define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56
\r
64 #define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1
\r
65 #define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1
\r
66 #define XPAR_PSU_APM_1_ENABLE_ADVANCED 1
\r
67 #define XPAR_PSU_APM_1_ENABLE_PROFILE 0
\r
68 #define XPAR_PSU_APM_1_ENABLE_TRACE 0
\r
69 #define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000
\r
70 #define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000
\r
71 #define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1
\r
74 /* Definitions for peripheral PSU_APM_2 */
\r
75 #define XPAR_PSU_APM_2_DEVICE_ID 2
\r
76 #define XPAR_PSU_APM_2_BASEADDR 0xFFA10000
\r
77 #define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF
\r
78 #define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32
\r
79 #define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32
\r
80 #define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1
\r
81 #define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1
\r
82 #define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3
\r
83 #define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1
\r
84 #define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0
\r
85 #define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32
\r
86 #define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56
\r
87 #define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1
\r
88 #define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1
\r
89 #define XPAR_PSU_APM_2_ENABLE_ADVANCED 1
\r
90 #define XPAR_PSU_APM_2_ENABLE_PROFILE 0
\r
91 #define XPAR_PSU_APM_2_ENABLE_TRACE 0
\r
92 #define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000
\r
93 #define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000
\r
94 #define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1
\r
97 /* Definitions for peripheral PSU_APM_5 */
\r
98 #define XPAR_PSU_APM_5_DEVICE_ID 3
\r
99 #define XPAR_PSU_APM_5_BASEADDR 0xFD490000
\r
100 #define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF
\r
101 #define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32
\r
102 #define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32
\r
103 #define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1
\r
104 #define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1
\r
105 #define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3
\r
106 #define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1
\r
107 #define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0
\r
108 #define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32
\r
109 #define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56
\r
110 #define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1
\r
111 #define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1
\r
112 #define XPAR_PSU_APM_5_ENABLE_ADVANCED 1
\r
113 #define XPAR_PSU_APM_5_ENABLE_PROFILE 0
\r
114 #define XPAR_PSU_APM_5_ENABLE_TRACE 0
\r
115 #define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000
\r
116 #define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000
\r
117 #define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1
\r
120 /******************************************************************/
\r
122 /* Canonical definitions for peripheral PSU_APM_0 */
\r
123 #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID
\r
124 #define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000
\r
125 #define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF
\r
126 #define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32
\r
127 #define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32
\r
128 #define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1
\r
129 #define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6
\r
130 #define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10
\r
131 #define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1
\r
132 #define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0
\r
133 #define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32
\r
134 #define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56
\r
135 #define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1
\r
136 #define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1
\r
137 #define XPAR_AXIPMON_0_ENABLE_ADVANCED 1
\r
138 #define XPAR_AXIPMON_0_ENABLE_PROFILE 0
\r
139 #define XPAR_AXIPMON_0_ENABLE_TRACE 0
\r
140 #define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000
\r
141 #define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000
\r
142 #define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1
\r
144 /* Canonical definitions for peripheral PSU_APM_1 */
\r
145 #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID
\r
146 #define XPAR_AXIPMON_1_BASEADDR 0xFFA00000
\r
147 #define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF
\r
148 #define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32
\r
149 #define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32
\r
150 #define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1
\r
151 #define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1
\r
152 #define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3
\r
153 #define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1
\r
154 #define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0
\r
155 #define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32
\r
156 #define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56
\r
157 #define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1
\r
158 #define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1
\r
159 #define XPAR_AXIPMON_1_ENABLE_ADVANCED 1
\r
160 #define XPAR_AXIPMON_1_ENABLE_PROFILE 0
\r
161 #define XPAR_AXIPMON_1_ENABLE_TRACE 0
\r
162 #define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000
\r
163 #define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000
\r
164 #define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1
\r
166 /* Canonical definitions for peripheral PSU_APM_2 */
\r
167 #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID
\r
168 #define XPAR_AXIPMON_2_BASEADDR 0xFFA10000
\r
169 #define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF
\r
170 #define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32
\r
171 #define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32
\r
172 #define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1
\r
173 #define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1
\r
174 #define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3
\r
175 #define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1
\r
176 #define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0
\r
177 #define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32
\r
178 #define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56
\r
179 #define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1
\r
180 #define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1
\r
181 #define XPAR_AXIPMON_2_ENABLE_ADVANCED 1
\r
182 #define XPAR_AXIPMON_2_ENABLE_PROFILE 0
\r
183 #define XPAR_AXIPMON_2_ENABLE_TRACE 0
\r
184 #define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000
\r
185 #define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000
\r
186 #define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1
\r
188 /* Canonical definitions for peripheral PSU_APM_5 */
\r
189 #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID
\r
190 #define XPAR_AXIPMON_3_BASEADDR 0xFD490000
\r
191 #define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF
\r
192 #define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32
\r
193 #define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32
\r
194 #define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1
\r
195 #define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1
\r
196 #define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3
\r
197 #define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1
\r
198 #define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0
\r
199 #define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32
\r
200 #define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56
\r
201 #define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1
\r
202 #define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1
\r
203 #define XPAR_AXIPMON_3_ENABLE_ADVANCED 1
\r
204 #define XPAR_AXIPMON_3_ENABLE_PROFILE 0
\r
205 #define XPAR_AXIPMON_3_ENABLE_TRACE 0
\r
206 #define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000
\r
207 #define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000
\r
208 #define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1
\r
211 /******************************************************************/
\r
213 /* Definitions for driver CANPS */
\r
214 #define XPAR_XCANPS_NUM_INSTANCES 1
\r
216 /* Definitions for peripheral PSU_CAN_1 */
\r
217 #define XPAR_PSU_CAN_1_DEVICE_ID 0
\r
218 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000
\r
219 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF
\r
220 #define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999
\r
223 /******************************************************************/
\r
225 /* Canonical definitions for peripheral PSU_CAN_1 */
\r
226 #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID
\r
227 #define XPAR_XCANPS_0_BASEADDR 0xFF070000
\r
228 #define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF
\r
229 #define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999
\r
232 /******************************************************************/
\r
234 /* Definitions for driver CSUDMA */
\r
235 #define XPAR_XCSUDMA_NUM_INSTANCES 1
\r
237 /* Definitions for peripheral PSU_CSUDMA */
\r
238 #define XPAR_PSU_CSUDMA_DEVICE_ID 0
\r
239 #define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000
\r
240 #define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF
\r
241 #define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0
\r
244 /******************************************************************/
\r
246 /* Canonical definitions for peripheral PSU_CSUDMA */
\r
247 #define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID
\r
248 #define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000
\r
249 #define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF
\r
250 #define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0
\r
253 /******************************************************************/
\r
255 /* Definitions for driver EMACPS */
\r
256 #define XPAR_XEMACPS_NUM_INSTANCES 1
\r
258 /* Definitions for peripheral PSU_ETHERNET_3 */
\r
259 #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
\r
260 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
\r
261 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
\r
262 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
\r
263 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
\r
264 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
\r
265 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
\r
266 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
\r
267 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
\r
268 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
\r
271 /******************************************************************/
\r
273 /* Canonical definitions for peripheral PSU_ETHERNET_3 */
\r
274 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
\r
275 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
\r
276 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
\r
277 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
\r
278 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
\r
279 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
\r
280 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
\r
281 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
\r
282 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
\r
283 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
\r
286 /******************************************************************/
\r
289 /* Definitions for peripheral PSU_AFI_0 */
\r
290 #define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000
\r
291 #define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF
\r
294 /* Definitions for peripheral PSU_AFI_1 */
\r
295 #define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000
\r
296 #define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF
\r
299 /* Definitions for peripheral PSU_AFI_2 */
\r
300 #define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000
\r
301 #define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF
\r
304 /* Definitions for peripheral PSU_AFI_3 */
\r
305 #define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000
\r
306 #define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF
\r
309 /* Definitions for peripheral PSU_AFI_4 */
\r
310 #define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000
\r
311 #define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF
\r
314 /* Definitions for peripheral PSU_AFI_5 */
\r
315 #define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000
\r
316 #define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF
\r
319 /* Definitions for peripheral PSU_AFI_6 */
\r
320 #define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000
\r
321 #define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF
\r
324 /* Definitions for peripheral PSU_APU */
\r
325 #define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000
\r
326 #define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
\r
329 /* Definitions for peripheral PSU_BBRAM_0 */
\r
330 #define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000
\r
331 #define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF
\r
334 /* Definitions for peripheral PSU_CCI_GPV */
\r
335 #define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
\r
336 #define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
\r
339 /* Definitions for peripheral PSU_CCI_REG */
\r
340 #define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000
\r
341 #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF
\r
344 /* Definitions for peripheral PSU_CRF_APB */
\r
345 #define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000
\r
346 #define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF
\r
349 /* Definitions for peripheral PSU_CRL_APB */
\r
350 #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000
\r
351 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF
\r
354 /* Definitions for peripheral PSU_CSU_0 */
\r
355 #define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000
\r
356 #define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF
\r
359 /* Definitions for peripheral PSU_DDR_0 */
\r
360 #define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
\r
361 #define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF
\r
364 /* Definitions for peripheral PSU_DDR_PHY */
\r
365 #define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000
\r
366 #define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF
\r
369 /* Definitions for peripheral PSU_DDR_QOS_CTRL */
\r
370 #define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000
\r
371 #define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF
\r
374 /* Definitions for peripheral PSU_DDR_XMPU0_CFG */
\r
375 #define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000
\r
376 #define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF
\r
379 /* Definitions for peripheral PSU_DDR_XMPU1_CFG */
\r
380 #define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000
\r
381 #define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF
\r
384 /* Definitions for peripheral PSU_DDR_XMPU2_CFG */
\r
385 #define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000
\r
386 #define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF
\r
389 /* Definitions for peripheral PSU_DDR_XMPU3_CFG */
\r
390 #define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000
\r
391 #define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF
\r
394 /* Definitions for peripheral PSU_DDR_XMPU4_CFG */
\r
395 #define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000
\r
396 #define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF
\r
399 /* Definitions for peripheral PSU_DDR_XMPU5_CFG */
\r
400 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000
\r
401 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
\r
404 /* Definitions for peripheral PSU_DDRC_0 */
\r
405 #define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000
\r
406 #define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF
\r
409 /* Definitions for peripheral PSU_DP */
\r
410 #define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000
\r
411 #define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF
\r
414 /* Definitions for peripheral PSU_DPDMA */
\r
415 #define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000
\r
416 #define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF
\r
419 /* Definitions for peripheral PSU_EFUSE */
\r
420 #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000
\r
421 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF
\r
424 /* Definitions for peripheral PSU_FPD_GPV */
\r
425 #define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000
\r
426 #define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF
\r
429 /* Definitions for peripheral PSU_FPD_SLCR */
\r
430 #define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000
\r
431 #define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF
\r
434 /* Definitions for peripheral PSU_FPD_SLCR_SECURE */
\r
435 #define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000
\r
436 #define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF
\r
439 /* Definitions for peripheral PSU_FPD_XMPU_CFG */
\r
440 #define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000
\r
441 #define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF
\r
444 /* Definitions for peripheral PSU_FPD_XMPU_SINK */
\r
445 #define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000
\r
446 #define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF
\r
449 /* Definitions for peripheral PSU_GPU */
\r
450 #define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000
\r
451 #define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
\r
454 /* Definitions for peripheral PSU_IOU_S */
\r
457 /* Definitions for peripheral PSU_IOU_SCNTR */
\r
458 #define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
\r
459 #define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
\r
462 /* Definitions for peripheral PSU_IOU_SCNTRS */
\r
463 #define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000
\r
464 #define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF
\r
467 /* Definitions for peripheral PSU_IOUSECURE_SLCR */
\r
468 #define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000
\r
469 #define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF
\r
472 /* Definitions for peripheral PSU_IOUSLCR_0 */
\r
473 #define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
\r
474 #define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF
\r
477 /* Definitions for peripheral PSU_LPD_SLCR */
\r
478 #define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000
\r
479 #define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF
\r
482 /* Definitions for peripheral PSU_LPD_SLCR_SECURE */
\r
483 #define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000
\r
484 #define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF
\r
487 /* Definitions for peripheral PSU_LPD_XPPU */
\r
488 #define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000
\r
489 #define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF
\r
492 /* Definitions for peripheral PSU_LPD_XPPU_SINK */
\r
493 #define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000
\r
494 #define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF
\r
497 /* Definitions for peripheral PSU_MBISTJTAG */
\r
498 #define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000
\r
499 #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF
\r
502 /* Definitions for peripheral PSU_OCM */
\r
503 #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000
\r
504 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF
\r
507 /* Definitions for peripheral PSU_OCM_RAM_0 */
\r
508 #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
\r
509 #define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF
\r
512 /* Definitions for peripheral PSU_OCM_RAM_1 */
\r
515 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
\r
516 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
\r
517 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
\r
520 /* Definitions for peripheral PSU_PCIE */
\r
521 #define XPAR_PSU_PCIE_S_AXI_BASEADDR 0xFD0E0000
\r
522 #define XPAR_PSU_PCIE_S_AXI_HIGHADDR 0xFD0EFFFF
\r
525 /* Definitions for peripheral PSU_PCIE_ATTRIB_0 */
\r
526 #define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_BASEADDR 0xFD480000
\r
527 #define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_HIGHADDR 0xFD48FFFF
\r
530 /* Definitions for peripheral PSU_PCIE_DMA */
\r
531 #define XPAR_PSU_PCIE_DMA_S_AXI_BASEADDR 0xFD0F0000
\r
532 #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF
\r
535 /* Definitions for peripheral PSU_PMU_GLOBAL_0 */
\r
536 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
\r
537 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
\r
540 /* Definitions for peripheral PSU_PMU_IOMODULE */
\r
541 #define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000
\r
542 #define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
\r
545 /* Definitions for peripheral PSU_PMU_RAM */
\r
546 #define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000
\r
547 #define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF
\r
550 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */
\r
551 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
\r
552 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
\r
555 /* Definitions for peripheral PSU_RPU */
\r
556 #define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000
\r
557 #define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF
\r
560 /* Definitions for peripheral PSU_RSA */
\r
561 #define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000
\r
562 #define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF
\r
565 /* Definitions for peripheral PSU_SATA */
\r
566 #define XPAR_PSU_SATA_S_AXI_BASEADDR 0xFD0C0000
\r
567 #define XPAR_PSU_SATA_S_AXI_HIGHADDR 0xFD0CFFFF
\r
570 /* Definitions for peripheral PSU_SERDES */
\r
571 #define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000
\r
572 #define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF
\r
575 /* Definitions for peripheral PSU_SIOU */
\r
576 #define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000
\r
577 #define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF
\r
580 /* Definitions for peripheral PSU_SMMU_GPV */
\r
581 #define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000
\r
582 #define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF
\r
585 /* Definitions for peripheral PSU_SMMU_REG */
\r
586 #define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000
\r
587 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
\r
590 /* Definitions for peripheral PSU_USB_0 */
\r
591 #define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000
\r
592 #define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF
\r
595 /******************************************************************/
\r
597 /* Definitions for driver GPIOPS */
\r
598 #define XPAR_XGPIOPS_NUM_INSTANCES 1
\r
600 /* Definitions for peripheral PSU_GPIO_0 */
\r
601 #define XPAR_PSU_GPIO_0_DEVICE_ID 0
\r
602 #define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000
\r
603 #define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF
\r
606 /******************************************************************/
\r
608 /* Canonical definitions for peripheral PSU_GPIO_0 */
\r
609 #define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
\r
610 #define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
\r
611 #define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF
\r
614 /******************************************************************/
\r
616 /* Definitions for driver IICPS */
\r
617 #define XPAR_XIICPS_NUM_INSTANCES 2
\r
619 /* Definitions for peripheral PSU_I2C_0 */
\r
620 #define XPAR_PSU_I2C_0_DEVICE_ID 0
\r
621 #define XPAR_PSU_I2C_0_BASEADDR 0xFF020000
\r
622 #define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF
\r
623 #define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999
\r
626 /* Definitions for peripheral PSU_I2C_1 */
\r
627 #define XPAR_PSU_I2C_1_DEVICE_ID 1
\r
628 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000
\r
629 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF
\r
630 #define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999
\r
633 /******************************************************************/
\r
635 /* Canonical definitions for peripheral PSU_I2C_0 */
\r
636 #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID
\r
637 #define XPAR_XIICPS_0_BASEADDR 0xFF020000
\r
638 #define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF
\r
639 #define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999
\r
641 /* Canonical definitions for peripheral PSU_I2C_1 */
\r
642 #define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID
\r
643 #define XPAR_XIICPS_1_BASEADDR 0xFF030000
\r
644 #define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF
\r
645 #define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999
\r
648 /******************************************************************/
\r
650 #define XPAR_XIPIPSU_NUM_INSTANCES 3
\r
652 /* Parameter definitions for peripheral psu_ipi_0 */
\r
653 #define XPAR_PSU_IPI_0_DEVICE_ID 0
\r
654 #define XPAR_PSU_IPI_0_BASE_ADDRESS 0xFF300000
\r
655 #define XPAR_PSU_IPI_0_BIT_MASK 0x00000001
\r
656 #define XPAR_PSU_IPI_0_BUFFER_INDEX 2
\r
657 #define XPAR_PSU_IPI_0_INT_ID 67
\r
659 /* Parameter definitions for peripheral psu_ipi_1 */
\r
660 #define XPAR_PSU_IPI_1_DEVICE_ID 1
\r
661 #define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000
\r
662 #define XPAR_PSU_IPI_1_BIT_MASK 0x00000100
\r
663 #define XPAR_PSU_IPI_1_BUFFER_INDEX 0
\r
664 #define XPAR_PSU_IPI_1_INT_ID 65
\r
666 /* Parameter definitions for peripheral psu_ipi_2 */
\r
667 #define XPAR_PSU_IPI_2_DEVICE_ID 2
\r
668 #define XPAR_PSU_IPI_2_BASE_ADDRESS 0xFF320000
\r
669 #define XPAR_PSU_IPI_2_BIT_MASK 0x00000200
\r
670 #define XPAR_PSU_IPI_2_BUFFER_INDEX 1
\r
671 #define XPAR_PSU_IPI_2_INT_ID 66
\r
673 /* Canonical definitions for peripheral psu_ipi_0 */
\r
674 #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_0_DEVICE_ID
\r
675 #define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_0_BASE_ADDRESS
\r
676 #define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_0_BIT_MASK
\r
677 #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_0_BUFFER_INDEX
\r
678 #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_0_INT_ID
\r
680 /* Canonical definitions for peripheral psu_ipi_1 */
\r
681 #define XPAR_XIPIPSU_1_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID
\r
682 #define XPAR_XIPIPSU_1_BASE_ADDRESS XPAR_PSU_IPI_1_BASE_ADDRESS
\r
683 #define XPAR_XIPIPSU_1_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
684 #define XPAR_XIPIPSU_1_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX
\r
685 #define XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_1_INT_ID
\r
687 /* Canonical definitions for peripheral psu_ipi_2 */
\r
688 #define XPAR_XIPIPSU_2_DEVICE_ID XPAR_PSU_IPI_2_DEVICE_ID
\r
689 #define XPAR_XIPIPSU_2_BASE_ADDRESS XPAR_PSU_IPI_2_BASE_ADDRESS
\r
690 #define XPAR_XIPIPSU_2_BIT_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
691 #define XPAR_XIPIPSU_2_BUFFER_INDEX XPAR_PSU_IPI_2_BUFFER_INDEX
\r
692 #define XPAR_XIPIPSU_2_INT_ID XPAR_PSU_IPI_2_INT_ID
\r
694 #define XPAR_XIPIPSU_NUM_TARGETS 11
\r
696 #define XPAR_PSU_IPI_0_BIT_MASK 0x00000001
\r
697 #define XPAR_PSU_IPI_0_BUFFER_INDEX 2
\r
698 #define XPAR_PSU_IPI_1_BIT_MASK 0x00000100
\r
699 #define XPAR_PSU_IPI_1_BUFFER_INDEX 0
\r
700 #define XPAR_PSU_IPI_2_BIT_MASK 0x00000200
\r
701 #define XPAR_PSU_IPI_2_BUFFER_INDEX 1
\r
702 #define XPAR_PSU_IPI_3_BIT_MASK 0x00010000
\r
703 #define XPAR_PSU_IPI_3_BUFFER_INDEX 7
\r
704 #define XPAR_PSU_IPI_4_BIT_MASK 0x00020000
\r
705 #define XPAR_PSU_IPI_4_BUFFER_INDEX 7
\r
706 #define XPAR_PSU_IPI_5_BIT_MASK 0x00040000
\r
707 #define XPAR_PSU_IPI_5_BUFFER_INDEX 7
\r
708 #define XPAR_PSU_IPI_6_BIT_MASK 0x00080000
\r
709 #define XPAR_PSU_IPI_6_BUFFER_INDEX 7
\r
710 #define XPAR_PSU_IPI_7_BIT_MASK 0x01000000
\r
711 #define XPAR_PSU_IPI_7_BUFFER_INDEX 3
\r
712 #define XPAR_PSU_IPI_8_BIT_MASK 0x02000000
\r
713 #define XPAR_PSU_IPI_8_BUFFER_INDEX 4
\r
714 #define XPAR_PSU_IPI_9_BIT_MASK 0x04000000
\r
715 #define XPAR_PSU_IPI_9_BUFFER_INDEX 5
\r
716 #define XPAR_PSU_IPI_10_BIT_MASK 0x08000000
\r
717 #define XPAR_PSU_IPI_10_BUFFER_INDEX 6
\r
718 /* Target List for referring to processor IPI Targets */
\r
720 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
\r
721 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0
\r
722 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
723 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX 1
\r
724 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
725 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX 2
\r
727 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
\r
728 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0
\r
729 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
730 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX 1
\r
731 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
732 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX 2
\r
734 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
\r
735 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0
\r
736 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
737 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX 1
\r
738 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
739 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX 2
\r
741 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK
\r
742 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0
\r
743 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
744 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX 1
\r
745 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
746 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX 2
\r
748 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
749 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1
\r
750 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
751 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_INDEX 2
\r
753 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
754 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 1
\r
755 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
756 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX 2
\r
758 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK
\r
759 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 1
\r
760 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK
\r
761 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 2
\r
762 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_3_BIT_MASK
\r
763 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 3
\r
764 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_4_BIT_MASK
\r
765 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 4
\r
766 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK XPAR_PSU_IPI_5_BIT_MASK
\r
767 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX 5
\r
768 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK XPAR_PSU_IPI_6_BIT_MASK
\r
769 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX 6
\r
771 /* Definitions for driver QSPIPSU */
\r
772 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
\r
774 /* Definitions for peripheral PSU_QSPI_0 */
\r
775 #define XPAR_PSU_QSPI_0_DEVICE_ID 0
\r
776 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000
\r
777 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF
\r
778 #define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749
\r
779 #define XPAR_PSU_QSPI_0_QSPI_MODE 2
\r
780 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2
\r
783 /******************************************************************/
\r
785 /* Canonical definitions for peripheral PSU_QSPI_0 */
\r
786 #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID
\r
787 #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000
\r
788 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF
\r
789 #define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749
\r
790 #define XPAR_XQSPIPSU_0_QSPI_MODE 2
\r
791 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2
\r
794 /******************************************************************/
\r
796 /* Definitions for driver RTCPSU */
\r
797 #define XPAR_XRTCPSU_NUM_INSTANCES 1
\r
799 /* Definitions for peripheral PSU_RTC */
\r
800 #define XPAR_PSU_RTC_DEVICE_ID 0
\r
801 #define XPAR_PSU_RTC_BASEADDR 0xFFA60000
\r
802 #define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF
\r
805 /******************************************************************/
\r
807 /* Canonical definitions for peripheral PSU_RTC */
\r
808 #define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID
\r
809 #define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000
\r
810 #define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF
\r
813 /******************************************************************/
\r
815 /* Definitions for driver SCUGIC */
\r
816 #define XPAR_XSCUGIC_NUM_INSTANCES 1
\r
818 /* Definitions for peripheral PSU_ACPU_GIC */
\r
819 #define XPAR_PSU_ACPU_GIC_DEVICE_ID 0
\r
820 #define XPAR_PSU_ACPU_GIC_BASEADDR 0xF9020000
\r
821 #define XPAR_PSU_ACPU_GIC_HIGHADDR 0xF9020FFF
\r
822 #define XPAR_PSU_ACPU_GIC_DIST_BASEADDR 0xF9010000
\r
825 /******************************************************************/
\r
827 /* Canonical definitions for peripheral PSU_ACPU_GIC */
\r
828 #define XPAR_SCUGIC_0_DEVICE_ID 0
\r
829 #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9020000
\r
830 #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9020FFF
\r
831 #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000
\r
834 /******************************************************************/
\r
836 /* Definitions for driver SDPS */
\r
837 #define XPAR_XSDPS_NUM_INSTANCES 1
\r
839 /* Definitions for peripheral PSU_SD_1 */
\r
840 #define XPAR_PSU_SD_1_DEVICE_ID 0
\r
841 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000
\r
842 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF
\r
843 #define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006
\r
844 #define XPAR_PSU_SD_1_HAS_CD 1
\r
845 #define XPAR_PSU_SD_1_HAS_WP 1
\r
848 /******************************************************************/
\r
850 /* Canonical definitions for peripheral PSU_SD_1 */
\r
851 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID
\r
852 #define XPAR_XSDPS_0_BASEADDR 0xFF170000
\r
853 #define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF
\r
854 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006
\r
855 #define XPAR_XSDPS_0_HAS_CD 1
\r
856 #define XPAR_XSDPS_0_HAS_WP 1
\r
859 /******************************************************************/
\r
861 /* Definitions for driver SYSMONPSU */
\r
862 #define XPAR_XSYSMONPSU_NUM_INSTANCES 1
\r
864 /* Definitions for peripheral PSU_AMS */
\r
865 #define XPAR_PSU_AMS_DEVICE_ID 0
\r
866 #define XPAR_PSU_AMS_BASEADDR 0xFFA50000
\r
867 #define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF
\r
870 /******************************************************************/
\r
872 /* Canonical definitions for peripheral PSU_AMS */
\r
873 #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID
\r
874 #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000
\r
875 #define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF
\r
878 /******************************************************************/
\r
880 /* Definitions for driver TTCPS */
\r
881 #define XPAR_XTTCPS_NUM_INSTANCES 12
\r
883 /* Definitions for peripheral PSU_TTC_0 */
\r
884 #define XPAR_PSU_TTC_0_DEVICE_ID 0
\r
885 #define XPAR_PSU_TTC_0_BASEADDR 0XFF110000
\r
886 #define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000
\r
887 #define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0
\r
888 #define XPAR_PSU_TTC_1_DEVICE_ID 1
\r
889 #define XPAR_PSU_TTC_1_BASEADDR 0XFF110004
\r
890 #define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000
\r
891 #define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0
\r
892 #define XPAR_PSU_TTC_2_DEVICE_ID 2
\r
893 #define XPAR_PSU_TTC_2_BASEADDR 0XFF110008
\r
894 #define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000
\r
895 #define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0
\r
898 /* Definitions for peripheral PSU_TTC_1 */
\r
899 #define XPAR_PSU_TTC_3_DEVICE_ID 3
\r
900 #define XPAR_PSU_TTC_3_BASEADDR 0XFF120000
\r
901 #define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000
\r
902 #define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0
\r
903 #define XPAR_PSU_TTC_4_DEVICE_ID 4
\r
904 #define XPAR_PSU_TTC_4_BASEADDR 0XFF120004
\r
905 #define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000
\r
906 #define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0
\r
907 #define XPAR_PSU_TTC_5_DEVICE_ID 5
\r
908 #define XPAR_PSU_TTC_5_BASEADDR 0XFF120008
\r
909 #define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000
\r
910 #define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0
\r
913 /* Definitions for peripheral PSU_TTC_2 */
\r
914 #define XPAR_PSU_TTC_6_DEVICE_ID 6
\r
915 #define XPAR_PSU_TTC_6_BASEADDR 0XFF130000
\r
916 #define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000
\r
917 #define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0
\r
918 #define XPAR_PSU_TTC_7_DEVICE_ID 7
\r
919 #define XPAR_PSU_TTC_7_BASEADDR 0XFF130004
\r
920 #define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000
\r
921 #define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0
\r
922 #define XPAR_PSU_TTC_8_DEVICE_ID 8
\r
923 #define XPAR_PSU_TTC_8_BASEADDR 0XFF130008
\r
924 #define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000
\r
925 #define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0
\r
928 /* Definitions for peripheral PSU_TTC_3 */
\r
929 #define XPAR_PSU_TTC_9_DEVICE_ID 9
\r
930 #define XPAR_PSU_TTC_9_BASEADDR 0XFF140000
\r
931 #define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000
\r
932 #define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0
\r
933 #define XPAR_PSU_TTC_10_DEVICE_ID 10
\r
934 #define XPAR_PSU_TTC_10_BASEADDR 0XFF140004
\r
935 #define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000
\r
936 #define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0
\r
937 #define XPAR_PSU_TTC_11_DEVICE_ID 11
\r
938 #define XPAR_PSU_TTC_11_BASEADDR 0XFF140008
\r
939 #define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000
\r
940 #define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0
\r
943 /******************************************************************/
\r
945 /* Canonical definitions for peripheral PSU_TTC_0 */
\r
946 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID
\r
947 #define XPAR_XTTCPS_0_BASEADDR 0xFF110000
\r
948 #define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000
\r
949 #define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
\r
951 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID
\r
952 #define XPAR_XTTCPS_1_BASEADDR 0xFF110004
\r
953 #define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000
\r
954 #define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
\r
956 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID
\r
957 #define XPAR_XTTCPS_2_BASEADDR 0xFF110008
\r
958 #define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000
\r
959 #define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
\r
961 /* Canonical definitions for peripheral PSU_TTC_1 */
\r
962 #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID
\r
963 #define XPAR_XTTCPS_3_BASEADDR 0xFF120000
\r
964 #define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000
\r
965 #define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0
\r
967 #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID
\r
968 #define XPAR_XTTCPS_4_BASEADDR 0xFF120004
\r
969 #define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000
\r
970 #define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0
\r
972 #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID
\r
973 #define XPAR_XTTCPS_5_BASEADDR 0xFF120008
\r
974 #define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000
\r
975 #define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0
\r
977 /* Canonical definitions for peripheral PSU_TTC_2 */
\r
978 #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID
\r
979 #define XPAR_XTTCPS_6_BASEADDR 0xFF130000
\r
980 #define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000
\r
981 #define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0
\r
983 #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID
\r
984 #define XPAR_XTTCPS_7_BASEADDR 0xFF130004
\r
985 #define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000
\r
986 #define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0
\r
988 #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID
\r
989 #define XPAR_XTTCPS_8_BASEADDR 0xFF130008
\r
990 #define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000
\r
991 #define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0
\r
993 /* Canonical definitions for peripheral PSU_TTC_3 */
\r
994 #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID
\r
995 #define XPAR_XTTCPS_9_BASEADDR 0xFF140000
\r
996 #define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000
\r
997 #define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0
\r
999 #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID
\r
1000 #define XPAR_XTTCPS_10_BASEADDR 0xFF140004
\r
1001 #define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000
\r
1002 #define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0
\r
1004 #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID
\r
1005 #define XPAR_XTTCPS_11_BASEADDR 0xFF140008
\r
1006 #define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000
\r
1007 #define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0
\r
1010 /******************************************************************/
\r
1012 /* Definitions for driver UARTPS */
\r
1013 #define XPAR_XUARTPS_NUM_INSTANCES 2
\r
1015 /* Definitions for peripheral PSU_UART_0 */
\r
1016 #define XPAR_PSU_UART_0_DEVICE_ID 0
\r
1017 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000
\r
1018 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF
\r
1019 #define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999
\r
1020 #define XPAR_PSU_UART_0_HAS_MODEM 0
\r
1023 /* Definitions for peripheral PSU_UART_1 */
\r
1024 #define XPAR_PSU_UART_1_DEVICE_ID 1
\r
1025 #define XPAR_PSU_UART_1_BASEADDR 0xFF010000
\r
1026 #define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF
\r
1027 #define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999
\r
1028 #define XPAR_PSU_UART_1_HAS_MODEM 0
\r
1031 /******************************************************************/
\r
1033 /* Canonical definitions for peripheral PSU_UART_0 */
\r
1034 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID
\r
1035 #define XPAR_XUARTPS_0_BASEADDR 0xFF000000
\r
1036 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF
\r
1037 #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999
\r
1038 #define XPAR_XUARTPS_0_HAS_MODEM 0
\r
1040 /* Canonical definitions for peripheral PSU_UART_1 */
\r
1041 #define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID
\r
1042 #define XPAR_XUARTPS_1_BASEADDR 0xFF010000
\r
1043 #define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF
\r
1044 #define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999
\r
1045 #define XPAR_XUARTPS_1_HAS_MODEM 0
\r
1048 /******************************************************************/
\r
1050 /* Definitions for driver WDTPS */
\r
1051 #define XPAR_XWDTPS_NUM_INSTANCES 2
\r
1053 /* Definitions for peripheral PSU_WDT_0 */
\r
1054 #define XPAR_PSU_WDT_0_DEVICE_ID 0
\r
1055 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
\r
1056 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
\r
1057 #define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
\r
1060 /* Definitions for peripheral PSU_WDT_1 */
\r
1061 #define XPAR_PSU_WDT_1_DEVICE_ID 1
\r
1062 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
\r
1063 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
\r
1064 #define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
\r
1067 /******************************************************************/
\r
1069 /* Canonical definitions for peripheral PSU_WDT_0 */
\r
1070 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
\r
1071 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
\r
1072 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
\r
1073 #define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
\r
1075 /* Canonical definitions for peripheral PSU_WDT_1 */
\r
1076 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
\r
1077 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
\r
1078 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
\r
1079 #define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
\r
1082 /******************************************************************/
\r
1084 /* Definitions for driver ZDMA */
\r
1085 #define XPAR_XZDMA_NUM_INSTANCES 16
\r
1087 /* Definitions for peripheral PSU_ADMA_0 */
\r
1088 #define XPAR_PSU_ADMA_0_DEVICE_ID 0
\r
1089 #define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000
\r
1090 #define XPAR_PSU_ADMA_0_DMA_MODE 1
\r
1091 #define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF
\r
1092 #define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0
\r
1095 /* Definitions for peripheral PSU_ADMA_1 */
\r
1096 #define XPAR_PSU_ADMA_1_DEVICE_ID 1
\r
1097 #define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000
\r
1098 #define XPAR_PSU_ADMA_1_DMA_MODE 1
\r
1099 #define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF
\r
1100 #define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0
\r
1103 /* Definitions for peripheral PSU_ADMA_2 */
\r
1104 #define XPAR_PSU_ADMA_2_DEVICE_ID 2
\r
1105 #define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000
\r
1106 #define XPAR_PSU_ADMA_2_DMA_MODE 1
\r
1107 #define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF
\r
1108 #define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0
\r
1111 /* Definitions for peripheral PSU_ADMA_3 */
\r
1112 #define XPAR_PSU_ADMA_3_DEVICE_ID 3
\r
1113 #define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000
\r
1114 #define XPAR_PSU_ADMA_3_DMA_MODE 1
\r
1115 #define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF
\r
1116 #define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0
\r
1119 /* Definitions for peripheral PSU_ADMA_4 */
\r
1120 #define XPAR_PSU_ADMA_4_DEVICE_ID 4
\r
1121 #define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000
\r
1122 #define XPAR_PSU_ADMA_4_DMA_MODE 1
\r
1123 #define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF
\r
1124 #define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0
\r
1127 /* Definitions for peripheral PSU_ADMA_5 */
\r
1128 #define XPAR_PSU_ADMA_5_DEVICE_ID 5
\r
1129 #define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000
\r
1130 #define XPAR_PSU_ADMA_5_DMA_MODE 1
\r
1131 #define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF
\r
1132 #define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0
\r
1135 /* Definitions for peripheral PSU_ADMA_6 */
\r
1136 #define XPAR_PSU_ADMA_6_DEVICE_ID 6
\r
1137 #define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000
\r
1138 #define XPAR_PSU_ADMA_6_DMA_MODE 1
\r
1139 #define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF
\r
1140 #define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0
\r
1143 /* Definitions for peripheral PSU_ADMA_7 */
\r
1144 #define XPAR_PSU_ADMA_7_DEVICE_ID 7
\r
1145 #define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000
\r
1146 #define XPAR_PSU_ADMA_7_DMA_MODE 1
\r
1147 #define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF
\r
1148 #define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0
\r
1151 /* Definitions for peripheral PSU_GDMA_0 */
\r
1152 #define XPAR_PSU_GDMA_0_DEVICE_ID 8
\r
1153 #define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000
\r
1154 #define XPAR_PSU_GDMA_0_DMA_MODE 0
\r
1155 #define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF
\r
1156 #define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0
\r
1159 /* Definitions for peripheral PSU_GDMA_1 */
\r
1160 #define XPAR_PSU_GDMA_1_DEVICE_ID 9
\r
1161 #define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000
\r
1162 #define XPAR_PSU_GDMA_1_DMA_MODE 0
\r
1163 #define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF
\r
1164 #define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0
\r
1167 /* Definitions for peripheral PSU_GDMA_2 */
\r
1168 #define XPAR_PSU_GDMA_2_DEVICE_ID 10
\r
1169 #define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000
\r
1170 #define XPAR_PSU_GDMA_2_DMA_MODE 0
\r
1171 #define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF
\r
1172 #define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0
\r
1175 /* Definitions for peripheral PSU_GDMA_3 */
\r
1176 #define XPAR_PSU_GDMA_3_DEVICE_ID 11
\r
1177 #define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000
\r
1178 #define XPAR_PSU_GDMA_3_DMA_MODE 0
\r
1179 #define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF
\r
1180 #define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0
\r
1183 /* Definitions for peripheral PSU_GDMA_4 */
\r
1184 #define XPAR_PSU_GDMA_4_DEVICE_ID 12
\r
1185 #define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000
\r
1186 #define XPAR_PSU_GDMA_4_DMA_MODE 0
\r
1187 #define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF
\r
1188 #define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0
\r
1191 /* Definitions for peripheral PSU_GDMA_5 */
\r
1192 #define XPAR_PSU_GDMA_5_DEVICE_ID 13
\r
1193 #define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000
\r
1194 #define XPAR_PSU_GDMA_5_DMA_MODE 0
\r
1195 #define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF
\r
1196 #define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0
\r
1199 /* Definitions for peripheral PSU_GDMA_6 */
\r
1200 #define XPAR_PSU_GDMA_6_DEVICE_ID 14
\r
1201 #define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000
\r
1202 #define XPAR_PSU_GDMA_6_DMA_MODE 0
\r
1203 #define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF
\r
1204 #define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0
\r
1207 /* Definitions for peripheral PSU_GDMA_7 */
\r
1208 #define XPAR_PSU_GDMA_7_DEVICE_ID 15
\r
1209 #define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000
\r
1210 #define XPAR_PSU_GDMA_7_DMA_MODE 0
\r
1211 #define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF
\r
1212 #define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0
\r
1215 /******************************************************************/
\r
1217 /* Canonical definitions for peripheral PSU_ADMA_0 */
\r
1218 #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID
\r
1219 #define XPAR_XZDMA_0_BASEADDR 0xFFA80000
\r
1220 #define XPAR_XZDMA_0_DMA_MODE 1
\r
1221 #define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF
\r
1222 #define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0
\r
1224 /* Canonical definitions for peripheral PSU_ADMA_1 */
\r
1225 #define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID
\r
1226 #define XPAR_XZDMA_1_BASEADDR 0xFFA90000
\r
1227 #define XPAR_XZDMA_1_DMA_MODE 1
\r
1228 #define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF
\r
1229 #define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0
\r
1231 /* Canonical definitions for peripheral PSU_ADMA_2 */
\r
1232 #define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID
\r
1233 #define XPAR_XZDMA_2_BASEADDR 0xFFAA0000
\r
1234 #define XPAR_XZDMA_2_DMA_MODE 1
\r
1235 #define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF
\r
1236 #define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0
\r
1238 /* Canonical definitions for peripheral PSU_ADMA_3 */
\r
1239 #define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID
\r
1240 #define XPAR_XZDMA_3_BASEADDR 0xFFAB0000
\r
1241 #define XPAR_XZDMA_3_DMA_MODE 1
\r
1242 #define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF
\r
1243 #define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0
\r
1245 /* Canonical definitions for peripheral PSU_ADMA_4 */
\r
1246 #define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID
\r
1247 #define XPAR_XZDMA_4_BASEADDR 0xFFAC0000
\r
1248 #define XPAR_XZDMA_4_DMA_MODE 1
\r
1249 #define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF
\r
1250 #define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0
\r
1252 /* Canonical definitions for peripheral PSU_ADMA_5 */
\r
1253 #define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID
\r
1254 #define XPAR_XZDMA_5_BASEADDR 0xFFAD0000
\r
1255 #define XPAR_XZDMA_5_DMA_MODE 1
\r
1256 #define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF
\r
1257 #define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0
\r
1259 /* Canonical definitions for peripheral PSU_ADMA_6 */
\r
1260 #define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID
\r
1261 #define XPAR_XZDMA_6_BASEADDR 0xFFAE0000
\r
1262 #define XPAR_XZDMA_6_DMA_MODE 1
\r
1263 #define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF
\r
1264 #define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0
\r
1266 /* Canonical definitions for peripheral PSU_ADMA_7 */
\r
1267 #define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID
\r
1268 #define XPAR_XZDMA_7_BASEADDR 0xFFAF0000
\r
1269 #define XPAR_XZDMA_7_DMA_MODE 1
\r
1270 #define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF
\r
1271 #define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0
\r
1273 /* Canonical definitions for peripheral PSU_GDMA_0 */
\r
1274 #define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID
\r
1275 #define XPAR_XZDMA_8_BASEADDR 0xFD500000
\r
1276 #define XPAR_XZDMA_8_DMA_MODE 0
\r
1277 #define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF
\r
1278 #define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0
\r
1280 /* Canonical definitions for peripheral PSU_GDMA_1 */
\r
1281 #define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID
\r
1282 #define XPAR_XZDMA_9_BASEADDR 0xFD510000
\r
1283 #define XPAR_XZDMA_9_DMA_MODE 0
\r
1284 #define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF
\r
1285 #define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0
\r
1287 /* Canonical definitions for peripheral PSU_GDMA_2 */
\r
1288 #define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID
\r
1289 #define XPAR_XZDMA_10_BASEADDR 0xFD520000
\r
1290 #define XPAR_XZDMA_10_DMA_MODE 0
\r
1291 #define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF
\r
1292 #define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0
\r
1294 /* Canonical definitions for peripheral PSU_GDMA_3 */
\r
1295 #define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID
\r
1296 #define XPAR_XZDMA_11_BASEADDR 0xFD530000
\r
1297 #define XPAR_XZDMA_11_DMA_MODE 0
\r
1298 #define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF
\r
1299 #define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0
\r
1301 /* Canonical definitions for peripheral PSU_GDMA_4 */
\r
1302 #define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID
\r
1303 #define XPAR_XZDMA_12_BASEADDR 0xFD540000
\r
1304 #define XPAR_XZDMA_12_DMA_MODE 0
\r
1305 #define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF
\r
1306 #define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0
\r
1308 /* Canonical definitions for peripheral PSU_GDMA_5 */
\r
1309 #define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID
\r
1310 #define XPAR_XZDMA_13_BASEADDR 0xFD550000
\r
1311 #define XPAR_XZDMA_13_DMA_MODE 0
\r
1312 #define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF
\r
1313 #define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0
\r
1315 /* Canonical definitions for peripheral PSU_GDMA_6 */
\r
1316 #define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID
\r
1317 #define XPAR_XZDMA_14_BASEADDR 0xFD560000
\r
1318 #define XPAR_XZDMA_14_DMA_MODE 0
\r
1319 #define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF
\r
1320 #define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0
\r
1322 /* Canonical definitions for peripheral PSU_GDMA_7 */
\r
1323 #define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID
\r
1324 #define XPAR_XZDMA_15_BASEADDR 0xFD570000
\r
1325 #define XPAR_XZDMA_15_DMA_MODE 0
\r
1326 #define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF
\r
1327 #define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0
\r
1330 /******************************************************************/
\r
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