// --------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - // --------------------------------------------------------- // The software is delivered "AS IS" without warranty or // condition of any kind, either express, implied or // statutory. This includes without limitation any warranty // or condition with respect to merchantability or fitness // for any particular purpose, or against the infringements of // intellectual property rights of others. // --------------------------------------------------------- // File: SAM7_RAM.mac // // User setup file for CSPY debugger to simulate interrupt // driven Fibonacchi data input. // 1.1 16/Jun/04 JPP : Creation // 1.2 27/Aug/04 JPP : PLL setting // // $Revision: 1.3 $ // // --------------------------------------------------------- __var i; __var pt; execUserPreload() { //* PllSetting(); //* Set the RAM memory at 0x0020 0000 for code AT 0 flash area CheckNoRemap(); //* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R i=__readMemory32(0xFFFFF240,"Memory"); __message " ---------------------------------------- Chip ID 0x",i:%X; i=__readMemory32(0xFFFFF244,"Memory"); __message " ---------------------------------------- Extention 0x",i:%X; i=__readMemory32(0xFFFFFF6C,"Memory"); __message " ---------------------------------------- Flash Version 0x",i:%X; //* Get the chip status //* Init AIC AIC(); //* Watchdog Disable Watchdog(); } //----------------------------------------------------------------------------- // PllSetting //------------------------------- // Set PLL //----------------------------------------------------------------------------- PllSetting() { // -1- Enabling the Main Oscillator: //*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register //*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register //*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register //*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 // AT91C_CKGR_MOSCEN )); //0x0000 0001 __writeMemory32(0x00000601,0xFFFFFC20,"Memory"); // -2- Wait // -3- Setting PLL and divider: // - div by 5 Fin = 3,6864 =(18,432 / 5) // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) // for 96 MHz the erroe is 0.16% // Field out NOT USED = 0 // PLLCOUNT pll startup time esrtimate at : 0.844 ms // PLLCOUNT 28 = 0.000844 /(1/32768) // pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 // (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 // (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 __writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); // -2- Wait // -5- Selection of Master Clock and Processor Clock // select the PLL clock divided by 2 // pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 // AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 __writeMemory32(0x00000007,0xFFFFFC30,"Memory"); __message "------------------------------- PLL Enable ----------------------------------------"; } //----------------------------------------------------------------------------- // Watchdog //------------------------------- // Normally, the Watchdog is enable at the reset for load it's preferable to // Disable. //----------------------------------------------------------------------------- Watchdog() { //* Watchdog Disable // AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); __message "------------------------------- Watchdog Disable ----------------------------------------"; } CheckNoRemap() { //* Read the value at 0x0 i=__readMemory32(0x00000000,"Memory"); i=i+1; __writeMemory32(i,0x00,"Memory"); pt=__readMemory32(0x00000000,"Memory"); if (i == pt) { __message "------------------------------- The Remap is done ----------------------------------------"; } else { __message "------------------------------- The Remap is NOT -----------------------------------------"; //* Toggel RESET The remap __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); } } execUserSetup() { ini(); __message "-------------------------------Set PC ----------------------------------------"; __writeMemory32(0x00000000,0xB4,"Register"); } //----------------------------------------------------------------------------- // Reset the Interrupt Controller //------------------------------- // Normally, the code is executed only if a reset has been actually performed. // So, the AIC initialization resumes at setting up the default vectors. //----------------------------------------------------------------------------- AIC() { // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); for (i=0;i < 8; i++) { // AT91C_BASE_AIC->AIC_EOICR pt = __readMemory32(0xFFFFF130,"Memory"); } __message "------------------------------- AIC INIT ---------------------------------------------"; } ini() { __writeMemory32(0x0,0x00,"Register"); __writeMemory32(0x0,0x04,"Register"); __writeMemory32(0x0,0x08,"Register"); __writeMemory32(0x0,0x0C,"Register"); __writeMemory32(0x0,0x10,"Register"); __writeMemory32(0x0,0x14,"Register"); __writeMemory32(0x0,0x18,"Register"); __writeMemory32(0x0,0x1C,"Register"); __writeMemory32(0x0,0x20,"Register"); __writeMemory32(0x0,0x24,"Register"); __writeMemory32(0x0,0x28,"Register"); __writeMemory32(0x0,0x2C,"Register"); __writeMemory32(0x0,0x30,"Register"); __writeMemory32(0x0,0x34,"Register"); __writeMemory32(0x0,0x38,"Register"); // Set CPSR __writeMemory32(0x0D3,0x98,"Register"); } RG() { i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; }