# 
# ##############################################################################
# 
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# 
# Tue Mar 04 08:41:46 2008
# 
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:	 virtex4
# Device:	 xc4vfx12
# Package:	 ff668
# Speed Grade:	 -10
# 
# Processor: PPC 405
# Processor clock frequency: 100.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# Data Cache: 16 KB
# Instruction Cache: 16 KB
# On Chip Memory :   4 KB
# Total Off Chip Memory :   1 MB
#   - SRAM_256Kx32 =   1 MB
# 
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]
 PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O
 PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = sys_clk_s
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_0_lock
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x40000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = opb
 PORT Interrupt = RS232_Uart_Interrupt
 PORT RX = fpga_0_RS232_Uart_RX
 PORT TX = fpga_0_RS232_Uart_TX
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_Positions
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = opb
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
END

BEGIN plb_emc
 PARAMETER INSTANCE = SRAM_256Kx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x000fffff
 BUS_INTERFACE SPLB = plb
 PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN
 PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ
 PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN
 PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN
 PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_include_burst_cacheln_support = 0
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xfffff000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = RS232_Uart_Interrupt
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split
 PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END