     [file version.texi not included]

OpenOCD User's Guide
********************

This User's Guide documents release VERSION, dated UPDATED, of the Open On-Chip Debugger (OpenOCD).

  * Copyright © 2008 The OpenOCD Project

  * Copyright © 2007-2008 Spencer Oliver spen@spen-soft.co.uk

  * Copyright © 2008 Oyvind Harboe oyvind.harboe@zylin.com

  * Copyright © 2008 Duane Ellis openocd@duaneellis.com

     Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts.  A copy of the license is included in the section entitled ``GNU Free Documentation License''.

About
*****

OpenOCD was created by Dominic Rath as part of a diploma thesis written at the University of Applied Sciences Augsburg (http://www.fh-augsburg.de). Since that time, the project has grown into an active open-source project, supported by a diverse community of software and hardware developers from around the world.

What is OpenOCD?
================

The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices.

JTAG: OpenOCD uses a ``hardware interface dongle'' to communicate with the JTAG (IEEE 1149.1) compliant TAPs on your target board. A TAP is a ``Test Access Port'', a module which processes special instructions and data.  TAPs are daisy-chained within and between chips and boards.

Dongles: OpenOCD currently supports many types of hardware dongles: USB based, parallel port based, and other standalone boxes that run OpenOCD internally. See JTAG Hardware Dongles.

GDB Debug: It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T, ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be debugged via the GDB protocol.

Flash Programing: Flash writing is supported for external CFI compatible NOR flashes (Intel and AMD/Spansion command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3, and STM32x). Preliminary support for various NAND flash controllers (LPC3180, Orion, S3C24xx, more) controller is included.

OpenOCD Web Site
================

The OpenOCD web site provides the latest public news from the community:

http://openocd.berlios.de/web/

Latest User's Guide:
====================

The user's guide you are now reading may not be the latest one available.  A version for more recent code may be available. Its HTML form is published irregularly at:

http://openocd.berlios.de/doc/

PDF form is likewise published at:

http://openocd.berlios.de/doc/pdf/

OpenOCD User's Forum
====================

There is an OpenOCD forum (phpBB) hosted by SparkFun:

http://forum.sparkfun.com/viewforum.php?f=18

OpenOCD Developer Resources
***************************

If you are interested in improving the state of OpenOCD's debugging and testing support, new contributions will be welcome.  Motivated developers can produce new target, flash or interface drivers, improve the documentation, as well as more conventional bug fixes and enhancements.

The resources in this chapter are available for developers wishing to explore or expand the OpenOCD source code.

OpenOCD Subversion Repository
=============================

The ``Building From Source'' section provides instructions to retrieve and and build the latest version of the OpenOCD source code. See Building OpenOCD.

Developers that want to contribute patches to the OpenOCD system are strongly encouraged to base their work off of the most recent trunk revision.  Patches created against older versions may require additional work from their submitter in order to be updated for newer releases.

Doxygen Developer Manual
========================

During the development of the 0.2.0 release, the OpenOCD project began providing a Doxygen reference manual.  This document contains more technical information about the software internals, development processes, and similar documentation:

http://openocd.berlios.de/doc/doxygen/index.html

This document is a work-in-progress, but contributions would be welcome to fill in the gaps.  All of the source files are provided in-tree, listed in the Doxyfile configuration in the top of the repository trunk.

OpenOCD Developer Mailing List
==============================

The OpenOCD Developer Mailing List provides the primary means of communication between developers:

https://lists.berlios.de/mailman/listinfo/openocd-development

All drivers developers are enouraged to also subscribe to the list of SVN commits to keep pace with the ongoing changes:

https://lists.berlios.de/mailman/listinfo/openocd-svn

Building OpenOCD
****************

Pre-Built Tools
===============

If you are interested in getting actual work done rather than building OpenOCD, then check if your interface supplier provides binaries for you. Chances are that that binary is from some SVN version that is more stable than SVN trunk where bleeding edge development takes place.

Packagers Please Read!
======================

You are a PACKAGER of OpenOCD if you

 1. Sell dongles and include pre-built binaries

 2. Supply tools i.e.: A complete development solution

 3. Supply IDEs like Eclipse, or RHIDE, etc.

 4. Build packages i.e.: RPM files, or DEB files for a Linux Distro

As a PACKAGER, you will experience first reports of most issues. When you fix those problems for your users, your solution may help prevent hundreds (if not thousands) of other questions from other users.

If something does not work for you, please work to inform the OpenOCD developers know how to improve the system or documentation to avoid future problems, and follow-up to help us ensure the issue will be fully resolved in our future releases.

That said, the OpenOCD developers would also like you to follow a few suggestions:

 1. Always build with printer ports enabled.

 2. Try to use LIBFTDI + LIBUSB where possible. You cover more bases.

  * Why YES to LIBFTDI + LIBUSB?

       * LESS work - libusb perhaps already there

       * LESS work - identical code, multiple platforms

       * MORE dongles are supported

       * MORE platforms are supported

       * MORE complete solution

  * Why not LIBFTDI + LIBUSB (i.e.: ftd2xx instead)?

       * LESS speed - some say it is slower

       * LESS complex to distribute (external dependencies)

Building From Source
====================

You can download the current SVN version with an SVN client of your choice from the following repositories:

svn://svn.berlios.de/openocd/trunk

or

http://svn.berlios.de/svnroot/repos/openocd/trunk

Using the SVN command line client, you can use the following command to fetch the latest version (make sure there is no (non-svn) directory called "openocd" in the current directory):

      svn checkout svn://svn.berlios.de/openocd/trunk openocd

If you prefer GIT based tools, the git-svn package works too:

      git svn clone -s svn://svn.berlios.de/openocd

Building OpenOCD from a repository requires a recent version of the GNU autotools (autoconf >= 2.59 and automake >= 1.9). For building on Windows, you have to use Cygwin. Make sure that your PATH environment variable contains no other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin paths, resulting in obscure dependency errors (This is an observation I've gathered from the logs of one user - correct me if I'm wrong).

You further need the appropriate driver files, if you want to build support for a FTDI FT2232 based interface:

  * ftdi2232 libftdi (http://www.intra2net.com/opensource/ftdi/)

  * ftd2xx libftd2xx (http://www.ftdichip.com/Drivers/D2XX.htm)

  * When using the Amontec JTAGkey, you have to get the drivers from the Amontec homepage (http://www.amontec.com). The JTAGkey uses a non-standard VID/PID.

libftdi is supported under Windows. Do not use versions earlier than 0.14.

In general, the D2XX driver provides superior performance (several times as fast), but has the draw-back of being binary-only - though that isn't that bad, as it isn't a kernel module, only a user space library.

To build OpenOCD (on both Linux and Cygwin), use the following commands:

      ./bootstrap

Bootstrap generates the configure script, and prepares building on your system.

      ./configure [options, see below]

Configure generates the Makefiles used to build OpenOCD.

      make
      make install

Make builds OpenOCD, and places the final executable in ./src/, the last step, ``make install'' is optional.

The configure script takes several options, specifying which JTAG interfaces should be included (among other things):

  * --enable-parport - Enable building the PC parallel port driver.

  * --enable-parport_ppdev - Enable use of ppdev (/dev/parportN) for parport.

  * --enable-parport_giveio - Enable use of giveio for parport instead of ioperm.

  * --enable-amtjtagaccel - Enable building the Amontec JTAG-Accelerator driver.

  * --enable-ecosboard - Enable building support for eCosBoard based JTAG debugger.

  * --enable-ioutil - Enable ioutil functions - useful for standalone OpenOCD implementations.

  * --enable-httpd - Enable builtin httpd server - useful for standalone OpenOCD implementations.

  * --enable-ep93xx - Enable building support for EP93xx based SBCs.

  * --enable-at91rm9200 - Enable building support for AT91RM9200 based SBCs.

  * --enable-gw16012 - Enable building support for the Gateworks GW16012 JTAG programmer.

  * --enable-ft2232_ftd2xx - Numerous USB type ARM JTAG dongles use the FT2232C chip from this FTDICHIP.COM chip (closed source).

  * --enable-ft2232_libftdi - An open source (free) alternative to FTDICHIP.COM ftd2xx solution (Linux, MacOS, Cygwin).

  * --with-ftd2xx-win32-zipdir=PATH - If using FTDICHIP.COM ft2232c driver, give the directory where the Win32 FTDICHIP.COM 'CDM' driver zip file was unpacked.

  * --with-ftd2xx-linux-tardir=PATH - If using FTDICHIP.COM ft2232c driver on Linux, give the directory where the Linux driver's TAR.GZ file was unpacked.

  * --with-ftd2xx-lib=shared|static - Linux only. Default: static. Specifies how the FTDICHIP.COM libftd2xx driver should be linked. Note: 'static' only works in conjunction with --with-ftd2xx-linux-tardir. The 'shared' value is supported (12/26/2008), however you must manually install the required header files and shared libraries in an appropriate place. This uses ``libusb'' internally.

  * --enable-presto_libftdi - Enable building support for ASIX Presto programmer using the libftdi driver.

  * --enable-presto_ftd2xx - Enable building support for ASIX Presto programmer using the FTD2XX driver.

  * --enable-usbprog - Enable building support for the USBprog JTAG programmer.

  * --enable-oocd_trace - Enable building support for the OpenOCD+trace ETM capture device.

  * --enable-jlink - Enable building support for the Segger J-Link JTAG programmer.

  * --enable-vsllink - Enable building support for the Versaloon-Link JTAG programmer.

  * --enable-rlink - Enable building support for the Raisonance RLink JTAG programmer.

  * --enable-arm-jtag-ew - Enable building support for the Olimex ARM-JTAG-EW programmer.

  * --enable-dummy - Enable building the dummy port driver.

Parallel Port Dongles
=====================

If you want to access the parallel port using the PPDEV interface you have to specify both the --enable-parport AND the --enable-parport_ppdev option since the --enable-parport_ppdev option actually is an option to the parport driver (see http://forum.sparkfun.com/viewtopic.php?t=3795 for more info).

The same is true for the --enable-parport_giveio option, you have to use both the --enable-parport AND the --enable-parport_giveio option if you want to use giveio instead of ioperm parallel port access method.

FT2232C Based USB Dongles
=========================

There are 2 methods of using the FTD2232, either (1) using the FTDICHIP.COM closed source driver, or (2) the open (and free) driver libftdi. Some claim the (closed) FTDICHIP.COM solution is faster.

The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux) TAR.GZ file. You must unpack them ``some where'' convient. As of this writing (12/26/2008) FTDICHIP does not supply means to install these files ``in an appropriate place'' As a result, there are two ``./configure'' options that help.

Below is an example build process:

 1. Check out the latest version of ``openocd'' from SVN.

 2. If you are using the FTDICHIP.COM driver, download and unpack the Windows or Linux FTD2xx drivers (http://www.ftdichip.com/Drivers/D2XX.htm). If you are using the libftdi driver, install that package (e.g. apt-get install libftdi on systems with APT).

          /home/duane/ftd2xx.win32    => the Cygwin/Win32 ZIP file contents
          /home/duane/libftd2xx0.4.16 => the Linux TAR.GZ file contents

 3. Configure with options resembling the following.

      a. Cygwin FTDICHIP solution:

               ./configure --prefix=/home/duane/mytools \
                       --enable-ft2232_ftd2xx \
                       --with-ftd2xx-win32-zipdir=/home/duane/ftd2xx.win32

      b. Linux FTDICHIP solution:

               ./configure --prefix=/home/duane/mytools \
                       --enable-ft2232_ftd2xx \
                       --with-ft2xx-linux-tardir=/home/duane/libftd2xx0.4.16

      c. Cygwin/Linux LIBFTDI solution ... assuming that

            * For Windows -- that the Windows port of LIBUSB is in place.

            * For Linux -- that libusb has been built/installed and is in place.

            * That libftdi has been built and installed (relies on libusb).

          Then configure the libftdi solution like this:

               ./configure --prefix=/home/duane/mytools \
                       --enable-ft2232_libftdi

 4. Then just type ``make'', and perhaps ``make install''.

Miscellaneous Configure Options
===============================

  * --disable-option-checking - Ignore unrecognized --enable and --with options.

  * --enable-gccwarnings - Enable extra gcc warnings during build. Default is enabled.

  * --enable-release - Enable building of an OpenOCD release, generally this is for developers. It simply omits the svn version string when the openocd -v is executed.

JTAG Hardware Dongles
*********************

Defined: dongle: A small device that plugins into a computer and serves as an adapter .... [snip]

In the OpenOCD case, this generally refers to a small adapater one attaches to your computer via USB or the Parallel Printer Port.  The execption being the Zylin ZY1000 which is a small box you attach via an ethernet cable. The Zylin ZY1000 has the advantage that it does not require any drivers to be installed on the developer PC. It also has a built in web interface. It supports RTCK/RCLK or adaptive clocking and has a built in relay to power cycle targets remotely.

Choosing a Dongle
=================

There are three things you should keep in mind when choosing a dongle.

 1. Voltage What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?

 2. Connection Printer Ports - Does your computer have one?

 3. Connection Is that long printer bit-bang cable practical?

 4. RTCK Do you require RTCK? Also known as ``adaptive clocking''

Stand alone Systems
===================

ZY1000 See: http://www.zylin.com/zy1000.html Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does not require any drivers installed on the developer PC. It also has a built in web interface. It supports RTCK/RCLK or adaptive clocking and has a built in relay to power cycle targets remotely.

USB FT2232 Based
================

There are many USB JTAG dongles on the market, many of them are based on a chip from ``Future Technology Devices International'' (FTDI) known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip. See: http://www.ftdichip.com for more information. In summer 2009, USB high speed (480 Mbps) versions of these FTDI chips are starting to become available in JTAG adapters.

As of 28/Nov/2008, the following are supported:

  * usbjtag

      Link http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html

  * jtagkey

      See: http://www.amontec.com/jtagkey.shtml

  * oocdlink

      See: http://www.oocdlink.com By Joern Kaipf

  * signalyzer

      See: http://www.signalyzer.com

  * evb_lm3s811

      See: http://www.luminarymicro.com - The Stellaris LM3S811 eval board has an FTD2232C chip built in.

  * olimex-jtag

      See: http://www.olimex.com

  * flyswatter

      See: http://www.tincantools.com

  * turtelizer2

      See: Turtelizer 2 (http://www.ethernut.de/en/hardware/turtelizer/index.html), or http://www.ethernut.de

  * comstick

      Link: http://www.hitex.com/index.php?id=383

  * stm32stick

      Link http://www.hitex.com/stm32-stick

  * axm0432_jtag

      Axiom AXM-0432 Link http://www.axman.com

  * cortino

      Link http://www.hitex.com/index.php?id=cortino

USB JLINK based
===============

There are several OEM versions of the Segger JLINK adapter. It is an example of a micro controller based JTAG adapter, it uses an AT91SAM764 internally.

  * ATMEL SAMICE Only works with ATMEL chips!

      Link: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892

  * SEGGER JLINK

      Link: http://www.segger.com/jlink.html

  * IAR J-Link

      Link: http://www.iar.com/website1/1.0.1.0/369/1/index.php

USB RLINK based
===============

Raisonance has an adapter called RLink.  It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines.  It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.

  * Raisonance RLink

      Link: http://www.raisonance.com/products/RLink.php

  * STM32 Primer

      Link: http://www.stm32circle.com/resources/stm32primer.php

  * STM32 Primer2

      Link: http://www.stm32circle.com/resources/stm32primer2.php

USB Other
=========

  * USBprog

      Link: http://www.embedded-projects.net/usbprog - which uses an Atmel MEGA32 and a UBN9604

  * USB - Presto

      Link: http://tools.asix.net/prg_presto.htm

  * Versaloon-Link

      Link: http://www.simonqian.com/en/Versaloon

  * ARM-JTAG-EW

      Link: http://www.olimex.com/dev/arm-jtag-ew.html

IBM PC Parallel Printer Port Based
==================================

The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5 and the MacGraigor Wiggler. There are many clones and variations of these on the market.

  * Wiggler - There are many clones of this.

      Link: http://www.macraigor.com/wiggler.htm

  * DLC5 - From XILINX - There are many clones of this

      Link: Search the web for: ``XILINX DLC5'' - it is no longer produced, PDF schematics are easily found and it is easy to make.

  * Amontec - JTAG Accelerator

      Link: http://www.amontec.com/jtag_accelerator.shtml

  * GW16402

      Link: http://www.gateworks.com/products/avila_accessories/gw16042.php

  * Wiggler2

     Improved parallel-port wiggler-style JTAG adapter (http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag)

  * Wiggler_ntrst_inverted

      Yet another variation - See the source code, src/jtag/parport.c

  * old_amt_wiggler

      Unknown - probably not on the market today

  * arm-jtag

      Link: Most likely http://www.olimex.com/dev/arm-jtag.html [another wiggler clone]

  * chameleon

      Link: http://www.amontec.com/chameleon.shtml

  * Triton

      Unknown.

  * Lattice

      ispDownload from Lattice Semiconductor http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf

  * flashlink

      From ST Microsystems; FlashLINK JTAG programing cable for PSD and uPSD (http://www.st.com/stonline/products/literature/um/7889.pdf)

Other...
========

  * ep93xx

      An EP93xx based Linux machine using the GPIO pins directly.

  * at91rm9200

      Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.

Running
*******

The --help option shows:
bash$ openocd --help

--help       | -h       display this help
--version    | -v       display OpenOCD version
--file       | -f       use configuration file <name>
--search     | -s       dir to search for config files and scripts
--debug      | -d       set debug level <0-3>
--log_output | -l       redirect log output to file <name>
--command    | -c       run <command>
--pipe       | -p       use pipes when talking to gdb

By default OpenOCD reads the file configuration file ``openocd.cfg'' in the current directory.  To specify a different (or multiple) configuration file, you can use the ``-f'' option. For example:

       openocd -f config1.cfg -f config2.cfg -f config3.cfg

Once started, OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).

If you are having problems, you can enable internal debug messages via the ``-d'' option.

Also it is possible to interleave commands w/config scripts using the -c command line switch.

To enable debug output (when reporting problems or working on OpenOCD itself), use the -d command line switch. This sets the debug_level to "3", outputting the most information, including debug messages. The default setting is "2", outputting only informational messages, warnings and errors. You can also change this setting from within a telnet or gdb session using debug_level <n> See debug_level.

You can redirect all output from the daemon to a file using the -l <logfile> switch.

Search paths for config/script files can be added to OpenOCD by using the -s <search> switch. The current directory and the OpenOCD target library is in the search path by default.

For details on the -p option. See Connecting to GDB.

Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection with the target. In general, it is possible for the JTAG controller to be unresponsive until the target is set up correctly via e.g. GDB monitor commands in a GDB init script.

Simple Configuration Files
**************************

Outline
=======

There are 4 basic ways of ``configurating'' OpenOCD to run, they are:

 1. A small openocd.cfg file which ``sources'' other configuration files

 2. A monolithic openocd.cfg file

 3. Many -f filename options on the command line

 4. Your Mixed Solution

Small configuration file method
===============================

This is the preferred method. It is simple and works well for many people. The developers of OpenOCD would encourage you to use this method. If you create a new configuration please email new configurations to the development list.

Here is an example of an openocd.cfg file for an ATMEL at91sam7x256

     source [find interface/signalyzer.cfg]

     # GDB can also flash my flash!
     gdb_memory_map enable
     gdb_flash_program enable

     source [find target/sam7x256.cfg]

There are many example configuration scripts you can work with. You should look in the directory: $(INSTALLDIR)/lib/openocd. You should find:

 1. board - eval board level configurations

 2. interface - specific dongle configurations

 3. target - the target chips

 4. tcl - helper scripts

 5. xscale - things specific to the xscale.

Look first in the ``boards'' area, then the ``targets'' area. Often a board configuration is a good example to work from.

Many -f filename options
========================

Some believe this is a wonderful solution, others find it painful.

You can use a series of ``-f filename'' options on the command line, OpenOCD will read each filename in sequence, for example:

     openocd -f file1.cfg -f file2.cfg -f file2.cfg

You can also intermix various commands with the ``-c'' command line option.

Monolithic file
===============

The ``Monolithic File'' dispenses with all ``source'' statements and puts everything in one self contained (monolithic) file. This is not encouraged.

Please try to ``source'' various files or use the multiple -f technique.

Advice for you
==============

Often, one uses a ``mixed approach''. Where possible, please try to ``source'' common things, and if needed cut/paste parts of the standard distribution configuration files as needed.

REMEMBER: The ``important parts'' of your configuration file are:

 1. Interface - Defines the dongle

 2. Taps - Defines the JTAG Taps

 3. GDB Targets - What GDB talks to

 4. Flash Programing - Very Helpful

Some key things you should look at and understand are:

 1. The reset configuration of your debug environment as a whole

 2. Is there a ``work area'' that OpenOCD can use?

      For ARM - work areas mean up to 10x faster downloads.

 3. For MMU/MPU based ARM chips (i.e.: ARM9 and later) will that work area still be available?

 4. For complex targets (multiple chips) the JTAG SPEED becomes an issue.

Config File Guidelines
**********************

This section/chapter is aimed at developers and integrators of OpenOCD. These are guidelines for creating new boards and new target configurations as of 28/Nov/2008.

However, you, the user of OpenOCD, should be somewhat familiar with this section as it should help explain some of the internals of what you might be looking at.

The user should find the following directories under $(INSTALLDIR)/lib/openocd :

  * interface

     Think JTAG Dongle. Files that configure the JTAG dongle go here.

  * board

      Think Circuit Board, PWA, PCB, they go by many names.  Board files contain initialization items that are specific to a board - for example: The SDRAM initialization sequence for the board, or the type of external flash and what address it is found at. Any initialization sequence to enable that external flash or SDRAM should be found in the board file. Boards may also contain multiple targets, i.e.: Two CPUs, or a CPU and an FPGA or CPLD.

  * target

      Think chip. The ``target'' directory represents the JTAG TAPs on a chip which OpenOCD should control, not a board. Two common types of targets are ARM chips and FPGA or CPLD chips. When a chip has multiple TAPs (maybe it has both ARM and DSP cores), the target config file defines all of them.

If needed... The user in their ``openocd.cfg'' file or the board file might override a specific feature in any of the above files by setting a variable or two before sourcing the target file. Or adding various commands specific to their situation.

Interface Config Files
======================

The user should be able to source one of these files via a command like this:

       source [find interface/FOOBAR.cfg]
     Or:
       openocd -f interface/FOOBAR.cfg

A preconfigured interface file should exist for every interface in use today, that said, perhaps some interfaces have only been used by the sole developer who created it.

Interface files should be found in $(INSTALLDIR)/lib/openocd/interface

Board Config Files
==================

Note: BOARD directory NEW as of 28/nov/2008

The user should be able to source one of these files via a command like this:

       source [find board/FOOBAR.cfg]
     Or:
       openocd -f board/FOOBAR.cfg

The board file should contain one or more source [find target/FOO.cfg] statements along with any board specific things.

In summary the board files should contain (if present)

 1. External flash configuration (i.e.: NOR flash on CS0, two NANDs on CS2)

 2. SDRAM configuration (size, speed, etc.

 3. Board specific IO configuration (i.e.: GPIO pins might disable a 2nd flash)

 4. Multiple TARGET source statements

 5. All things that are not ``inside a chip''

 6. Things inside a chip go in a 'target' file

Target Config Files
===================

The user should be able to source one of these files via a command like this:

       source [find target/FOOBAR.cfg]
     Or:
       openocd -f target/FOOBAR.cfg

In summary the target files should contain

 1. Set defaults

 2. Add TAPs to the scan chain

 3. Add CPU targets

 4. Reset configuration

 5. CPU/Chip/CPU-Core specific features

 6. On-Chip flash

Important variable names
------------------------

By default, the end user should never need to set these variables. However, if the user needs to override a setting they only need to set the variable in a simple way.

  * CHIPNAME

      This gives a name to the overall chip, and is used as part of the tap identifier dotted name.

  * ENDIAN

      By default little - unless the chip or board is not normally used that way.

  * CPUTAPID

      When OpenOCD examines the JTAG chain, it will attempt to identify every chip. If the -expected-id is nonzero, OpenOCD attempts to verify the tap id number verses configuration file and may issue an error or warning like this. The hope is that this will help to pinpoint problems in OpenOCD configurations.

          Info:   JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
                          (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
          Error:  ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678,
                          Got: 0x3f0f0f0f
          Error:  ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
          Error:  ERROR:      got: mfg: 0x787, part: 0xf0f0, ver: 0x3

  * _TARGETNAME

      By convention, this variable is created by the target configuration script. The board configuration file may make use of this variable to configure things like a ``reset init'' script, or other things specific to that board and that target.

     If the chip has 2 targets, use the names _TARGETNAME0, _TARGETNAME1, ... etc.

     Remember: The ``board file'' may include multiple targets.

     At no time should the name ``target0'' (the default target name if none was specified) be used. The name ``target0'' is a hard coded name - the next target on the board will be some other number. In the same way, avoid using target numbers even when they are permitted; use the right target name(s) for your board.

     The user (or board file) should reasonably be able to:

             source [find target/FOO.cfg]
             $_TARGETNAME configure ... FOO specific parameters

             source [find target/BAR.cfg]
             $_TARGETNAME configure ... BAR specific parameters

Tcl Variables Guide Line
------------------------

The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.

Thus the rule we follow in OpenOCD is this: Variables that begin with a leading underscore are temporary in nature, and can be modified and used at will within a ?TARGET? configuration file.

EXAMPLE: The user should be able to do this:

        # Board has 3 chips,
        #    PXA270 #1 network side, big endian
        #    PXA270 #2 video side, little endian
        #    Xilinx    Glue logic
        set CHIPNAME network
        set ENDIAN big
        source [find target/pxa270.cfg]
        # variable: _TARGETNAME = network.cpu
        # other commands can refer to the "network.cpu" tap.
        $_TARGETNAME configure .... params for this CPU..

        set ENDIAN little
        set CHIPNAME video
        source [find target/pxa270.cfg]
        # variable: _TARGETNAME = video.cpu
        # other commands can refer to the "video.cpu" tap.
        $_TARGETNAME configure .... params for this CPU..

        unset ENDIAN
        set CHIPNAME xilinx
        source [find target/spartan3.cfg]

        # Since $_TARGETNAME is temporal..
        #  these names still work!
        network.cpu configure ... params
        video.cpu   configure ... params

Default Value Boiler Plate Code
-------------------------------

All target configuration files should start with this (or a modified form)

     # SIMPLE example
     if { [info exists CHIPNAME] } {
        set  _CHIPNAME $CHIPNAME
     } else {
        set  _CHIPNAME sam7x256
     }

     if { [info exists ENDIAN] } {
        set  _ENDIAN $ENDIAN
     } else {
        set  _ENDIAN little
     }

     if { [info exists CPUTAPID ] } {
        set _CPUTAPID $CPUTAPID
     } else {
        set _CPUTAPID 0x3f0f0f0f
     }

Adding TAPs to the Scan Chain
-----------------------------

After the ``defaults'' are set up, add the TAPs on each chip to the JTAG scan chain. See TAP Creation, and the naming convention for taps.

In the simplest case the chip has only one TAP, probably for a CPU or FPGA. The config file for the Atmel AT91SAM7X256 looks (in part) like this:

     jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
             -expected-id $_CPUTAPID

A board with two such at91sam7 chips would be able to source such a config file twice, with different values for CHIPNAME and CPUTAPID, so it adds a different TAP each time.

There are more complex examples too, with chips that have multiple TAPs.  Ones worth looking at include:

  * target/omap3530.cfg -- with a disabled ARM, and a JRC (there's a DSP too, which is not listed)

  * target/str912.cfg -- with flash, CPU, and boundary scan

  * target/ti_dm355.cfg -- with ETM, ARM, and JRC (this JRC is not currently used)

Add CPU targets
---------------

After adding a TAP for a CPU, you should set it up so that GDB and other commands can use it. See CPU Configuration. For the at91sam7 example above, the command can look like this:

     target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME

Work areas are small RAM areas associated with CPU targets. They are used by OpenOCD to speed up downloads, and to download small snippets of code to program flash chips. If the chip includes a form of ``on-chip-ram'' - and many do - define a work area if you can. Again using the at91sam7 as an example, this can look like:

     $_TARGETNAME configure -work-area-phys 0x00200000 \
     	-work-area-size 0x4000 -work-area-backup 0

Reset Configuration
-------------------

Some chips have specific ways the TRST and SRST signals are managed. If these are CHIP SPECIFIC they go here, if they are BOARD SPECIFIC they go in the board file.

ARM Core Specific Hacks
-----------------------

If the chip has a DCC, enable it. If the chip is an ARM9 with some special high speed download features - enable it.

If the chip has an ARM ``vector catch'' feature - by default enable it for Undefined Instructions, Data Abort, and Prefetch Abort, if the user is really writing a handler for those situations - they can easily disable it.  Experiance has shown the ``vector catch'' is helpful - for common programing errors.

If present, the MMU, the MPU and the CACHE should be disabled.

Some ARM cores are equipped with trace support, which permits examination of the instruction and data bus activity.  Trace activity is controlled through an ``Embedded Trace Module'' (ETM) on one of the core's scan chains.  The ETM emits voluminous data through a ``trace port''.  (see ARM Tracing.) If you are using an external trace port, configure it in your board config file. If you are using an on-chip ``Embedded Trace Buffer'' (ETB), configure it in your target config file.

     etm config $_TARGETNAME 16 normal full etb
     etb config $_TARGETNAME $_CHIPNAME.etb

Internal Flash Configuration
----------------------------

This applies ONLY TO MICROCONTROLLERS that have flash built in.

Never ever in the ``target configuration file'' define any type of flash that is external to the chip. (For example a BOOT flash on Chip Select 0.) Such flash information goes in a board file - not the TARGET (chip) file.

Examples:

  * at91sam7x256 - has 256K flash YES enable it.

  * str912 - has flash internal YES enable it.

  * imx27 - uses boot flash on CS0 - it goes in the board file.

  * pxa270 - again - CS0 flash - it goes in the board file.

About JIM-Tcl
*************

OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can learn more about JIM here: http://jim.berlios.de

  * JIM vs. Tcl

      JIM-TCL is a stripped down version of the well known Tcl language, which can be found here: http://www.tcl.tk. JIM-Tcl has far fewer features. JIM-Tcl is a single .C file and a single .H file and impliments the basic Tcl command set along. In contrast: Tcl 8.6 is a 4.2 MB .zip file containing 1540 files.

  * Missing Features

      Our practice has been: Add/clone the real Tcl feature if/when needed. We welcome JIM Tcl improvements, not bloat.

  * Scripts

      OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's command interpreter today (28/nov/2008) is a mixture of (newer) JIM-Tcl commands, and (older) the orginal command interpreter.

  * Commands

      At the OpenOCD telnet command line (or via the GDB mon command) one can type a Tcl for() loop, set variables, etc.

  * Historical Note

      JIM-Tcl was introduced to OpenOCD in spring 2008.

  * Need a crash course in Tcl?

     See Tcl Crash Course.

Daemon Configuration
********************

The commands here are commonly found in the openocd.cfg file and are used to specify what TCP/IP ports are used, and how GDB should be supported.

Configuration Stage
===================

When the OpenOCD server process starts up, it enters a configuration stage which is the only time that certain commands, configuration commands, may be issued. Those configuration commands include declaration of TAPs and other basic setup. The server must leave the configuration stage before it may access or activate TAPs. After it leaves this stage, configuration commands may no longer be issued.

 -- Config Command: init
     This command terminates the configuration stage and enters the normal command mode. This can be useful to add commands to the startup scripts and commands such as resetting the target, programming flash, etc. To reset the CPU upon startup, add "init" and "reset" at the end of the config script or at the end of the OpenOCD command line using the -c command line switch.

     If this command does not appear in any startup/configuration file OpenOCD executes the command for you after processing all configuration files and/or command line options.

     NOTE: This command normally occurs at or near the end of your openocd.cfg file to force OpenOCD to ``initialize'' and make the targets ready. For example: If your openocd.cfg file needs to read/write memory on your target, init must occur before the memory read/write commands.  This includes nand probe.

TCP/IP Ports
============

The OpenOCD server accepts remote commands in several syntaxes. Each syntax uses a different TCP/IP port, which you may specify only during configuration (before those ports are opened).

 -- Command: gdb_port (number)
     Specify or query the first port used for incoming GDB connections. The GDB port for the first target will be gdb_port, the second target will listen on gdb_port + 1, and so on. When not specified during the configuration stage, the port NUMBER defaults to 3333.

 -- Command: tcl_port (number)
     Specify or query the port used for a simplified RPC connection that can be used by clients to issue TCL commands and get the output from the Tcl engine. Intended as a machine interface. When not specified during the configuration stage, the port NUMBER defaults to 6666.

 -- Command: telnet_port (number)
     Specify or query the port on which to listen for incoming telnet connections. This port is intended for interaction with one human through TCL commands. When not specified during the configuration stage, the port NUMBER defaults to 4444.

GDB Configuration
=================

You can reconfigure some GDB behaviors if needed. The ones listed here are static and global. See Target Create, about declaring individual targets. See Target Events, about configuring target-specific event handling.

 -- Command: gdb_breakpoint_override <hard|soft|disable>
     Force breakpoint type for gdb break commands. The raison d'etre for this option is to support GDB GUI's which don't distinguish hard versus soft breakpoints, if the default OpenOCD and GDB behaviour is not sufficient.  GDB normally uses hardware breakpoints if the memory map has been set up for flash regions.

     This option replaces older arm7_9 target commands that addressed the same issue.

 -- Config command: gdb_detach <resume|reset|halt|nothing>
     Configures what OpenOCD will do when GDB detaches from the daemon. Default behaviour is RESUME.

 -- Config command: gdb_flash_program <enable|disable>
     Set to ENABLE to cause OpenOCD to program the flash memory when a vFlash packet is received. The default behaviour is ENABLE.

 -- Config command: gdb_memory_map <enable|disable>
     Set to ENABLE to cause OpenOCD to send the memory configuration to GDB when requested. GDB will then know when to set hardware breakpoints, and program flash using the GDB load command. gdb_flash_program enable must also be enabled for flash programming to work. Default behaviour is ENABLE. See gdb_flash_program.

 -- Config command: gdb_report_data_abort <enable|disable>
     Specifies whether data aborts cause an error to be reported by GDB memory read packets. The default behaviour is DISABLE; use ENABLE see these errors reported.

Interface - Dongle Configuration
********************************

Interface commands are normally found in an interface configuration file which is sourced by your openocd.cfg file. These commands tell OpenOCD what type of JTAG dongle you have and how to talk to it.

Simple Complete Interface Examples
==================================

A Turtelizer FT2232 Based JTAG Dongle
#interface
interface ft2232
ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
ft2232_layout turtelizer2
ft2232_vid_pid 0x0403 0xbdc8
A SEGGER Jlink
# jlink interface
interface jlink
A Raisonance RLink
# rlink interface
interface rlink
Parallel Port
interface parport
parport_port 0xc8b8
parport_cable wiggler
jtag_speed 0
ARM-JTAG-EW
interface arm-jtag-ew

Interface Configuration
=======================

The interface command tells OpenOCD what type of JTAG dongle you are using. Depending on the type of dongle, you may need to have one or more additional commands.

 -- Config Command: interface name
     Use the interface driver NAME to connect to the target.

 -- Command: jtag interface
     Returns the name of the interface driver being used.

Interface Drivers
=================

Currently supported interface drivers are:

  - parport

      PC parallel port bit-banging (Wigglers, PLD download cable, ...)

  - amt_jtagaccel

      Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP mode parallel port

  - ft2232

      FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only FTD2XX driver. The FTD2XX is superior in performance, but not available on every platform. The libftdi uses libusb, and should be portable to all systems that provide libusb.

  - ep93xx

     Cirrus Logic EP93xx based single-board computer bit-banging (in development)

  - presto

      ASIX PRESTO USB JTAG programmer.

  - usbprog

      usbprog is a freely programmable USB adapter.

  - gw16012

      Gateworks GW16012 JTAG programmer.

  - jlink

      Segger jlink USB adapter

  - rlink

      Raisonance RLink USB adapter

  - vsllink

      vsllink is part of Versaloon which is a versatile USB programmer.

  - arm-jtag-ew

      Olimex ARM-JTAG-EW USB adapter

parport options
---------------

  * parport_port <NUMBER>

     Either the address of the I/O port (default: 0x378 for LPT1) or the number of the /dev/parport device

     When using PPDEV to access the parallel port, use the number of the parallel port: parport_port 0 (the default). If parport_port 0x378 is specified you may encounter a problem.

  * parport_cable <NAME>

     The layout of the parallel port cable used to connect to the target. Currently supported cables are

       - wiggler The original Wiggler layout, also supported by several clones, such as the Olimex ARM-JTAG

       - wiggler2 Same as original wiggler except an led is fitted on D5.

       - wiggler_ntrst_inverted Same as original wiggler except TRST is inverted.

       - old_amt_wiggler The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new version available from the website uses the original Wiggler layout ('WIGGLER')

       - chameleon The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.

       - dlc5 The Xilinx Parallel cable III.

       - triton The parallel port adapter found on the 'Karo Triton 1 Development Board'. This is also the layout used by the HollyGates design (see http://www.lartmaker.nl/projects/jtag/).

       - flashlink The ST Parallel cable.

       - arm-jtag Same as original wiggler except SRST and TRST connections reversed and TRST is also inverted.

       - altium Altium Universal JTAG cable.

  * parport_write_on_exit <ON|OFF>

     This will configure the parallel driver to write a known value to the parallel interface on exiting OpenOCD

amt_jtagaccel options
---------------------

  * parport_port <NUMBER>

     Either the address of the I/O port (default: 0x378 for LPT1) or the number of the /dev/parport device

ft2232 options
--------------

  * ft2232_device_desc <DESCRIPTION>

     The USB device description of the FTDI FT2232 device. If not specified, the FTDI default value is used. This setting is only valid if compiled with FTD2XX support.

     TODO: Confirm the following: On Windows the name needs to end with a ``space A''? Or not? It has to do with the FTD2xx driver. When must this be added and when must it not be added? Why can't the code in the interface or in OpenOCD automatically add this if needed? -- Duane.

  * ft2232_serial <SERIAL-NUMBER>

     The serial number of the FTDI FT2232 device. If not specified, the FTDI default values are used.

  * ft2232_layout <NAME>

     The layout of the FT2232 GPIO signals used to control output-enables and reset signals. Valid layouts are

       - usbjtag "USBJTAG-1" layout described in the original OpenOCD diploma thesis

       - jtagkey Amontec JTAGkey and JTAGkey-Tiny

       - signalyzer Signalyzer

       - olimex-jtag Olimex ARM-USB-OCD

       - m5960 American Microsystems M5960

       - evb_lm3s811 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or SRST signals on external connector

       - comstick Hitex STR9 comstick

       - stm32stick Hitex STM32 Performance Stick

       - flyswatter Tin Can Tools Flyswatter

       - turtelizer2 egnite Software turtelizer2

       - oocdlink OOCDLink

       - axm0432_jtag Axiom AXM-0432

       - cortino Hitex Cortino JTAG interface

  * ft2232_vid_pid <VID> <PID>

     The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI default values are used. Multiple <VID>, <PID> pairs may be given, e.g.

          ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003

  * ft2232_latency <MS>

     On some systems using FT2232 based JTAG interfaces the FT_Read function call in ft2232_read() fails to return the expected number of bytes. This can be caused by USB communication delays and has proved hard to reproduce and debug. Setting the FT2232 latency timer to a larger value increases delays for short USB packets but it also reduces the risk of timeouts before receiving the expected number of bytes. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.

JTAG Speed
==========

JTAG clock setup is part of system setup. It does not belong with interface setup since any interface only knows a few of the constraints for the JTAG clock speed. Sometimes the JTAG speed is changed during the target initialization process: (1) slow at reset, (2) program the CPU clocks, (3) run fast. Both the "slow" and "fast" clock rates are functions of the oscillators used, the chip, the board design, and sometimes power management software that may be active.

The speed used during reset can be adjusted using pre_reset and post_reset event handlers. See Target Events.

If your system supports adaptive clocking (RTCK), configuring JTAG to use that is probably the most robust approach. However, it introduces delays to synchronize clocks; so it may not be the fastest solution.

NOTE: Script writers should consider using jtag_rclk instead of jtag_khz.

 -- Command: jtag_khz max_speed_kHz
     A non-zero speed is in KHZ. Hence: 3000 is 3mhz. JTAG interfaces usually support a limited number of speeds.  The speed actually used won't be faster than the speed specified.

     As a rule of thumb, if you specify a clock rate make sure the JTAG clock is no more than 1/6th CPU-Clock. This is especially true for synthesized cores (ARMxxx-S).

     Speed 0 (khz) selects RTCK method. See FAQ RTCK. If your system uses RTCK, you won't need to change the JTAG clocking after setup. Not all interfaces, boards, or targets support ``rtck''. If the interface device can not support it, an error is returned when you try to use RTCK.

 -- Function: jtag_rclk fallback_speed_kHz
     This Tcl proc (defined in startup.tcl) attempts to enable RTCK/RCLK. If that fails (maybe the interface, board, or target doesn't support it), falls back to the specified frequency.

          # Fall back to 3mhz if RTCK is not supported
          jtag_rclk 3000

Reset Configuration
*******************

Every system configuration may require a different reset configuration. This can also be quite confusing. Resets also interact with RESET-INIT event handlers, which do things like setting up clocks and DRAM, and JTAG clock rates.  (see JTAG Speed.) Please see the various board files for examples.

     To maintainers and integrators: Reset configuration touches several things at once. Normally the board configuration file should define it and assume that the JTAG adapter supports everything that's wired up to the board's JTAG connector. However, the target configuration file could also make note of something the silicon vendor has done inside the chip, which will be true for most (or all) boards using that chip. And when the JTAG adapter doesn't support everything, the system configuration file will need to override parts of the reset configuration provided by other files.

Types of Reset
==============

There are many kinds of reset possible through JTAG, but they may not all work with a given board and adapter. That's part of why reset configuration can be error prone.

  * System Reset ... the SRST hardware signal resets all chips connected to the JTAG adapter, such as processors, power management chips, and I/O controllers.  Normally resets triggered with this signal behave exactly like pressing a RESET button.

  * JTAG TAP Reset ... the TRST hardware signal resets just the TAP controllers connected to the JTAG adapter. Such resets should not be visible to the rest of the system; resetting a device's the TAP controller just puts that controller into a known state.

  * Emulation Reset ... many devices can be reset through JTAG commands.  These resets are often distinguishable from system resets, either explicitly (a "reset reason" register says so) or implicitly (not all parts of the chip get reset).

  * Other Resets ... system-on-chip devices often support several other types of reset. You may need to arrange that a watchdog timer stops while debugging, preventing a watchdog reset. There may be individual module resets.

In the best case, OpenOCD can hold SRST, then reset the TAPs via TRST and send commands through JTAG to halt the CPU at the reset vector before the 1st instruction is executed. Then when it finally releases the SRST signal, the system is halted under debugger control before any code has executed. This is the behavior required to support the reset halt and reset init commands; after reset init a board-specific script might do things like setting up DRAM. (see Reset Command.)

SRST and TRST Issues
====================

Because SRST and TRST are hardware signals, they can have a variety of system-specific constraints.  Some of the most common issues are:

  * Signal not available ... Some boards don't wire SRST or TRST to the JTAG connector.  Some JTAG adapters don't support such signals even if they are wired up. Use the reset_config SIGNALS options to say when one of those signals is not connected. When SRST is not available, your code might not be able to rely on controllers having been fully reset during code startup.

  * Signals shorted ... Sometimes a chip, board, or adapter will connect SRST to TRST, instead of keeping them separate. Use the reset_config COMBINATION options to say when those signals aren't properly independent.

  * Timing ... Reset circuitry like a resistor/capacitor delay circuit, reset supervisor, or on-chip features can extend the effect of a JTAG adapter's reset for some time after the adapter stops issuing the reset.  For example, there may be chip or board requirements that all reset pulses last for at least a certain amount of time; and reset buttons commonly have hardware debouncing. Use the jtag_nsrst_delay and jtag_ntrst_delay commands to say when extra delays are needed.

  * Drive type ... Reset lines often have a pullup resistor, letting the JTAG interface treat them as open-drain signals.  But that's not a requirement, so the adapter may need to use push/pull output drivers. Also, with weak pullups it may be advisable to drive signals to both levels (push/pull) to minimize rise times. Use the reset_config TRST_TYPE and SRST_TYPE parameters to say how to drive reset signals.

  * Special initialization ...  Targets sometimes need special JTAG initialization sequences to handle chip-specific issues (not limited to errata). For example, certain JTAG commands might need to be issued while the system as a whole is in a reset state (SRST active) but the JTAG scan chain is usable (TRST inactive). (see JTAG Commands, where the jtag_reset command is presented.)

There can also be other issues. Some devices don't fully conform to the JTAG specifications. Trivial system-specific differences are common, such as SRST and TRST using slightly different names. There are also vendors who distribute key JTAG documentation for their chips only to developers who have signed a Non-Disclosure Agreement (NDA).

Sometimes there are chip-specific extensions like a requirement to use the normally-optional TRST signal (precluding use of JTAG adapters which don't pass TRST through), or needing extra steps to complete a TAP reset.

In short, SRST and especially TRST handling may be very finicky, needing to cope with both architecture and board specific constraints.

Commands for Handling Resets
============================

 -- Command: jtag_nsrst_delay milliseconds
     How long (in milliseconds) OpenOCD should wait after deasserting nSRST (active-low system reset) before starting new JTAG operations. When a board has a reset button connected to SRST line it will probably have hardware debouncing, implying you should use this.

 -- Command: jtag_ntrst_delay milliseconds
     How long (in milliseconds) OpenOCD should wait after deasserting nTRST (active-low JTAG TAP reset) before starting new JTAG operations.

 -- Command: reset_config mode_flag ...
     This command tells OpenOCD the reset configuration of your combination of JTAG board and target in target configuration scripts.

     If you have an interface that does not support SRST and TRST(unlikely), then you may be able to work around that problem by using a reset_config command to override any settings in the target configuration script.

     SRST and TRST has a fairly well understood definition and behaviour in the JTAG specification, but vendors take liberties to achieve various more or less clearly understood goals. Sometimes documentation is available, other times it is not. OpenOCD has the reset_config command to allow OpenOCD to deal with the various common cases.

     The MODE_FLAG options can be specified in any order, but only one of each type -- SIGNALS, COMBINATION, TRST_TYPE, and SRST_TYPE -- may be specified at a time. If you don't provide a new value for a given type, its previous value (perhaps the default) is unchanged. For example, this means that you don't need to say anything at all about TRST just to declare that if the JTAG adapter should want to drive SRST, it must explicitly be driven high (srst_push_pull).

     SIGNALS can specify which of the reset signals are connected. For example, If the JTAG interface provides SRST, but the board doesn't connect that signal properly, then OpenOCD can't use it. Possible values are none (the default), trst_only, srst_only and trst_and_srst.

          If your board provides SRST or TRST through the JTAG connector, you must declare that or else those signals will not be used.

     The COMBINATION is an optional value specifying broken reset signal implementations. The default behaviour if no option given is separate, indicating everything behaves normally. srst_pulls_trst states that the test logic is reset together with the reset of the system (e.g. Philips LPC2000, "broken" board layout), trst_pulls_srst says that the system is reset together with the test logic (only hypothetical, I haven't seen hardware with such a bug, and can be worked around). combined implies both srst_pulls_trst and trst_pulls_srst.

     The optional TRST_TYPE and SRST_TYPE parameters allow the driver mode of each reset line to be specified.  These values only affect JTAG interfaces with support for different driver modes, like the Amontec JTAGkey and JTAGAccelerator.  Also, they are necessarily ignored if the relevant signal (TRST or SRST) is not connected.

     Possible TRST_TYPE driver modes for the test reset signal (TRST) are trst_push_pull (default) and trst_open_drain. Most boards connect this signal to a pulldown, so the JTAG TAPs never leave reset unless they are hooked up to a JTAG adapter.

     Possible SRST_TYPE driver modes for the system reset signal (SRST) are the default srst_open_drain, and srst_push_pull. Most boards connect this signal to a pullup, and allow the signal to be pulled low by various events including system powerup and pressing a reset button.

TAP Creation
************

Test Access Ports (TAPs) are the core of JTAG. TAPs serve many roles, including:

  * Debug Target A CPU TAP can be used as a GDB debug target

  * Flash Programing Some chips program the flash directly via JTAG. Others do it indirectly, making a CPU do it.

  * Program Download Using the same CPU support GDB uses, you can initialize a DRAM controller, download code to DRAM, and then start running that code.

  * Boundary Scan Most chips support boundary scan, which helps test for board assembly problems like solder bridges and missing connections

OpenOCD must know about the active TAPs on your board(s). Setting up the TAPs is the core task of your configuration files. Once those TAPs are set up, you can pass their names to code which sets up CPUs and exports them as GDB targets, probes flash memory, performs low-level JTAG operations, and more.

Scan Chains
===========

OpenOCD uses a JTAG adapter (interface) to talk to your board, which has a daisy chain of TAPs. That daisy chain is called a scan chain. Simple configurations may have a single TAP in the scan chain, perhaps for a microcontroller. Complex configurations might have a dozen or more TAPs: several in one chip, more in the next, and connecting to other boards with their own chips and TAPs.

Unfortunately those TAPs can't always be autoconfigured, because not all devices provide good support for that. (JTAG doesn't require supporting IDCODE instructions.) The configuration mechanism currently supported by OpenOCD requires explicit configuration of all TAP devices using jtag newtap commands. One like this would create a tap named chip1.cpu:

     jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55

Each target configuration file lists the TAPs provided by a given chip. Board configuration files combine all the targets on a board, and so forth. Note that the order in which TAPs are created is very important. It must match the order in the JTAG scan chain, both inside a single chip and between them.

For example, the ST Microsystems STR912 chip has three separate TAPs (See the ST document titled: STR91xFAxxx, Section 3.15 Jtag Interface, Page: 28/102, Figure 3: JTAG chaining inside the STR91xFA. http://eu.st.com/stonline/products/literature/ds/13495.pdf Checked: 28-Nov-2008). To configure those taps, target/str912.cfg includes commands something like this:

     jtag newtap str912 flash ... params ...
     jtag newtap str912 cpu ... params ...
     jtag newtap str912 bs ... params ...

Actual config files use a variable instead of literals like str912, to support more than one chip of each type. See Config File Guidelines.

TAP Names
=========

When a TAP objects is created with jtag newtap, a dotted.name is created for the TAP, combining the name of a module (usually a chip) and a label for the TAP. For example: xilinx.tap, str912.flash, omap3530.jrc, dm6446.dsp, or stm32.cpu. Many other commands use that dotted.name to manipulate or refer to the TAP.  For example, CPU configuration uses the name, as does declaration of NAND or NOR flash banks.

The components of a dotted name should follow ``C'' symbol name rules:  start with an alphabetic character, then numbers and underscores are OK; while others (including dots!) are not.

     In older code, JTAG TAPs were numbered from 0..N. This feature is still present. However its use is highly discouraged, and should not be counted upon. Update all of your scripts to use TAP names rather than numbers. Using TAP numbers in target configuration scripts prevents reusing on boards with multiple targets.

TAP Creation Commands
=====================

 -- Command: jtag newtap chipname tapname configparams...
     Creates a new TAP with the dotted name CHIPNAME.TAPNAME, and configured according to the various CONFIGPARAMS.

     The CHIPNAME is a symbolic name for the chip. Conventionally target config files use $_CHIPNAME, defaulting to the model name given by the chip vendor but overridable.

     The TAPNAME reflects the role of that TAP, and should follow this convention:

       * bs -- For boundary scan if this is a seperate TAP;

       * cpu -- The main CPU of the chip, alternatively arm and dsp on chips with both ARM and DSP CPUs, arm1 and arm2 on chips two ARMs, and so forth;

       * etb -- For an embedded trace buffer (example: an ARM ETB11);

       * flash -- If the chip has a flash TAP, like the str912;

       * jrc -- For JTAG route controller (example: the ICEpick modules on many Texas Instruments chips, like the OMAP3530 on Beagleboards);

       * tap -- Should be used only FPGA or CPLD like devices with a single TAP;

       * unknownN -- If you have no idea what the TAP is for (N is a number);

       * when in doubt -- Use the chip maker's name in their data sheet. For example, the Freescale IMX31 has a SDMA (Smart DMA) with a JTAG TAP; that TAP should be named sdma.

     Every TAP requires at least the following CONFIGPARAMS:

       * -ircapture NUMBER

          The IDCODE capture command, such as 0x01.

       * -irlen NUMBER

          The length in bits of the instruction register, such as 4 or 5 bits.

       * -irmask NUMBER

          A mask for the IR register. For some devices, there are bits in the IR that aren't used. This lets OpenOCD mask them off when doing IDCODE comparisons. In general, this should just be all ones for the size of the IR.

     A TAP may also provide optional CONFIGPARAMS:

       * -disable (or -enable)

          Use the -disable paramater to flag a TAP which is not linked in to the scan chain when it is declared. You may use -enable to highlight the default state (the TAP is linked in). See Enabling and Disabling TAPs.

       * -expected-id NUMBER

          A non-zero value represents the expected 32-bit IDCODE found when the JTAG chain is examined. These codes are not required by all JTAG devices. Repeat the option as many times as required if more than one ID code could appear (for example, multiple versions).

Enabling and Disabling TAPs
===========================

In some systems, a JTAG Route Controller (JRC) is used to enable and/or disable specific JTAG TAPs. Many ARM based chips from Texas Instruments include an ``ICEpick'' module, which is a JRC. Such chips include DaVinci and OMAP3 processors.

A given TAP may not be visible until the JRC has been told to link it into the scan chain; and if the JRC has been told to unlink that TAP, it will no longer be visible. Such routers address problems that JTAG ``bypass mode'' ignores, such as:

  * The scan chain can only go as fast as its slowest TAP.

  * Having many TAPs slows instruction scans, since all TAPs receive new instructions.

  * TAPs in the scan chain must be powered up, which wastes power and prevents debugging some power management mechanisms.

The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap, as implied by the existence of JTAG routers. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG) does include a kind of JTAG router functionality.

 -- Command: jtag cget dotted.name -event name
 -- Command: jtag configure dotted.name -event name string
     At this writing this mechanism is used only for event handling, and the only two events relate to TAP enabling and disabling.

     The configure subcommand assigns an event handler, a TCL string which is evaluated when the event is triggered. The cget subcommand returns that handler. The two possible values for an event NAME are tap-disable and tap-enable.

     So for example, when defining a TAP for a CPU connected to a JTAG router, you should define TAP event handlers using code that looks something like this:

          jtag configure CHIP.cpu -event tap-enable {
            echo "Enabling CPU TAP"
            ... jtag operations using CHIP.jrc
          }
          jtag configure CHIP.cpu -event tap-disable {
            echo "Disabling CPU TAP"
            ... jtag operations using CHIP.jrc
          }

 -- Command: jtag tapdisable dotted.name
 -- Command: jtag tapenable dotted.name
 -- Command: jtag tapisenabled dotted.name
     These three commands all return the string "1" if the tap specified by DOTTED.NAME is enabled, and "0" if it is disbabled. The tapenable variant first enables the tap by sending it a tap-enable event. The tapdisable variant first disables the tap by sending it a tap-disable event.

          Humans will find the scan_chain command more helpful than the script-oriented tapisenabled for querying the state of the JTAG taps.

CPU Configuration
*****************

This chapter discusses how to create a GDB debug target for a CPU. You can also access these targets without GDB (see Architecture and Core Commands) and, where relevant, through various kinds of NAND and NOR flash commands. Also, if you have multiple CPUs you can have multiple such targets.

Before creating a ``target'', you must have added its TAP to the scan chain. When you've added that TAP, you will have a dotted.name which is used to set up the CPU support. The chip-specific configuration file will normally configure its CPU(s) right after it adds all of the chip's TAPs to the scan chain.

targets [NAME]
==============

Note: This command name is PLURAL - not singular.

With NO parameter, this plural targets command lists all known targets in a human friendly form.

With a parameter, this plural targets command sets the current target to the given name. (i.e.: If there are multiple debug targets)

Example:
(gdb) mon targets
      CmdName     Type     Endian    ChainPos   State
--  ---------- ---------- ---------- -------- ----------
    0: target0  arm7tdmi   little        0      halted

target COMMANDS
===============

Note: This command name is SINGULAR - not plural. It is used to manipulate specific targets, to create targets and other things.

Once a target is created, a TARGETNAME (object) command is created; see below for details.

The TARGET command accepts these sub-commands:

  * create .. parameters ..

      creates a new target, see below for details.

  * types

      Lists all supported target types (perhaps some are not yet in this document).

  * names

      Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
     	foreach t [target names] {
     	    puts [format "Target: %s\n" $t]
     	}

  * current

      Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way. By default, commands like: ``mww'' (used to write memory) operate on the current target.

  * number NUMBER

      Internally OpenOCD maintains a list of targets - in numerical index (0..N-1) this command returns the name of the target at index N. Example usage:
         set thename [target number $x]
         puts [format "Target %d is: %s\n" $x $thename]

  * count

      Returns the number of targets known to OpenOCD (see number above) Example:
         set c [target count]
         for { set x 0 } { $x < $c } { incr x } {
            	# Assuming you have created this function
            	print_target_details $x
         }

TARGETNAME (object) commands
============================

Use: Once a target is created, an ``object name'' that represents the target is created. By convention, the target name is identical to the tap name. In a multiple target system, one can precede many common commands with a specific target name and effect only that target.

         str912.cpu    mww 0x1234 0x42
         omap3530.cpu  mww 0x5555 123

Model: The Tcl/Tk language has the concept of object commands. A good example is a on screen button, once a button is created a button has a name (a path in Tk terms) and that name is useable as a 1st class command. For example in Tk, one can create a button and later configure it like this:

         # Create
         button .foobar -background red -command { foo }
         # Modify
         .foobar configure -foreground blue
         # Query
         set x [.foobar cget -background]
         # Report
         puts [format "The button is %s" $x]

In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk button. Commands available as a ``target object'' are:

  * configure - configure the target; see Target Config/Cget Options below

  * cget - query the target configuration; see Target Config/Cget Options below

  * curstate - current target state (running, halt, etc.

  * eventlist

      Intended for a human to see/read the currently configure target events.

  * Various Memory Commands See the ``mww'' command elsewhere.

       * mww ...

       * mwh ...

       * mwb ...

       * mdw ...

       * mdh ...

       * mdb ...

  * Memory To Array, Array To Memory

      These are aimed at a machine interface to memory

       * mem2array ARRAYNAME WIDTH ADDRESS COUNT

       * array2mem ARRAYNAME WIDTH ADDRESS COUNT

           Where:

             ARRAYNAME is the name of an array variable

             WIDTH is 8/16/32 - indicating the memory access size

             ADDRESS is the target memory address

             COUNT is the number of elements to process

  * Used during ``reset''

      These commands are used internally by the OpenOCD scripts to deal with odd reset situations and are not documented here.

       * arp_examine

       * arp_poll

       * arp_reset

       * arp_halt

       * arp_waitstate

  * invoke-event EVENT-NAME

      Invokes the specific event manually for the target

Target Events
=============

At various times, certain things can happen, or you want them to happen.

Examples:

  * What should happen when GDB connects? Should your target reset?

  * When GDB tries to flash the target, do you need to enable the flash via a special command?

  * During reset, do you need to write to certain memory location to reconfigure the SDRAM?

All of the above items are handled by target events.

To specify an event action, either during target creation, or later via ``$_TARGETNAME configure'' see this example.

Syntactially, the option is: ``-event NAME BODY'' where NAME is a target event name, and BODY is a Tcl procedure or string of commands to execute.

The programmers model is the ``-command'' option used in Tcl/Tk buttons and events. Below are two identical examples, the first creates and invokes small procedure. The second inlines the procedure.

        proc my_attach_proc { } {
            puts "RESET...."
            reset halt
        }
        mychip.cpu configure -event gdb-attach my_attach_proc
        mychip.cpu configure -event gdb-attach {
            puts "Reset..."
            reset halt
        }

Current Events
==============

The following events are available:

  * debug-halted

      The target has halted for debug reasons (i.e.: breakpoint)

  * debug-resumed

      The target has resumed (i.e.: gdb said run)

  * early-halted

      Occurs early in the halt process

  * examine-end

      Currently not used (goal: when JTAG examine completes)

  * examine-start

      Currently not used (goal: when JTAG examine starts)

  * gdb-attach

      When GDB connects

  * gdb-detach

      When GDB disconnects

  * gdb-end

      When the taret has halted and GDB is not doing anything (see early halt)

  * gdb-flash-erase-start

      Before the GDB flash process tries to erase the flash

  * gdb-flash-erase-end

      After the GDB flash process has finished erasing the flash

  * gdb-flash-write-start

      Before GDB writes to the flash

  * gdb-flash-write-end

      After GDB writes to the flash

  * gdb-start

      Before the taret steps, gdb is trying to start/resume the target

  * halted

      The target has halted

  * old-gdb_program_config

      DO NOT USE THIS: Used internally

  * old-pre_resume

      DO NOT USE THIS: Used internally

  * reset-assert-pre

      Before reset is asserted on the tap.

  * reset-assert-post

      Reset is now asserted on the tap.

  * reset-deassert-pre

      Reset is about to be released on the tap

  * reset-deassert-post

      Reset has been released on the tap

  * reset-end

      Currently not used.

  * reset-halt-post

      Currently not usd

  * reset-halt-pre

      Currently not used

  * reset-init

      Used by reset init command for board-specific initialization. This is where you would configure PLLs and clocking, set up DRAM so you can download programs that don't fit in on-chip SRAM, set up pin multiplexing, and so on.

  * reset-start

      Currently not used

  * reset-wait-pos

      Currently not used

  * reset-wait-pre

      Currently not used

  * resume-start

      Before any target is resumed

  * resume-end

      After all targets have resumed

  * resume-ok

      Success

  * resumed

      Target has resumed

Target Create
=============

     target create <NAME> <TYPE> <PARAMS ...>

This command creates a GDB debug target that refers to a specific JTAG tap.

  * NAME

      Is the name of the debug target. By convention it should be the tap DOTTED.NAME.  This name is also used to create the target object command, and in other places the target needs to be identified.

  * TYPE

      Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:

       - arm7tdmi

       - arm720t

       - arm9tdmi

       - arm920t

       - arm922t

       - arm926ejs

       - arm966e

       - cortex_m3

       - feroceon

       - xscale

       - arm11

       - mips_m4k

  * PARAMS

     PARAMs are various target configuration parameters. The following ones are mandatory:

       * -endian big|little

       * -chain-position DOTTED.NAME

Target Config/Cget Options
==========================

These options can be specified when the target is created, or later via the configure option or to query the target via cget.

You should specify a working area if you can; typically it uses some on-chip SRAM.  Such a working area can speed up many things, including bulk writes to target memory; flash operations like checking to see if memory needs to be erased; GDB memory checksumming; and may help perform otherwise unavailable operations (like some coprocessor operations on ARM7/9 systems).

  * -type - returns the target type

  * -event NAME BODY see Target events

  * -work-area-virt [ADDRESS] specify/set the work area base address which will be used when an MMU is active.

  * -work-area-phys [ADDRESS] specify/set the work area base address which will be used when an MMU is inactive.

  * -work-area-size [ADDRESS] specify/set the work area

  * -work-area-backup [0|1] does the work area get backed up; by default, it doesn't.  When possible, use a working_area that doesn't need to be backed up, since performing a backup slows down operations.

  * -endian  [big|little]

  * -variant [NAME] some chips have variants OpenOCD needs to know about

  * -chain-position DOTTED.NAME the tap name this target refers to.

Example:

       for { set x 0 } { $x < [target count] } { incr x } {
         set name [target number $x]
         set y [$name cget -endian]
         set z [$name cget -type]
         puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
       }

PROBLEM: On more complex chips, the work area can become inaccessible when application code enables or disables the MMU. For example, the MMU context used to acess the virtual address will probably matter.

Target Variants
===============

  * cortex_m3

      Use variant lm3s when debugging older Stellaris LM3S targets. This will cause OpenOCD to use a software reset rather than asserting SRST, to avoid a issue with clearing the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will be detected and the normal reset behaviour used.

  * xscale

     Supported variants are ixp42x, ixp45x, ixp46x, pxa250, pxa255, pxa26x.

  * mips_m4k

      Use variant ejtag_srst when debugging targets that do not provide a functional SRST line on the EJTAG connector.  This causes OpenOCD to instead use an EJTAG software reset command to reset the processor.  You still need to enable srst on the reset configuration command to enable OpenOCD hardware reset functionality.

Flash Commands
**************

OpenOCD has different commands for NOR and NAND flash; the ``flash'' command works with NOR flash, while the ``nand'' command works with NAND flash. This partially reflects different hardware technologies: NOR flash usually supports direct CPU instruction and data bus access, while data from a NAND flash must be copied to memory before it can be used.  (SPI flash must also be copied to memory before use.) However, the documentation also uses ``flash'' as a generic term; for example, ``Put flash configuration in board-specific files''.

     As of 28-nov-2008 OpenOCD does not know how to program a SPI flash that a micro may boot from. Perhaps you, the reader, would like to contribute support for this.

Flash Steps:

 1. Configure via the command flash bank

      Do this in a board-specific configuration file, passing parameters as needed by the driver.

 2. Operate on the flash via flash subcommand

      Often commands to manipulate the flash are typed by a human, or run via a script in some automated way.  Common tasks include writing a boot loader, operating system, or other data.

 3. GDB Flashing

      Flashing via GDB requires the flash be configured via ``flash bank'', and the GDB flash features be enabled. See GDB Configuration.

Many CPUs have the ablity to ``boot'' from the first flash bank. This means that misprograming that bank can ``brick'' a system, so that it can't boot. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the board by (re)installing working boot firmware.

Flash Configuration Commands
============================

 -- Config Command: flash bank driver base size chip_width bus_width target [driver_options]
     Configures a flash bank which provides persistent storage for addresses from base to base + size - 1. These banks will often be visible to GDB through the target's memory map. In some cases, configuring a flash bank will activate extra commands; see the driver-specific documentation.

       * DRIVER ... identifies the controller driver associated with the flash bank being declared. This is usually cfi for external flash, or else the name of a microcontroller with embedded flash memory. See Flash Driver List.

       * BASE ... Base address of the flash chip.

       * SIZE ... Size of the chip, in bytes. For some drivers, this value is detected from the hardware.

       * CHIP_WIDTH ... Width of the flash chip, in bytes; ignored for most microcontroller drivers.

       * BUS_WIDTH ... Width of the data bus used to access the chip, in bytes; ignored for most microcontroller drivers.

       * TARGET ... Names the target used to issue commands to the flash controller.

       * DRIVER_OPTIONS ... drivers may support, or require, additional parameters.  See the driver-specific documentation for more information.

          This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.

 -- Command: flash banks
     Prints a one-line summary of each device declared using flash bank, numbered from zero. Note that this is the plural form; the singular form is a very different command.

 -- Command: flash probe num
     Identify the flash, or validate the parameters of the configured flash. Operation depends on the flash type. The NUM parameter is a value shown by flash banks. Most flash commands will implicitly autoprobe the bank; flash drivers can distinguish between probing and autoprobing, but most don't bother.

Erasing, Reading, Writing to Flash
==================================

One feature distinguishing NOR flash from NAND or serial flash technologies is that for read access, it acts exactly like any other addressible memory. This means you can use normal memory read commands like mdw or dump_image with it, with no special flash subcommands. See Memory access, and Image access.

Write access works differently.  Flash memory normally needs to be erased before it's written.  Erasing a sector turns all of its bits to ones, and writing can turn ones into zeroes.  This is why there are special commands for interactive erasing and writing, and why GDB needs to know which parts of the address space hold NOR flash memory.

     Most of these erase and write commands leverage the fact that NOR flash chips consume target address space.  They implicitly refer to the current JTAG target, and map from an address in that target's address space back to a flash bank. A few commands use abstract addressing based on bank and sector numbers, and don't depend on searching the current target and its address space. Avoid confusing the two command models.

Some flash chips implement software protection against accidental writes, since such buggy writes could in some cases ``brick'' a system. For such systems, erasing and writing may require sector protection to be disabled first. Examples include CFI flash such as ``Intel Advanced Bootblock flash'', and AT91SAM7 on-chip flash. See flash protect.

 -- Command: flash erase_sector num first last
     Erase sectors in bank NUM, starting at sector FIRST up to and including LAST. Sector numbering starts at 0. The NUM parameter is a value shown by flash banks.

 -- Command: flash erase_address address length
     Erase sectors starting at ADDRESS for LENGTH bytes. The flash bank to use is inferred from the ADDRESS, and the specified length must stay within that bank. As a special case, when LENGTH is zero and ADDRESS is the start of the bank, the whole flash is erased.

 -- Command: flash fillw address word length
 -- Command: flash fillh address halfword length
 -- Command: flash fillb address byte length
     Fills flash memory with the specified WORD (32 bits), HALFWORD (16 bits), or BYTE (8-bit) pattern, starting at ADDRESS and continuing for LENGTH units (word/halfword/byte). No erasure is done before writing; when needed, that must be done before issuing this command. Writes are done in blocks of up to 1024 bytes, and each write is verified by reading back the data and comparing it to what was written. The flash bank to use is inferred from the ADDRESS of each block, and the specified length must stay within that bank.

 -- Command: flash write_bank num filename offset
     Write the binary filename to flash bank NUM, starting at OFFSET bytes from the beginning of the bank. The NUM parameter is a value shown by flash banks.

 -- Command: flash write_image [erase] filename [offset] [type]
     Write the image filename to the current target's flash bank(s). A relocation OFFSET may be specified, in which case it is added to the base address for each section in the image. The file [TYPE] can be specified explicitly as bin (binary), ihex (Intel hex), elf (ELF file), s19 (Motorola s19). mem, or builder. The relevant flash sectors will be erased prior to programming if the erase parameter is given. The flash bank to use is inferred from the ADDRESS of each image segment.

Other Flash commands
====================

 -- Command: flash erase_check num
     Check erase state of sectors in flash bank NUM, and display that status. The NUM parameter is a value shown by flash banks. This is the only operation that updates the erase state information displayed by flash info. That means you have to issue an flash erase_check command after erasing or programming the device to get updated information. (Code execution may have invalidated any state records kept by OpenOCD.)

 -- Command: flash info num
     Print info about flash bank NUM The NUM parameter is a value shown by flash banks. The information includes per-sector protect status.

 -- Command: flash protect num first last (on|off)
     Enable (ON) or disable (OFF) protection of flash sectors FIRST to LAST of flash bank NUM. The NUM parameter is a value shown by flash banks.

 -- Command: flash protect_check num
     Check protection state of sectors in flash bank NUM. The NUM parameter is a value shown by flash banks.

Flash Drivers, Options, and Commands
====================================

As noted above, the flash bank command requires a driver name, and allows driver-specific options and behaviors. Some drivers also activate driver-specific commands.

External Flash
--------------

 -- Flash Driver: cfi
     The ``Common Flash Interface'' (CFI) is the main standard for external NOR flash chips, each of which connects to a specific external chip select on the CPU. Frequently the first such chip is used to boot the system. Your board's reset-init handler might need to configure additional chip selects using other commands (like: mww to configure a bus and its timings) , or perhaps configure a GPIO pin that controls the ``write protect'' pin on the flash chip. The CFI driver can use a target-specific working area to significantly speed up operation.

     The CFI driver can accept the following optional parameters, in any order:

       * JEDEC_PROBE ... is used to detect certain non-CFI flash ROMs, like AM29LV010 and similar types.

       * X16_AS_X8 ...

     To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes) wide on a sixteen bit bus:

          flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
          flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME

Internal Flash (Microcontrollers)
---------------------------------

 -- Flash Driver: aduc702x
     The ADUC702x analog microcontrollers from ST Micro include internal flash and use ARM7TDMI cores. The aduc702x flash driver works with models ADUC7019 through ADUC7028. The setup command only requires the TARGET argument since all devices in this family have the same memory layout.

          flash bank aduc702x 0 0 0 0 $_TARGETNAME

 -- Flash Driver: at91sam7
     All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.

          flash bank at91sam7 0 0 0 0 $_TARGETNAME

     For chips which are not recognized by the controller driver, you must provide additional parameters in the following order:

       * CHIP_MODEL ... label used with flash info

       * BANKS

       * SECTORS_PER_BANK

       * PAGES_PER_SECTOR

       * PAGES_SIZE

       * NUM_NVM_BITS

       * FREQ_KHZ ... required if an external clock is provided, optional (but recommended) when the oscillator frequency is known

     It is recommended that you provide zeroes for all of those values except the clock frequency, so that everything except that frequency will be autoconfigured. Knowing the frequency helps ensure correct timings for flash access.

     The flash controller handles erases automatically on a page (128/256 byte) basis, so explicit erase commands are not necessary for flash programming. However, there is an ``EraseAll`` command that can erase an entire flash plane (of up to 256KB), and it will be used automatically when you issue flash erase_sector or flash erase_address commands.

      -- Command: at91sam7 gpnvm bitnum (set|clear)
          Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM) bit for the processor.   Each processor has a number of such bits, used for controlling features such as brownout detection (so they are not truly general purpose).

               This assumes that the first flash bank (number 0) is associated with the appropriate at91sam7 target.

 -- Flash Driver: avr
     The AVR 8-bit microcontrollers from Atmel integrate flash memory. The current implementation is incomplete.

 -- Flash Driver: ecosflash
     No idea what this is... The ECOSFLASH driver defines one mandatory parameter, the name of a modules of target code which is downloaded and executed.

 -- Flash Driver: lpc2000
     Most members of the LPC2000 microcontroller family from NXP include internal flash and use ARM7TDMI cores. The LPC2000 driver defines two mandatory and one optional parameters, which must appear in the following order:

       * VARIANT ... required, may be LPC2000_V1 (older LPC21xx and LPC22xx) or LPC2000_V2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)

       * CLOCK_KHZ ... the frequency, in kiloHertz, at which the core is running

       * CALC_CHECKSUM ... optional (but you probably want to provide this!), telling the driver to calculate a valid checksum for the exception vector table.

     LPC flashes don't require the chip and bus width to be specified.

          flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
                lpc2000_v2 14765 calc_checksum

 -- Flash Driver: lpc288x
     The LPC2888 microcontroller from NXP needs slightly different flash support from its lpc2000 siblings. The LPC288X driver defines one mandatory parameter, the programming clock rate in Hz. LPC flashes don't require the chip and bus width to be specified.

          flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000

 -- Flash Driver: ocl
     No idea what this is, other than using some arm7/arm9 core.

          flash bank ocl 0 0 0 0 $_TARGETNAME

 -- Flash Driver: pic32mx
     The PIC32MX microcontrollers are based on the MIPS 4K cores, and integrate flash memory. The current implementation is incomplete.

          flash bank pix32mx 0 0 0 0 $_TARGETNAME

     Some pic32mx-specific commands are defined:
      -- Command: pic32mx pgm_word address value bank
          Programs the specified 32-bit VALUE at the given ADDRESS in the specified chip BANK.

 -- Flash Driver: stellaris
     All members of the Stellaris LM3Sxxx microcontroller family from Texas Instruments include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. (Currently there is a stellaris mass_erase command. That seems pointless since the same effect can be had using the standard flash erase_address command.)

          flash bank stellaris 0 0 0 0 $_TARGETNAME

 -- Flash Driver: stm32x
     All members of the STM32 microcontroller family from ST Microelectronics include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.

          flash bank stm32x 0 0 0 0 $_TARGETNAME

     Some stm32x-specific commands (Currently there is a stm32x mass_erase command. That seems pointless since the same effect can be had using the standard flash erase_address command.) are defined:

      -- Command: stm32x lock num
          Locks the entire stm32 device. The NUM parameter is a value shown by flash banks.

      -- Command: stm32x unlock num
          Unlocks the entire stm32 device. The NUM parameter is a value shown by flash banks.

      -- Command: stm32x options_read num
          Read and display the stm32 option bytes written by the stm32x options_write command. The NUM parameter is a value shown by flash banks.

      -- Command: stm32x options_write num (SWWDG|HWWDG) (RSTSTNDBY|NORSTSTNDBY) (RSTSTOP|NORSTSTOP)
          Writes the stm32 option byte with the specified values. The NUM parameter is a value shown by flash banks.

 -- Flash Driver: str7x
     All members of the STR7 microcontroller family from ST Microelectronics include internal flash and use ARM7TDMI cores. The STR7X driver defines one mandatory parameter, VARIANT, which is either STR71x, STR73x or STR75x.

          flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x

 -- Flash Driver: str9x
     Most members of the STR9 microcontroller family from ST Microelectronics include internal flash and use ARM966E cores. The str9 needs the flash controller to be configured using the str9x flash_config command prior to Flash programming.

          flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
          str9x flash_config 0 4 2 0 0x80000

      -- Command: str9x flash_config num bbsr nbbsr bbadr nbbadr
          Configures the str9 flash controller. The NUM parameter is a value shown by flash banks.

            * BBSR - Boot Bank Size register

            * NBBSR - Non Boot Bank Size register

            * BBADR - Boot Bank Start Address register

            * NBBADR - Boot Bank Start Address register

 -- Flash Driver: tms470
     Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. This driver doesn't require the chip and bus width to be specified.

     Some tms470-specific commands are defined:

      -- Command: tms470 flash_keyset key0 key1 key2 key3
          Saves programming keys in a register, to enable flash erase and write commands.

      -- Command: tms470 osc_mhz clock_mhz
          Reports the clock speed, which is used to calculate timings.

      -- Command: tms470 plldis (0|1)
          Disables (1) or enables (0) use of the PLL to speed up the flash clock.

str9xpec driver
---------------

Here is some background info to help you better understand how this driver works. OpenOCD has two flash drivers for the str9:

 1. Standard driver str9x programmed via the str9 core. Normally used for flash programming as it is faster than the str9xpec driver.

 2. Direct programming str9xpec using the flash controller. This is an ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9 core does not need to be running to program using this flash driver. Typical use for this driver is locking/unlocking the target and programming the option bytes.

Before we run any commands using the str9xpec driver we must first disable the str9 core. This example assumes the str9xpec driver has been configured for flash bank 0.

     # assert srst, we do not want core running
     # while accessing str9xpec flash driver
     jtag_reset 0 1
     # turn off target polling
     poll off
     # disable str9 core
     str9xpec enable_turbo 0
     # read option bytes
     str9xpec options_read 0
     # re-enable str9 core
     str9xpec disable_turbo 0
     poll on
     reset halt

The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the str9xpec driver as mentioned above, just issue the commands above manually or from a telnet prompt.

str9xpec driver options
.......................

flash bank str9xpec <BASE> <SIZE> 0 0 <TARGET>

Before using the flash commands the turbo mode must be enabled using str9xpec enable_turbo <NUM>.

Only use this driver for locking/unlocking the device or configuring the option bytes. Use the standard str9 driver for programming.

str9xpec specific commands
..........................

These are flash specific commands when using the str9xpec driver.

  * str9xpec enable_turbo <NUM>

     enable turbo mode, will simply remove the str9 from the chain and talk directly to the embedded flash controller.

  * str9xpec disable_turbo <NUM>

     restore the str9 into JTAG chain.

  * str9xpec lock <NUM>

     lock str9 device. The str9 will only respond to an unlock command that will erase the device.

  * str9xpec unlock <NUM>

     unlock str9 device.

  * str9xpec options_read <NUM>

     read str9 option bytes.

  * str9xpec options_write <NUM>

     write str9 option bytes.

STR9 option byte configuration
..............................

  * str9xpec options_cmap <NUM> <bank0|bank1>

     configure str9 boot bank.

  * str9xpec options_lvdthd <NUM> <2.4v|2.7v>

     configure str9 lvd threshold.

  * str9xpec options_lvdsel <NUM> <vdd|vdd_vddq>

     configure str9 lvd source.

  * str9xpec options_lvdwarn <BANK> <vdd|vdd_vddq>

     configure str9 lvd reset warning source.

mFlash
======

mFlash Configuration
--------------------

mflash bank <SOC> <BASE> <RST PIN> <TARGET>

Configures a mflash for <SOC> host bank at <BASE>. Pin number format is dependent on host GPIO calling convention. Currently, mflash bank support s3c2440 and pxa270.

(ex. of s3c2440) mflash <RST PIN> is GPIO B1.

     mflash bank s3c2440 0x10000000 1b 0

(ex. of pxa270) mflash <RST PIN> is GPIO 43.

     mflash bank pxa270 0x08000000 43 0

mFlash commands
---------------

  * mflash probe

     Probe mflash.

  * mflash write <NUM> <FILE> <OFFSET>

     Write the binary <FILE> to mflash bank <NUM>, starting at <OFFSET> bytes from the beginning of the bank.

  * mflash dump <NUM> <FILE> <OFFSET> <SIZE>

     Dump <size> bytes, starting at <OFFSET> bytes from the beginning of the <NUM> bank to a <FILE>.

  * mflash config pll <FREQUENCY>

     Configure mflash pll. <FREQUENCY> is input frequency of mflash. The order is Hz. Issuing this command will erase mflash's whole internal nand and write new pll. After this command, mflash needs power-on-reset for normal operation. If pll was newly configured, storage and boot(optional) info also need to be update.

  * mflash config boot

     Configure bootable option. If bootable option is set, mflash offer the first 8 sectors (4kB) for boot.

  * mflash config storage

     Configure storage information. For the normal storage operation, this information must be written.

NAND Flash Commands
*******************

Compared to NOR or SPI flash, NAND devices are inexpensive and high density.  Today's NAND chips, and multi-chip modules, commonly hold multiple GigaBytes of data.

NAND chips consist of a number of ``erase blocks'' of a given size (such as 128 KBytes), each of which is divided into a number of pages (of perhaps 512 or 2048 bytes each).  Each page of a NAND flash has an ``out of band'' (OOB) area to hold Error Correcting Code (ECC) and other metadata, usually 16 bytes of OOB for every 512 bytes of page data.

One key characteristic of NAND flash is that its error rate is higher than that of NOR flash.  In normal operation, that ECC is used to correct and detect errors.  However, NAND blocks can also wear out and become unusable; those blocks are then marked "bad".  NAND chips are even shipped from the manufacturer with a few bad blocks.  The highest density chips use a technology (MLC) that wears out more quickly, so ECC support is increasingly important as a way to detect blocks that have begun to fail, and help to preserve data integrity with techniques such as wear leveling.

Software is used to manage the ECC.  Some controllers don't support ECC directly; in those cases, software ECC is used. Other controllers speed up the ECC calculations with hardware. Single-bit error correction hardware is routine.  Controllers geared for newer MLC chips may correct 4 or more errors for every 512 bytes of data.

You will need to make sure that any data you write using OpenOCD includes the apppropriate kind of ECC.  For example, that may mean passing the oob_softecc flag when writing NAND data, or ensuring that the correct hardware ECC mode is used.

The basic steps for using NAND devices include:

 1. Declare via the command nand device

      Do this in a board-specific configuration file, passing parameters as needed by the controller.

 2. Configure each device using nand probe.

      Do this only after the associated target is set up, such as in its reset-init script or in procures defined to access that device.

 3. Operate on the flash via nand subcommand

      Often commands to manipulate the flash are typed by a human, or run via a script in some automated way.  Common task include writing a boot loader, operating system, or other data needed to initialize or de-brick a board.

NOTE: At the time this text was written, the largest NAND flash fully supported by OpenOCD is 2 GiBytes (16 GiBits). This is because the variables used to hold offsets and lengths are only 32 bits wide. (Larger chips may work in some cases, unless an offset or length is larger than 0xffffffff, the largest 32-bit unsigned integer.) Some larger devices will work, since they are actually multi-chip modules with two smaller chips and individual chipselect lines.

NAND Configuration Commands
===========================

NAND chips must be declared in configuration scripts, plus some additional configuration that's done after OpenOCD has initialized.

 -- Config Command: nand device controller target [configparams...]
     Declares a NAND device, which can be read and written to after it has been configured through nand probe. In OpenOCD, devices are single chips; this is unlike some operating systems, which may manage multiple chips as if they were a single (larger) device. In some cases, configuring a device will activate extra commands; see the controller-specific documentation.

     NOTE: This command is not available after OpenOCD initialization has completed.  Use it in board specific configuration files, not interactively.

       * CONTROLLER ... identifies the controller driver associated with the NAND device being declared. See NAND Driver List.

       * TARGET ... names the target used when issuing commands to the NAND controller.

       * CONFIGPARAMS ... controllers may support, or require, additional parameters.  See the controller-specific documentation for more information.

 -- Command: nand list
     Prints a one-line summary of each device declared using nand device, numbered from zero. Note that un-probed devices show no details.

 -- Command: nand probe num
     Probes the specified device to determine key characteristics like its page and block sizes, and how many blocks it has. The NUM parameter is the value shown by nand list. You must (successfully) probe a device before you can use it with most other NAND commands.

Erasing, Reading, Writing to NAND Flash
=======================================

 -- Command: nand dump num filename offset length [oob_option]
     Reads binary data from the NAND device and writes it to the file, starting at the specified offset. The NUM parameter is the value shown by nand list.

     Use a complete path name for FILENAME, so you don't depend on the directory used to start the OpenOCD server.

     The OFFSET and LENGTH must be exact multiples of the device's page size.  They describe a data region; the OOB data associated with each such page may also be accessed.

     NOTE: At the time this text was written, no error correction was done on the data that's read, unless raw access was disabled and the underlying NAND controller driver had a read_page method which handled that error correction.

     By default, only page data is saved to the specified file. Use an OOB_OPTION parameter to save OOB data:

       * no oob_* parameter

          Output file holds only page data; OOB is discarded.

       * oob_raw

          Output file interleaves page data and OOB data; the file will be longer than "length" by the size of the spare areas associated with each data page. Note that this kind of "raw" access is different from what's implied by nand raw_access, which just controls whether a hardware-aware access method is used.

       * oob_only

          Output file has only raw OOB data, and will be smaller than "length" since it will contain only the spare areas associated with each data page.

 -- Command: nand erase num offset length
     Erases blocks on the specified NAND device, starting at the specified OFFSET and continuing for LENGTH bytes. Both of those values must be exact multiples of the device's block size, and the region they specify must fit entirely in the chip. The NUM parameter is the value shown by nand list.

     NOTE: This command will try to erase bad blocks, when told to do so, which will probably invalidate the manufacturer's bad block marker. For the remainder of the current server session, nand info will still report that the block ``is'' bad.

 -- Command: nand write num filename offset [option...]
     Writes binary data from the file into the specified NAND device, starting at the specified offset.  Those pages should already have been erased; you can't change zero bits to one bits. The NUM parameter is the value shown by nand list.

     Use a complete path name for FILENAME, so you don't depend on the directory used to start the OpenOCD server.

     The OFFSET must be an exact multiple of the device's page size. All data in the file will be written, assuming it doesn't run past the end of the device. Only full pages are written, and any extra space in the last page will be filled with 0xff bytes.  (That includes OOB data, if that's being written.)

     NOTE: At the time this text was written, bad blocks are ignored.  That is, this routine will not skip bad blocks, but will instead try to write them.  This can cause problems.

     Provide at most one OPTION parameter.  With some NAND drivers, the meanings of these parameters may change if nand raw_access was used to disable hardware ECC.

       * no oob_* parameter

          File has only page data, which is written. If raw acccess is in use, the OOB area will not be written. Otherwise, if the underlying NAND controller driver has a write_page routine, that routine may write the OOB with hardware-computed ECC data.

       * oob_only

          File has only raw OOB data, which is written to the OOB area. Each page's data area stays untouched.  This can be a dangerous option, since it can invalidate the ECC data. You may need to force raw access to use this mode.

       * oob_raw

          File interleaves data and OOB data, both of which are written If raw access is enabled, the data is written first, then the un-altered OOB. Otherwise, if the underlying NAND controller driver has a write_page routine, that routine may modify the OOB before it's written, to include hardware-computed ECC data.

       * oob_softecc

          File has only page data, which is written. The OOB area is filled with 0xff, except for a standard 1-bit software ECC code stored in conventional locations. You might need to force raw access to use this mode, to prevent the underlying driver from applying hardware ECC.

       * oob_softecc_kw

          File has only page data, which is written. The OOB area is filled with 0xff, except for a 4-bit software ECC specific to the boot ROM in Marvell Kirkwood SoCs. You might need to force raw access to use this mode, to prevent the underlying driver from applying hardware ECC.

Other NAND commands
===================

 -- Command: nand check_bad_blocks [offset length]
     Checks for manufacturer bad block markers on the specified NAND device.  If no parameters are provided, checks the whole device; otherwise, starts at the specified OFFSET and continues for LENGTH bytes. Both of those values must be exact multiples of the device's block size, and the region they specify must fit entirely in the chip. The NUM parameter is the value shown by nand list.

     NOTE: Before using this command you should force raw access with nand raw_access enable to ensure that the underlying driver will not try to apply hardware ECC.

 -- Command: nand info num
     The NUM parameter is the value shown by nand list. This prints the one-line summary from "nand list", plus for devices which have been probed this also prints any known status for each block.

 -- Command: nand raw_access num <enable|disable>
     Sets or clears an flag affecting how page I/O is done. The NUM parameter is the value shown by nand list.

     This flag is cleared (disabled) by default, but changing that value won't affect all NAND devices.  The key factor is whether the underlying driver provides read_page or write_page methods.  If it doesn't provide those methods, the setting of this flag is irrelevant; all access is effectively ``raw''.

     When those methods exist, they are normally used when reading data (nand dump or reading bad block markers) or writing it (nand write).  However, enabling raw access (setting the flag) prevents use of those methods, bypassing hardware ECC logic. This can be a dangerous option, since writing blocks with the wrong ECC data can cause them to be marked as bad.

NAND Drivers, Options, and Commands
===================================

As noted above, the nand device command allows driver-specific options and behaviors. Some controllers also activate controller-specific commands.

 -- NAND Driver: davinci
     This driver handles the NAND controllers found on DaVinci family chips from Texas Instruments. It takes three extra parameters: address of the NAND chip; hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix); address of the AEMIF controller on this processor.

          nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000

     All DaVinci processors support the single-bit ECC hardware, and newer ones also support the four-bit ECC hardware. The write_page and read_page methods are used to implement those ECC modes, unless they are disabled using the nand raw_access command.

 -- NAND Driver: lpc3180
     These controllers require an extra nand device parameter:  the clock rate used by the controller.
      -- Command: lpc3180 select num [mlc|slc]
          Configures use of the MLC or SLC controller mode. MLC implies use of hardware ECC. The NUM parameter is the value shown by nand list.

     At this writing, this driver includes write_page and read_page methods.  Using nand raw_access to disable those methods will prevent use of hardware ECC in the MLC controller mode, but won't change SLC behavior.

 -- NAND Driver: orion
     These controllers require an extra nand device parameter:  the address of the controller.

          nand device orion 0xd8000000

     These controllers don't define any specialized commands. At this writing, their drivers don't include write_page or read_page methods, so nand raw_access won't change any behavior.

 -- NAND Driver: s3c2410
 -- NAND Driver: s3c2412
 -- NAND Driver: s3c2440
 -- NAND Driver: s3c2443
     These S3C24xx family controllers don't have any special nand device options, and don't define any specialized commands. At this writing, their drivers don't include write_page or read_page methods, so nand raw_access won't change any behavior.

General Commands
****************

The commands documented in this chapter here are common commands that you, as a human, may want to type and see the output of. Configuration type commands are documented elsewhere.

Intent:

  * Source Of Commands

      OpenOCD commands can occur in a configuration script (discussed elsewhere) or typed manually by a human or supplied programatically, or via one of several TCP/IP Ports.

  * From the human

      A human should interact with the telnet interface (default port: 4444) or via GDB (default port 3333).

     To issue commands from within a GDB session, use the monitor command, e.g. use monitor poll to issue the poll command. All output is relayed through the GDB session.

  * Machine Interface The Tcl interface's intent is to be a machine interface. The default Tcl port is 5555.

Daemon Commands
===============

sleep [MSEC]
------------

Wait for n milliseconds before resuming. Useful in connection with script files (SCRIPT command and TARGET_SCRIPT configuration).

shutdown
--------

Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).

debug_level [N]
---------------

Display or adjust debug level to n<0-3>

fast [ENABLE|DISABLE]
---------------------

Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory downloads and fast memory access will work if the JTAG interface isn't too fast and the core doesn't run at a too low frequency. Note that this option only changes the default and that the indvidual options, like DCC memory downloads, can be enabled and disabled individually.

The target specific "dangerous" optimisation tweaking options may come and go as more robust and user friendly ways are found to ensure maximum throughput and robustness with a minimum of configuration.

Typically the "fast enable" is specified first on the command line:

     openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg

echo <MESSAGE>
--------------

Output message to stdio. e.g. echo "Programming - please wait"

log_output <FILE>
-----------------

Redirect logging to <file> (default: stderr)

script <FILE>
-------------

Execute commands from <file> See also: ``source [find FILENAME]''

Target state handling
=====================

power <ON|OFF>
--------------

Turn power switch to target on/off. No arguments: print status. Not all interfaces support this.

reg [#|name] [value]
--------------------

Access a single register by its number[#] or by its [name]. No arguments: list all available registers for the current target. Number or name argument: display a register. Number or name and value arguments: set register value.

poll [on|off]
-------------

Poll the target for its current state. If the target is in debug mode, architecture specific information about the current state is printed. An optional parameter allows continuous polling to be enabled and disabled.

halt [ms]
---------

Send a halt request to the target and wait for it to halt for up to [ms] milliseconds. Default [ms] is 5 seconds if no arg given. Optional arg ms is a timeout in milliseconds. Using 0 as the [ms] will stop OpenOCD from waiting.

wait_halt [ms]
--------------

Wait for the target to enter debug mode. Optional [ms] is a timeout in milliseconds. Default [ms] is 5 seconds if no arg is given.

resume [ADDRESS]
----------------

Resume the target at its current code position, or at an optional address. OpenOCD will wait 5 seconds for the target to resume.

step [ADDRESS]
--------------

Single-step the target at its current code position, or at an optional address.

reset [run|halt|init]
---------------------

Perform a hard-reset. The optional parameter specifies what should happen after the reset. If there is no parameter, a reset run is executed. The other options will not work on all systems. See Reset Configuration.

  - run

     Let the target run.

  - halt

     Immediately halt the target (works only with certain configurations).

  - init

     Immediately halt the target, and execute the reset script (works only with certain configurations)

soft_reset_halt
---------------

Requesting target halt and executing a soft reset. This is often used when a target cannot be reset and halted. The target, after reset is released begins to execute code. OpenOCD attempts to stop the CPU and then sets the program counter back to the reset vector. Unfortunately the code that was executed may have left the hardware in an unknown state.

Memory access commands
======================

meminfo
-------

display available RAM memory on OpenOCD host. Used in OpenOCD regression testing scripts. Mainly useful on embedded targets, PC type hosts have complimentary tools like Valgrind to address resource tracking problems.

Memory peek/poke type commands
------------------------------

These commands allow accesses of a specific size to the memory system. Often these are used to configure the current target in some special way. For example - one may need to write certian values to the SDRAM controller to enable SDRAM.

 1. To change the current target see the ``targets'' (plural) command

 2. In system level scripts these commands are deprecated, please use the TARGET object versions.

  * mdw <ADDR> [COUNT]

     display memory words (32bit)

  * mdh <ADDR> [COUNT]

     display memory half-words (16bit)

  * mdb <ADDR> [COUNT]

     display memory bytes (8bit)

  * mww <ADDR> <VALUE>

     write memory word (32bit)

  * mwh <ADDR> <VALUE>

     write memory half-word (16bit)

  * mwb <ADDR> <VALUE>

     write memory byte (8bit)

Image loading commands
======================

load_image
----------

load_image <FILE> <ADDRESS> [bin|ihex|elf]

Load image <FILE> to target memory at <ADDRESS>

fast_load_image
---------------

fast_load_image <FILE> <ADDRESS> [bin|ihex|elf]

Normally you should be using load_image or GDB load. However, for testing purposes or when I/O overhead is significant(OpenOCD running on an embedded host), storing the image in memory and uploading the image to the target can be a way to upload e.g. multiple debug sessions when the binary does not change. Arguments are the same as load_image, but the image is stored in OpenOCD host memory, i.e. does not affect target.  This approach is also useful when profiling target programming performance as I/O and target programming can easily be profiled separately.

fast_load
---------

fast_load

Loads an image stored in memory by fast_load_image to the current target. Must be preceeded by fast_load_image.

dump_image
----------

dump_image <FILE> <ADDRESS> <SIZE>

Dump <SIZE> bytes of target memory starting at <ADDRESS> to a (binary) <FILE>.

verify_image
------------

verify_image <FILE> <ADDRESS> [bin|ihex|elf]

Verify <FILE> against target memory starting at <ADDRESS>. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.

Breakpoint commands
===================

  * bp <ADDR> <LEN> [HW]

     set breakpoint <address> <length> [hw]

  * rbp <ADDR>

     remove breakpoint <adress>

  * wp <ADDR> <LEN> <R|W|A> [VALUE] [MASK]

     set watchpoint <address> <length> <r/w/a> [value] [mask]

  * rwp <ADDR>

     remove watchpoint <adress>

Misc Commands
=============

  * profile <SECONDS> <GMON.OUT>

     Profiling samples the CPU's program counter as quickly as possible, which is useful for non-intrusive stochastic profiling.

Architecture and Core Commands
******************************

Most CPUs have specialized JTAG operations to support debugging. OpenOCD packages most such operations in its standard command framework. Some of those operations don't fit well in that framework, so they are exposed here as architecture or implementation (core) specific commands.

ARM Tracing
===========

CPUs based on ARM cores may include standard tracing interfaces, based on an ``Embedded Trace Module'' (ETM) which sends voluminous address and data bus trace records to a ``Trace Port''.

  * Development-oriented boards will sometimes provide a high speed trace connector for collecting that data, when the particular CPU supports such an interface. (The standard connector is a 38-pin Mictor, with both JTAG and trace port support.) Those trace connectors are supported by higher end JTAG adapters and some logic analyzer modules; frequently those modules can buffer several megabytes of trace data. Configuring an ETM coupled to such an external trace port belongs in the board-specific configuration file.

  * If the CPU doesn't provide an external interface, it probably has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a dedicated SRAM.  4KBytes is one common ETB size. Configuring an ETM coupled only to an ETB belongs in the CPU-specific (target) configuration file, since it works the same on all boards.

ETM support in OpenOCD doesn't seem to be widely used yet.

     ETM support may be buggy, and at least some etm config parameters should be detected by asking the ETM for them. It seems like a GDB hookup should be possible, as well as triggering trace on specific events (perhaps handling IRQ 23 or calls foo()). There should be GUI tools to manipulate saved trace data and help analyse it in conjunction with the source code. It's unclear how much of a common interface is shared with the current XScale trace support, or should be shared with eventual Nexus-style trace module support.

ETM Configuration
-----------------

ETM setup is coupled with the trace port driver configuration.

 -- Config Command: etm config target width mode clocking driver
     Declares the ETM associated with TARGET, and associates it with a given trace port DRIVER.  See Trace Port Drivers.

     Several of the parameters must reflect the trace port configuration. The WIDTH must be either 4, 8, or 16. The MODE must be normal, multiplexted, or demultiplexted. The CLOCKING must be half or full.

          You can see the ETM registers using the reg command, although not all of those possible registers are present in every ETM.

 -- Command: etm info
     Displays information about the current target's ETM.

 -- Command: etm status
     Displays status of the current target's ETM: is the ETM idle, or is it collecting data? Did trace data overflow? Was it triggered?

 -- Command: etm tracemode [type context_id_bits cycle_accurate branch_output]
     Displays what data that ETM will collect. If arguments are provided, first configures that data. When the configuration changes, tracing is stopped and any buffered trace data is invalidated.

       * TYPE ... one of none (save nothing), data (save data), address (save addresses), all (save data and addresses)

       * CONTEXT_ID_BITS ... 0, 8, 16, or 32

       * CYCLE_ACCURATE ...  enable or disable

       * BRANCH_OUTPUT ...  enable or disable

 -- Command: etm trigger_percent percent
     Buggy and effectively a NOP ... PERCENT from 2..100

ETM Trace Operation
-------------------

After setting up the ETM, you can use it to collect data. That data can be exported to files for later analysis. It can also be parsed with OpenOCD, for basic sanity checking.

 -- Command: etm analyze
     Reads trace data into memory, if it wasn't already present. Decodes and prints the data that was collected.

 -- Command: etm dump filename
     Stores the captured trace data in filename.

 -- Command: etm image filename [base_address] [type]
     Opens an image file.

 -- Command: etm load filename
     Loads captured trace data from filename.

 -- Command: etm start
     Starts trace data collection.

 -- Command: etm stop
     Stops trace data collection.

Trace Port Drivers
------------------

To use an ETM trace port it must be associated with a driver.

 -- Trace Port Driver: dummy
     Use the dummy driver if you are configuring an ETM that's not connected to anything (on-chip ETB or off-chip trace connector). This driver lets OpenOCD talk to the ETM, but it does not expose any trace data collection.
      -- Config Command: etm_dummy config target
          Associates the ETM for TARGET with a dummy driver.

 -- Trace Port Driver: etb
     Use the etb driver if you are configuring an ETM to use on-chip ETB memory.
      -- Config Command: etb config target etb_tap
          Associates the ETM for TARGET with the ETB at ETB_TAP. You can see the ETB registers using the reg command.

 -- Trace Port Driver: oocd_trace
     This driver isn't available unless OpenOCD was explicitly configured with the --enable-oocd_trace option.  You probably don't want to configure it unless you've built the appropriate prototype hardware; it's proof-of-concept software.

     Use the oocd_trace driver if you are configuring an ETM that's connected to an off-chip trace connector.

      -- Config Command: oocd_trace config target tty
          Associates the ETM for TARGET with a trace driver which collects data through the serial port TTY.

      -- Command: oocd_trace resync
          Re-synchronizes with the capture clock.

      -- Command: oocd_trace status
          Reports whether the capture clock is locked or not.

ARMv4 and ARMv5 Architecture
============================

These commands are specific to ARM architecture v4 and v5, including all ARM7 or ARM9 systems and Intel XScale. They are available in addition to other core-specific commands that may be available.

 -- Command: armv4_5 core_state [arm|thumb]
     Displays the core_state, optionally changing it to process either arm or thumb instructions. The target may later be resumed in the currently set core_state. (Processors may also support the Jazelle state, but that is not currently supported in OpenOCD.)

 -- Command: armv4_5 disassemble address count [thumb]
     Disassembles COUNT instructions starting at ADDRESS. If thumb is specified, Thumb (16-bit) instructions are used; else ARM (32-bit) instructions are used. (Processors may also support the Jazelle state, but those instructions are not currently understood by OpenOCD.)

 -- Command: armv4_5 reg
     Display a list of all banked core registers, fetching the current value from every core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current register value.

ARM7 and ARM9 specific commands
-------------------------------

These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T, ARM9TDMI, ARM920T or ARM926EJ-S. They are available in addition to the ARMv4/5 commands, and any other core-specific commands that may be available.

 -- Command: arm7_9 dbgrq (enable|disable)
     Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode, instead of breakpoints.  This should be safe for all but ARM7TDMI--S cores (like Philips LPC).

 -- Command: arm7_9 dcc_downloads (enable|disable)
     Control the use of the debug communications channel (DCC) to write larger (>128 byte) amounts of memory. DCC downloads offer a huge speed increase, but might be unsafe, especially with targets running at very low speeds. This command was introduced with OpenOCD rev. 60, and requires a few bytes of working area.

 -- Command: arm7_9 fast_memory_access (enable|disable)
     Enable or disable memory writes and reads that don't check completion of the operation. This provides a huge speed increase, especially with USB JTAG cables (FT2232), but might be unsafe if used with targets running at very low speeds, like the 32kHz startup clock of an AT91RM9200.

 -- Debug Command: arm7_9 write_core_reg num mode word
     This is intended for use while debugging OpenOCD; you probably shouldn't use it.

     Writes a 32-bit WORD to register NUM (from 0 to 16) as used in the specified MODE (where e.g. mode 16 is "user" and mode 19 is "supervisor"; the M4..M0 bits of the PSR). Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15). Register 16 is the mode-specific SPSR, unless the specified mode is 0xffffffff (32-bit all-ones) in which case register 16 is the CPSR. The write goes directly to the CPU, bypassing the register cache.

 -- Debug Command: arm7_9 write_xpsr word (0|1)
     This is intended for use while debugging OpenOCD; you probably shouldn't use it.

     If the second parameter is zero, writes WORD to the Current Program Status register (CPSR). Else writes WORD to the current mode's Saved PSR (SPSR). In both cases, this bypasses the register cache.

 -- Debug Command: arm7_9 write_xpsr_im8 byte rotate (0|1)
     This is intended for use while debugging OpenOCD; you probably shouldn't use it.

     Writes eight bits to the CPSR or SPSR, first rotating them by 2*rotate bits, and bypassing the register cache. This has lower JTAG overhead than writing the entire CPSR or SPSR with arm7_9 write_xpsr.

ARM720T specific commands
-------------------------

These commands are available to ARM720T based CPUs, which are implementations of the ARMv4T architecture based on the ARM7TDMI-S integer core. They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.

 -- Command: arm720t cp15 regnum [value]
     Display cp15 register REGNUM; else if a VALUE is provided, that value is written to that register.

 -- Command: arm720t mdw_phys addr [count]
 -- Command: arm720t mdh_phys addr [count]
 -- Command: arm720t mdb_phys addr [count]
     Display contents of physical address ADDR, as 32-bit words (mdw_phys), 16-bit halfwords (mdh_phys), or 8-bit bytes (mdb_phys). If COUNT is specified, displays that many units.

 -- Command: arm720t mww_phys addr word
 -- Command: arm720t mwh_phys addr halfword
 -- Command: arm720t mwb_phys addr byte
     Writes the specified WORD (32 bits), HALFWORD (16 bits), or BYTE (8-bit) pattern, at the specified physical address ADDR.

 -- Command: arm720t virt2phys va
     Translate a virtual address VA to a physical address and display the result.

ARM9TDMI specific commands
--------------------------

Many ARM9-family CPUs are built around ARM9TDMI integer cores, or processors resembling ARM9TDMI, and can use these commands. Such cores include the ARM920T, ARM926EJ-S, and ARM966.

 -- Command: arm9tdmi vector_catch (all|none|list)
     Catch arm9 interrupt vectors, can be all, none, or a list with one or more of the following: reset undef swi pabt dabt reserved irq fiq.

ARM920T specific commands
-------------------------

These commands are available to ARM920T based CPUs, which are implementations of the ARMv4T architecture built using the ARM9TDMI integer core. They are available in addition to the ARMv4/5, ARM7/ARM9, and ARM9TDMI commands.

 -- Command: arm920t cache_info
     Print information about the caches found. This allows to see whether your target is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).

 -- Command: arm920t cp15 regnum [value]
     Display cp15 register REGNUM; else if a VALUE is provided, that value is written to that register.

 -- Command: arm920t cp15i opcode [value [address]]
     Interpreted access using cp15 OPCODE. If no VALUE is provided, the result is displayed. Else if that value is written using the specified ADDRESS, or using zero if no other address is not provided.

 -- Command: arm920t mdw_phys addr [count]
 -- Command: arm920t mdh_phys addr [count]
 -- Command: arm920t mdb_phys addr [count]
     Display contents of physical address ADDR, as 32-bit words (mdw_phys), 16-bit halfwords (mdh_phys), or 8-bit bytes (mdb_phys). If COUNT is specified, displays that many units.

 -- Command: arm920t mww_phys addr word
 -- Command: arm920t mwh_phys addr halfword
 -- Command: arm920t mwb_phys addr byte
     Writes the specified WORD (32 bits), HALFWORD (16 bits), or BYTE (8-bit) pattern, at the specified physical address ADDR.

 -- Command: arm920t read_cache filename
     Dump the content of ICache and DCache to a file named filename.

 -- Command: arm920t read_mmu filename
     Dump the content of the ITLB and DTLB to a file named filename.

 -- Command: arm920t virt2phys VA
     Translate a virtual address VA to a physical address and display the result.

ARM926EJ-S specific commands
----------------------------

These commands are available to ARM926EJ-S based CPUs, which are implementations of the ARMv5TEJ architecture based on the ARM9EJ-S integer core. They are available in addition to the ARMv4/5, ARM7/ARM9, and ARM9TDMI commands.

 -- Command: arm926ejs cache_info
     Print information about the caches found.

 -- Command: arm926ejs cp15 opcode1 opcode2 CRn CRm regnum [value]
     Accesses cp15 register REGNUM using OPCODE1, OPCODE2, CRN, and CRM. If a VALUE is provided, that value is written to that register. Else that register is read and displayed.

 -- Command: arm926ejs mdw_phys addr [count]
 -- Command: arm926ejs mdh_phys addr [count]
 -- Command: arm926ejs mdb_phys addr [count]
     Display contents of physical address ADDR, as 32-bit words (mdw_phys), 16-bit halfwords (mdh_phys), or 8-bit bytes (mdb_phys). If COUNT is specified, displays that many units.

 -- Command: arm926ejs mww_phys addr word
 -- Command: arm926ejs mwh_phys addr halfword
 -- Command: arm926ejs mwb_phys addr byte
     Writes the specified WORD (32 bits), HALFWORD (16 bits), or BYTE (8-bit) pattern, at the specified physical address ADDR.

 -- Command: arm926ejs virt2phys VA
     Translate a virtual address VA to a physical address and display the result.

ARM966E specific commands
-------------------------

These commands are available to ARM966 based CPUs, which are implementations of the ARMv5TE architecture. They are available in addition to the ARMv4/5, ARM7/ARM9, and ARM9TDMI commands.

 -- Command: arm966e cp15 regnum [value]
     Display cp15 register REGNUM; else if a VALUE is provided, that value is written to that register.

XScale specific commands
------------------------

These commands are available to XScale based CPUs, which are implementations of the ARMv5TE architecture.

 -- Command: xscale analyze_trace
     Displays the contents of the trace buffer.

 -- Command: xscale cache_clean_address address
     Changes the address used when cleaning the data cache.

 -- Command: xscale cache_info
     Displays information about the CPU caches.

 -- Command: xscale cp15 regnum [value]
     Display cp15 register REGNUM; else if a VALUE is provided, that value is written to that register.

 -- Command: xscale debug_handler target address
     Changes the address used for the specified target's debug handler.

 -- Command: xscale dcache (enable|disable)
     Enables or disable the CPU's data cache.

 -- Command: xscale dump_trace filename
     Dumps the raw contents of the trace buffer to filename.

 -- Command: xscale icache (enable|disable)
     Enables or disable the CPU's instruction cache.

 -- Command: xscale mmu (enable|disable)
     Enables or disable the CPU's memory management unit.

 -- Command: xscale trace_buffer (enable|disable) [fill [n] | wrap]
     Enables or disables the trace buffer, and controls how it is emptied.

 -- Command: xscale trace_image filename [offset [type]]
     Opens a trace image from filename, optionally rebasing its segment addresses by OFFSET. The image TYPE may be one of bin (binary), ihex (Intel hex), elf (ELF file), s19 (Motorola s19), mem, or builder.

 -- Command: xscale vector_catch mask
     Provide a bitmask showing the vectors to catch.

ARMv6 Architecture
==================

ARM11 specific commands
-----------------------

 -- Command: arm11 mcr p1 p2 p3 p4 p5
     Read coprocessor register

 -- Command: arm11 memwrite burst [value]
     Displays the value of the memwrite burst-enable flag, which is enabled by default. If VALUE is defined, first assigns that.

 -- Command: arm11 memwrite error_fatal [value]
     Displays the value of the memwrite error_fatal flag, which is enabled by default. If VALUE is defined, first assigns that.

 -- Command: arm11 mrc p1 p2 p3 p4 p5 value
     Write coprocessor register

 -- Command: arm11 no_increment [value]
     Displays the value of the flag controlling whether some read or write operations increment the pointer (the default behavior) or not (acting like a FIFO). If VALUE is defined, first assigns that.

 -- Command: arm11 step_irq_enable [value]
     Displays the value of the flag controlling whether IRQs are enabled during single stepping; they is disabled by default. If VALUE is defined, first assigns that.

ARMv7 Architecture
==================

ARMv7 Debug Access Port (DAP) specific commands
-----------------------------------------------

These commands are specific to ARM architecture v7 Debug Access Port (DAP), included on cortex-m3 and cortex-a8 systems. They are available in addition to other core-specific commands that may be available.

 -- Command: dap info [num]
     Displays dap info for ap [num], default currently selected AP.

 -- Command: dap apsel [num]
     Select a different AP [num] (default 0).

 -- Command: dap apid [num]
     Displays id reg from AP [num], default currently selected AP.

 -- Command: dap baseaddr [num]
     Displays debug base address from AP [num], default currently selected AP.

 -- Command: dap memaccess [value]
     Displays the number of extra tck for mem-ap memory bus access [0-255]. If value is defined, first assigns that.

Cortex-M3 specific commands
---------------------------

 -- Command: cortex_m3 maskisr (on|off)
     Control masking (disabling) interrupts during target step/resume.

Target DCC Requests
===================

OpenOCD can handle certain target requests; currently debugmsgs target_request debugmsgs are only supported for arm7_9 and cortex_m3.

See libdcc in the contrib dir for more details. Linux-ARM kernels have a ``Kernel low-level debugging via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC, depends on CONFIG_DEBUG_LL) which uses this mechanism to deliver messages before a serial console can be activated.

 -- Command: target_request debugmsgs [enable|disable|charmsg]
     Displays current handling of target DCC message requests. These messages may be sent to the debugger while the target is running. The optional enable and charmsg parameters both enable the messages, while disable disables them. With charmsg the DCC words each contain one character, as used by Linux with CONFIG_DEBUG_ICEDCC; otherwise the libdcc format is used.

JTAG Commands
*************

Most general purpose JTAG commands have been presented earlier. (see JTAG Speed, Reset Configuration, and TAP Creation.) Lower level JTAG commands, as presented here, may be needed to work with targets which require special attention during operations such as reset or initialization.

To use these commands you will need to understand some of the basics of JTAG, including:

  * A JTAG scan chain consists of a sequence of individual TAP devices such as a CPUs.

  * Control operations involve moving each TAP through the same standard state machine (in parallel) using their shared TMS and clock signals.

  * Data transfer involves shifting data through the chain of instruction or data registers of each TAP, writing new register values while the reading previous ones.

  * Data register sizes are a function of the instruction active in a given TAP, while instruction register sizes are fixed for each TAP. All TAPs support a BYPASS instruction with a single bit data register.

  * The way OpenOCD differentiates between TAP devices is by shifting different instructions into (and out of) their instruction registers.

Low Level JTAG Commands
=======================

These commands are used by developers who need to access JTAG instruction or data registers, possibly controlling the order of TAP state transitions. If you're not debugging OpenOCD internals, or bringing up a new JTAG adapter or a new type of TAP device (like a CPU or JTAG router), you probably won't need to use these commands.

 -- Command: drscan tap [numbits value]+ [-endstate tap_state]
     Loads the data register of TAP with a series of bit fields that specify the entire register. Each field is NUMBITS bits long with a numeric VALUE (hexadecimal encouraged). The return value holds the original value of each of those fields.

     For example, a 38 bit number might be specified as one field of 32 bits then one of 6 bits. For portability, never pass fields which are more than 32 bits long.  Many OpenOCD implementations do not support 64-bit (or larger) integer values.

     All TAPs other than TAP must be in BYPASS mode. The single bit in their data registers does not matter.

     When TAP_STATE is specified, the JTAG state machine is left in that state. For example DRPAUSE might be specified, so that more instructions can be issued before re-entering the RUN/IDLE state. If the end state is not specified, the RUN/IDLE state is entered.

          OpenOCD does not record information about data register lengths, so it is important that you get the bit field lengths right. Remember that different JTAG instructions refer to different data registers, which may have different lengths. Moreover, those lengths may not be fixed; the SCAN_N instruction can change the length of the register accessed by the INTEST instruction (by connecting a different scan chain).

 -- Command: flush_count
     Returns the number of times the JTAG queue has been flushed. This may be used for performance tuning.

     For example, flushing a queue over USB involves a minimum latency, often several milliseconds, which does not change with the amount of data which is written. You may be able to identify performance problems by finding tasks which waste bandwidth by flushing small transfers too often, instead of batching them into larger operations.

 -- Command: endstate tap_state
     Flush any pending JTAG operations, and return with all TAPs in TAP_STATE. This state should be a stable state such as RESET, RUN/IDLE, DRPAUSE, or IRPAUSE.

 -- Command: irscan [tap instruction]+ [-endstate tap_state]
     For each TAP listed, loads the instruction register with its associated numeric INSTRUCTION. (The number of bits in that instruction may be displayed using the scan_chain command.) For other TAPs, a BYPASS instruction is loaded.

     When TAP_STATE is specified, the JTAG state machine is left in that state. For example IRPAUSE might be specified, so the data register can be loaded before re-entering the RUN/IDLE state. If the end state is not specified, the RUN/IDLE state is entered.

          OpenOCD currently supports only a single field for instruction register values, unlike data register values. For TAPs where the instruction register length is more than 32 bits, portable scripts currently must issue only BYPASS instructions.

 -- Command: jtag_reset trst srst
     Set values of reset signals. The TRST and SRST parameter values may be 0, indicating that reset is inactive (pulled or driven high), or 1, indicating it is active (pulled or driven low). The reset_config command should already have been used to configure how the board and JTAG adapter treat these two signals, and to say if either signal is even present. See Reset Configuration.

 -- Command: runtest NUM_CYCLES
     Move to the RUN/IDLE state, and execute at least NUM_CYCLES of the JTAG clock (TCK). Instructions often need some time to execute before they take effect.

 -- Command: scan_chain
     Displays the TAPs in the scan chain configuration, and their status. The set of TAPs listed by this command is fixed by exiting the OpenOCD configuration stage, but systems with a JTAG router can enable or disable TAPs dynamically. In addition to the enable/disable status, the contents of each TAP's instruction register can also change.

 -- Command: verify_ircapture (enable|disable)
     Verify values captured during IRCAPTURE and returned during IR scans.  Default is enabled, but this can be overridden by verify_jtag.

 -- Command: verify_jtag (enable|disable)
     Enables verification of DR and IR scans, to help detect programming errors.  For IR scans, verify_ircapture must also be enabled. Default is enabled.

TAP state names
===============

The TAP_STATE names used by OpenOCD in the drscan, endstate, and irscan commands are:

  * RESET

  * RUN/IDLE

  * DRSELECT

  * DRCAPTURE

  * DRSHIFT

  * DREXIT1

  * DRPAUSE

  * DREXIT2

  * DRUPDATE

  * IRSELECT

  * IRCAPTURE

  * IRSHIFT

  * IREXIT1

  * IRPAUSE

  * IREXIT2

  * IRUPDATE

Note that only six of those states are fully ``stable'' in the face of TMS fixed and a free-running JTAG clock; for all the others, the next TCK transition changes to a new state.

  * RESET is probably most useful with endstate, but entering it frequently has side effects. (This is the only stable state with TMS high.)

  * From DRSHIFT and IRSHIFT, clock transitions will produce side effects by changing register contents.  The values to be latched in upcoming DRUPDATE or IRUPDATE states may not be as expected.

  * RUN/IDLE, DRPAUSE, and IRPAUSE are reasonable choices after drscan or irscan commands, since they are free of side effects.

TFTP
****

If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can be used to access files on PCs (either the developer's PC or some other PC).

The way this works on the ZY1000 is to prefix a filename by "/tftp/ip/" and append the TFTP path on the TFTP server (tftpd). For example,

     load_image /tftp/10.0.0.96/c:\temp\abc.elf

will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as if the file was hosted on the embedded host.

In order to achieve decent performance, you must choose a TFTP server that supports a packet size bigger than the default packet size (512 bytes). There are numerous TFTP servers out there (free and commercial) and you will have to do a bit of googling to find something that fits your requirements.

Sample Scripts
**************

This page shows how to use the Target Library.

The configuration script can be divided into the following sections:

  * Daemon configuration

  * Interface

  * JTAG scan chain

  * Target configuration

  * Flash configuration

Detailed information about each section can be found at OpenOCD configuration.

AT91R40008 example
==================

To start OpenOCD with a target script for the AT91R40008 CPU and reset the CPU upon startup of the OpenOCD daemon.

     openocd -f interface/parport.cfg -f target/at91r40008.cfg \
             -c "init" -c "reset"

GDB and OpenOCD
***************

OpenOCD complies with the remote gdbserver protocol, and as such can be used to debug remote targets.

Connecting to GDB
=================

Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance GDB 6.3 has a known bug that produces bogus memory access errors, which has since been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb

OpenOCD can communicate with GDB in two ways:

 1. A socket (TCP/IP) connection is typically started as follows:

          target remote localhost:3333

     This would cause GDB to connect to the gdbserver on the local pc using port 3333.

 2. A pipe connection is typically started as follows:

          target remote | openocd --pipe

     This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout). Using this method has the advantage of GDB starting/stopping OpenOCD for the debug session.

To list the available OpenOCD commands type monitor help on the GDB command line.

OpenOCD supports the gdb qSupported packet, this enables information to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes packet size and the device's memory map.

Previous versions of OpenOCD required the following GDB options to increase the packet size and speed up GDB communication:

     set remote memory-write-packet-size 1024
     set remote memory-write-packet-size fixed
     set remote memory-read-packet-size 1024
     set remote memory-read-packet-size fixed

This is now handled in the qSupported PacketSize and should not be required.

Programming using GDB
=====================

By default the target memory map is sent to GDB. This can be disabled by the following OpenOCD configuration option:

     gdb_memory_map disable

For this to function correctly a valid flash configuration must also be set in OpenOCD. For faster performance you should also configure a valid working area.

Informing GDB of the memory map of the target will enable GDB to protect any flash areas of the target and use hardware breakpoints by default. This means that the OpenOCD option gdb_breakpoint_override is not required when using a memory map. See gdb_breakpoint_override.

To view the configured memory map in GDB, use the GDB command info mem All other unassigned addresses within GDB are treated as RAM.

GDB 6.8 and higher set any memory area not in the memory map as inaccessible. This can be changed to the old behaviour by using the following GDB command

     set mem inaccessible-by-default off

If gdb_flash_program enable is also used, GDB will be able to program any flash memory using the vFlash interface.

GDB will look at the target memory map when a load command is given, if any areas to be programmed lie within the target flash area the vFlash packets will be used.

If the target needs configuring before GDB programming, an event script can be executed:

     $_TARGETNAME configure -event EVENTNAME BODY

To verify any flash programming the GDB command compare-sections can be used.

Tcl Scripting API
*****************

API rules
=========

The commands are stateless. E.g. the telnet command line has a concept of currently active target, the Tcl API proc's take this sort of state information as an argument to each proc.

There are three main types of return values: single value, name value pair list and lists.

Name value pair. The proc 'foo' below returns a name/value pair list.

 >  set foo(me)  Duane
 >  set foo(you) Oyvind
 >  set foo(mouse) Micky
 >  set foo(duck) Donald

If one does this:

 >  set foo

The result is:

    me Duane you Oyvind mouse Micky duck Donald

Thus, to get the names of the associative array is easy:

     foreach  { name value }   [set foo]   {
                puts "Name: $name, Value: $value"
     }

Lists returned must be relatively small. Otherwise a range should be passed in to the proc in question.

Internal low-level Commands
===========================

By low-level, the intent is a human would not directly use these commands.

Low-level commands are (should be) prefixed with "ocd_", e.g. ocd_flash_banks is the low level API upon which flash banks is implemented.

  * ocd_mem2array <VARNAME> <WIDTH> <ADDR> <NELEMS>

     Read memory and return as a Tcl array for script processing

  * ocd_array2mem <VARNAME> <WIDTH> <ADDR> <NELEMS>

     Convert a Tcl array to memory locations and write the values

  * ocd_flash_banks <DRIVER> <BASE> <SIZE> <CHIP_WIDTH> <BUS_WIDTH> <TARGET> [driver options ...]

     Return information about the flash banks

OpenOCD commands can consist of two words, e.g. "flash banks". The startup.tcl "unknown" proc will translate this into a Tcl proc called "flash_banks".

OpenOCD specific Global Variables
=================================

HostOS
------

Real Tcl has ::tcl_platform(), and platform::identify, and many other variables. JimTCL, as implemented in OpenOCD creates $HostOS which holds one of the following values:

  * winxx    Built using Microsoft Visual Studio

  * linux    Linux is the underlying operating sytem

  * darwin   Darwin (mac-os) is the underlying operating sytem.

  * cygwin   Running under Cygwin

  * mingw32  Running under MingW32

  * other    Unknown, none of the above.

Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.

     We should add support for a variable like Tcl variable tcl_platform(platform), it should be called jim_platform (because it is jim, not real tcl).

Deprecated/Removed Commands
***************************

Certain OpenOCD commands have been deprecated or removed during the various revisions.

Upgrade your scripts as soon as possible. These descriptions for old commands may be removed a year after the command itself was removed. This means that in January 2010 this chapter may become much shorter.

  * arm7_9 fast_writes

     Use arm7_9 fast_memory_access instead. See arm7_9 fast_memory_access.

  * arm7_9 force_hw_bkpts

     Use gdb_breakpoint_override instead. Note that GDB will use hardware breakpoints for flash if the GDB memory map has been set up(default when flash is declared in target configuration). See gdb_breakpoint_override.

  * arm7_9 sw_bkpts

     On by default. See gdb_breakpoint_override.

  * daemon_startup

     this config option has been removed, simply adding init and reset halt to the end of your config script will give the same behaviour as using daemon_startup reset and target cortex_m3 little reset_halt 0.

  * dump_binary

     use dump_image command with same args. See dump_image.

  * flash erase

     use flash erase_sector command with same args. See flash erase_sector.

  * flash write

     use flash write_bank command with same args. See flash write_bank.

  * flash write_binary

     use flash write_bank command with same args. See flash write_bank.

  * flash auto_erase

     use flash write_image command passing erase as the first parameter. See flash write_image.

  * jtag_device

     use the jtag newtap command, converting from positional syntax to named prefixes, and naming the TAP. See jtag newtap. Note that if you try to use the old command, a message will tell you the right new command to use; and that the fourth parameter in the old syntax was never actually used.

          OLD: jtag_device 8 0x01 0xe3 0xfe
          NEW: jtag newtap CHIPNAME TAPNAME \
                     -irlen 8 -ircapture 0x01 -irmask 0xe3

  * jtag_speed value

     See JTAG Speed. Usually, a value of zero means maximum speed. The actual effect of this option depends on the JTAG interface used.

       - wiggler: maximum speed / NUMBER

       - ft2232: 6MHz / (NUMBER+1)

       - amt jtagaccel: 8 / 2**NUMBER

       - jlink: maximum speed in kHz (0-12000), 0 will use RTCK

       - rlink: 24MHz / NUMBER, but only for certain values of NUMBER

  * load_binary

     use load_image command with same args. See load_image.

  * run_and_halt_time

     This command has been removed for simpler reset behaviour, it can be simulated with the following commands:

          reset run
          sleep 100
          halt

  * target <TYPE> <ENDIAN> <JTAG-POSITION>

     use the create subcommand of target.

  * target_script <TARGET#> <EVENTNAME> <SCRIPTNAME>

     use <TARGET_NAME> configure -event <EVENTNAME> "script <SCRIPTNAME>"

  * working_area

     use the configure subcommand of target to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.

FAQ
***

 1. RTCK, also known as: Adaptive Clocking - What is it?

     In digital circuit design it is often refered to as ``clock synchronisation'' the JTAG interface uses one clock (TCK or TCLK) operating at some speed, your target is operating at another.  The two clocks are not synchronised, they are ``asynchronous''

     In order for the two to work together they must be synchronised. Otherwise the two systems will get out of sync with each other and nothing will work. There are 2 basic options:

      1. Use a special circuit.

      2. One clock must be some multiple slower than the other.

     Does this really matter? For some chips and some situations, this is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some Atmel SAM7 and SAM9 chips start operation from reset at 32kHz - program/enable the oscillators and eventually the main clock. It is in those critical times you must slow the JTAG clock to sometimes 1 to 4kHz.

     Imagine debugging a 500MHz ARM926 hand held battery powered device that ``deep sleeps'' at 32kHz between every keystroke. It can be painful.

     Solution #1 - A special circuit

     In order to make use of this, your JTAG dongle must support the RTCK feature. Not all dongles support this - keep reading!

     The RTCK signal often found in some ARM chips is used to help with this problem. ARM has a good description of the problem described at this link: http://www.arm.com/support/faqdev/4170.html [checked 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic work? / how does adaptive clocking work?''.

     The nice thing about adaptive clocking is that ``battery powered hand held device example'' - the adaptiveness works perfectly all the time. One can set a break point or halt the system in the deep power down code, slow step out until the system speeds up.

     Solution #2 - Always works - but may be slower

     Often this is a perfectly acceptable solution.

     In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of the target clock speed. But what that ``magic division'' is varies depending on the chips on your board. ARM rule of thumb Most ARM based systems require an 8:1 division. Xilinx rule of thumb is 1/12 the clock speed.

     Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.

     You can still debug the 'low power' situations - you just need to manually adjust the clock speed at every step. While painful and tedious, it is not always practical.

     It is however easy to ``code your way around it'' - i.e.: Cheat a little, have a special debug mode in your application that does a ``high power sleep''. If you are careful - 98% of your problems can be debugged this way.

     To set the JTAG frequency use the command:

                  # Example: 1.234MHz
                  jtag_khz 1234

 2. Win32 Pathnames Why don't backslashes work in Windows paths?

     OpenOCD uses Tcl and a backslash is an escape char. Use { and } around Windows filenames.

          > echo \a

          > echo {\a}
          \a
          > echo "\a"

          >

 3. Missing: cygwin1.dll OpenOCD complains about a missing cygwin1.dll.

     Make sure you have Cygwin installed, or at least a version of OpenOCD that claims to come with all the necessary DLLs. When using Cygwin, try launching OpenOCD from the Cygwin shell.

 4. Breakpoint Issue I'm trying to set a breakpoint using GDB (or a frontend like Insight or Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".

     GDB issues software breakpoints when a normal breakpoint is requested, or to implement source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T, software breakpoints consume one of the two available hardware breakpoints.

 5. LPC2000 Flash When erasing or writing LPC2000 on-chip flash, the operation fails at random.

     Make sure the core frequency specified in the flash lpc2000 line matches the clock at the time you're programming the flash. If you've specified the crystal's frequency, make sure the PLL is disabled. If you've specified the full core speed (e.g. 60MHz), make sure the PLL is enabled.

 6. Amontec Chameleon When debugging using an Amontec Chameleon in its JTAG Accelerator configuration, I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed out while waiting for end of scan, rtck was disabled".

     Make sure your PC's parallel port operates in EPP mode. You might have to try several settings in your PC BIOS (ECP, EPP, and different versions of those).

 7. Data Aborts When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse), I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory(): memory read caused data abort".

     The errors are non-fatal, and are the result of GDB trying to trace stack frames beyond the last valid frame. It might be possible to prevent this by setting up a proper "initial" stack frame, if you happen to know what exactly has to be done, feel free to add this here.

     Simple: In your startup code - push 8 registers of zeros onto the stack before calling main(). What GDB is doing is ``climbing'' the run time stack by reading various values on the stack using the standard call frame for the target. GDB keeps going - until one of 2 things happen #1 an invalid frame is found, or #2 some huge number of stackframes have been processed. By pushing zeros on the stack, GDB gracefully stops.

     Debugging Interrupt Service Routines - In your ISR before you call your C code, do the same - artifically push some zeros onto the stack, remember to pop them off when the ISR is done.

     Also note: If you have a multi-threaded operating system, they often do not in the intrest of saving memory waste these few bytes. Painful...

 8. JTAG Reset Config I get the following message in the OpenOCD console (or log file): "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".

     This warning doesn't indicate any serious problem, as long as you don't want to debug your core right out of reset. Your .cfg file specified jtag_reset trst_and_srst srst_pulls_trst to tell OpenOCD that either your board, your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals independently. With this setup, it's not possible to halt the core right out of reset, everything else should work fine.

 9. USB Power When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be unstable. When single-stepping over large blocks of code, GDB and OpenOCD quit with an error message. Is there a stability issue with OpenOCD?

     No, this is not a stability issue concerning OpenOCD. Most users have solved this issue by simply using a self-powered USB hub, which they connect their Amontec JTAGkey to. Apparently, some computers do not provide a USB power supply stable enough for the Amontec JTAGkey to be operated.

     Laptops running on battery have this problem too...

 10. USB Power When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned: 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232". What does that mean and what might be the reason for this?

     First of all, the reason might be the USB power supply. Try using a self-powered hub instead of a direct connection to your computer. Secondly, the error code 4 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB chip ran into some sort of error - this points us to a USB problem.

 11. GDB Disconnects When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054". What does that mean and what might be the reason for this?

     Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB) has closed the connection to OpenOCD. This might be a GDB issue.

 12. LPC2000 Flash In the configuration file in the section where flash device configurations are described, there is a parameter for specifying the clock frequency for LPC2000 internal flash devices (e.g.  flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum), which must be specified in kilohertz. However, I do have a quartz crystal of a frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).  Is it possible to specify real numbers for the clock frequency?

     No. The clock frequency specified here must be given as an integral number. However, this clock frequency is used by the In-Application-Programming (IAP) routines of the LPC2000 family only, which seems to be very tolerant concerning the given clock frequency, so a slight difference between the specified clock frequency and the actual clock frequency will not cause any trouble.

 13. Command Order Do I have to keep a specific order for the commands in the configuration file?

     Well, yes and no. Commands can be given in arbitrary order, yet the devices listed for the JTAG scan chain must be given in the right order (jtag newdevice), with the device closest to the TDO-Pin being listed first. In general, whenever objects of the same type exist which require an index number, then these objects must be given in the right order (jtag newtap, targets and flash banks - a target references a jtag newtap and a flash bank references a target).

     You can use the ``scan_chain'' command to verify and display the tap order.

     Also, some commands can't execute until after init has been processed.  Such commands include nand probe and everything else that needs to write to controller registers, perhaps for setting up DRAM and loading it with code.

 14. JTAG Tap Order JTAG tap order - command order

     Many newer devices have multiple JTAG taps. For example: ST Microsystems STM32 chips have two taps, a ``boundary scan tap'' and ``Cortex-M3'' tap.  Example: The STM32 reference manual, Document ID: RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is connected to the boundary scan tap, which then connects to the Cortex-M3 tap, which then connects to the TDO pin.

     Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then (2) The boundary scan tap. If your board includes an additional JTAG chip in the scan chain (for example a Xilinx CPLD or FPGA) you could place it before or after the STM32 chip in the chain. For example:

       * OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)

       * STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)

       * STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin

       * STM32 TDO Pin (output) -> Xilinx TDI Pin (input)

       * Xilinx TDO Pin -> OpenOCD TDO (input)

     The ``jtag device'' commands would thus be in the order shown below. Note:

       * jtag newtap Xilinx tap -irlen ...

       * jtag newtap stm32  cpu -irlen ...

       * jtag newtap stm32  bs  -irlen ...

       * # Create the debug target and say where it is

       * target create stm32.cpu -chain-position stm32.cpu ...

 15. SYSCOMP Sometimes my debugging session terminates with an error. When I look into the log file, I can see these error messages: Error: arm7_9_common.c:561 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP

     TODO.

Tcl Crash Course
****************

Not everyone knows Tcl - this is not intended to be a replacement for learning Tcl, the intent of this chapter is to give you some idea of how the Tcl scripts work.

This chapter is written with two audiences in mind. (1) OpenOCD users who need to understand a bit more of how JIM-Tcl works so they can do something useful, and (2) those that want to add a new command to OpenOCD.

Tcl Rule #1
===========

There is a famous joke, it goes like this:

 1. Rule #1: The wife is always correct

 2. Rule #2: If you think otherwise, See Rule #1

The Tcl equal is this:

 1. Rule #1: Everything is a string

 2. Rule #2: If you think otherwise, See Rule #1

As in the famous joke, the consequences of Rule #1 are profound. Once you understand Rule #1, you will understand Tcl.

Tcl Rule #1b
============

There is a second pair of rules.

 1. Rule #1: Control flow does not exist. Only commands

      For example: the classic FOR loop or IF statement is not a control flow item, they are commands, there is no such thing as control flow in Tcl.

 2. Rule #2: If you think otherwise, See Rule #1

      Actually what happens is this: There are commands that by convention, act like control flow key words in other languages. One of those commands is the word ``for'', another command is ``if''.

Per Rule #1 - All Results are strings
=====================================

Every Tcl command results in a string. The word ``result'' is used deliberatly. No result is just an empty string. Remember: Rule #1 - Everything is a string

Tcl Quoting Operators
=====================

In life of a Tcl script, there are two important periods of time, the difference is subtle.

 1. Parse Time

 2. Evaluation Time

The two key items here are how ``quoted things'' work in Tcl. Tcl has three primary quoting constructs, the [square-brackets] the {curly-braces} and ``double-quotes''

By now you should know $VARIABLES always start with a $DOLLAR sign. BTW: To set a variable, you actually use the command ``set'', as in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x = 1'' statement, but without the equal sign.

  * [square-brackets]

      [square-brackets] are command substitutions. It operates much like Unix Shell `back-ticks`. The result of a [square-bracket] operation is exactly 1 string. Remember Rule #1 - Everything is a string. These two statements are roughly identical:

              # bash example
              X=`date`
              echo "The Date is: $X"
              # Tcl example
              set X [date]
              puts "The Date is: $X"

  * ``double-quoted-things''

      ``double-quoted-things'' are just simply quoted text. $VARIABLES and [square-brackets] are expanded in place - the result however is exactly 1 string. Remember Rule #1 - Everything is a string

              set x "Dinner"
              puts "It is now \"[date]\", $x is in 1 hour"

  * {Curly-Braces}

     {Curly-Braces} are magic: $VARIABLES and [square-brackets] are parsed, but are NOT expanded or executed. {Curly-Braces} are like 'single-quote' operators in BASH shell scripts, with the added feature: {curly-braces} can be nested, single quotes can not.  {{{this is nested 3 times}}} NOTE: [date] is perhaps a bad example, as of 28/nov/2008, Jim/OpenOCD does not have a date command.

Consequences of Rule 1/2/3/4
============================

The consequences of Rule 1 are profound.

Tokenisation & Execution.
-------------------------

Of course, whitespace, blank lines and #comment lines are handled in the normal way.

As a script is parsed, each (multi) line in the script file is tokenised and according to the quoting rules. After tokenisation, that line is immedatly executed.

Multi line statements end with one or more ``still-open'' {curly-braces} which - eventually - closes a few lines later.

Command Execution
-----------------

Remember earlier: There are no ``control flow'' statements in Tcl. Instead there are COMMANDS that simply act like control flow operators.

Commands are executed like this:

 1. Parse the next line into (argc) and (argv[]).

 2. Look up (argv[0]) in a table and call its function.

 3. Repeat until End Of File.

It sort of works like this:

         for(;;){
             ReadAndParse( &argc, &argv );

             cmdPtr = LookupCommand( argv[0] );

             (*cmdPtr->Execute)( argc, argv );
         }

When the command ``proc'' is parsed (which creates a procedure function) it gets 3 parameters on the command line. 1 the name of the proc (function), 2 the list of parameters, and 3 the body of the function. Not the choice of words: LIST and BODY. The PROC command stores these items in a table somewhere so it can be found by ``LookupCommand()''

The FOR command
---------------

The most interesting command to look at is the FOR command.  In Tcl, the FOR command is normally implemented in C. Remember, FOR is a command just like any other command.

When the ascii text containing the FOR command is parsed, the parser produces 5 parameter strings, (If in doubt: Refer to Rule #1) they are:

 0. The ascii text 'for'

 1. The start text

 2. The test expression

 3. The next text

 4. The body text

Sort of reminds you of ``main( int argc, char **argv )'' does it not? Remember Rule #1 - Everything is a string. The key point is this: Often many of those parameters are in {curly-braces} - thus the variables inside are not expanded or replaced until later.

Remember that every Tcl command looks like the classic ``main( argc, argv )'' function in C. In JimTCL - they actually look like this:

     int
     MyCommand( Jim_Interp *interp,
                int *argc,
                Jim_Obj * const *argvs );

Real Tcl is nearly identical. Although the newer versions have introduced a byte-code parser and intepreter, but at the core, it still operates in the same basic way.

FOR command implementation
--------------------------

To understand Tcl it is perhaps most helpful to see the FOR command. Remember, it is a COMMAND not a control flow structure.

In Tcl there are two underlying C helper functions.

Remember Rule #1 - You are a string.

The first helper parses and executes commands found in an ascii string. Commands can be seperated by semicolons, or newlines. While parsing, variables are expanded via the quoting rules.

The second helper evaluates an ascii string as a numerical expression and returns a value.

Here is an example of how the FOR command could be implemented. The pseudo code below does not show error handling.

     void Execute_AsciiString( void *interp, const char *string );

     int Evaluate_AsciiExpression( void *interp, const char *string );

     int
     MyForCommand( void *interp,
                   int argc,
                   char **argv )
     {
        if( argc != 5 ){
            SetResult( interp, "WRONG number of parameters");
            return ERROR;
        }

        // argv[0] = the ascii string just like C

        // Execute the start statement.
        Execute_AsciiString( interp, argv[1] );

        // Top of loop test
        for(;;){
             i = Evaluate_AsciiExpression(interp, argv[2]);
             if( i == 0 )
                 break;

             // Execute the body
             Execute_AsciiString( interp, argv[3] );

             // Execute the LOOP  part
             Execute_AsciiString( interp, argv[4] );
         }

         // Return no error
         SetResult( interp, "" );
         return SUCCESS;
     }

Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works in the same basic way.

OpenOCD Tcl Usage
=================

source and find commands
------------------------

Where: In many configuration files

 Example:  source [find FILENAME]

Remember the parsing rules

 1. The FIND command is in square brackets.

      The FIND command is executed with the parameter FILENAME. It should find the full path to the named file. The RESULT is a string, which is substituted on the orginal command line.

 2. The command source is executed with the resulting filename.

      SOURCE reads a file and executes as a script.

format command
--------------

Where: Generally occurs in numerous places.

 Tcl has no command like printf(), instead it has format, which is really more like sprintf(). Example

         set x 6
         set y 7
         puts [format "The answer: %d" [expr $x * $y]]

 1. The SET command creates 2 variables, X and Y.

 2. The double [nested] EXPR command performs math

      The EXPR command produces numerical result as a string.

      Refer to Rule #1

 3. The format command is executed, producing a single string

      Refer to Rule #1.

 4. The PUTS command outputs the text.

Body or Inlined Text
--------------------

Where: Various TARGET scripts.

     #1 Good
        proc someproc {} {
            ... multiple lines of stuff ...
        }
        $_TARGETNAME configure -event FOO  someproc
     #2 Good - no variables
        $_TARGETNAME confgure -event foo "this ; that;"
     #3 Good Curly Braces
        $_TARGETNAME configure -event FOO {
             puts "Time: [date]"
        }
     #4 DANGER DANGER DANGER
        $_TARGETNAME configure -event foo "puts \"Time: [date]\""

 1. The $_TARGETNAME is an OpenOCD variable convention.

     $_TARGETNAME represents the last target created, the value changes each time a new target is created. Remember the parsing rules. When the ascii text is parsed, the $_TARGETNAME becomes a simple string, the name of the target which happens to be a TARGET (object) command.

 2. The 2nd parameter to the -event parameter is a TCBODY

     There are 4 examples:

      1. The TCLBODY is a simple string that happens to be a proc name

      2. The TCLBODY is several simple commands seperated by semicolons

      3. The TCLBODY is a multi-line {curly-brace} quoted string

      4. The TCLBODY is a string with variables that get expanded.

     In the end, when the target event FOO occurs the TCLBODY is evaluated. Method #1 and #2 are functionally identical.  For Method #3 and #4 it is more interesting. What is the TCLBODY?

     Remember the parsing rules. In case #3, {curly-braces} mean the $VARS and [square-brackets] are expanded later, when the EVENT occurs, and the text is evaluated. In case #4, they are replaced before the ``Target Object Command'' is executed. This occurs at the same time $_TARGETNAME is replaced. In case #4 the date will never change. {BTW: [date] is perhaps a bad example, as of 28/nov/2008, Jim/OpenOCD does not have a date command}

Global Variables
----------------

Where: You might discover this when writing your own procs
 In simple terms: Inside a PROC, if you need to access a global variable you must say so. See also ``upvar''. Example:

     proc myproc { } {
          set y 0  #Local variable Y
          global x #Global variable X
          puts [format "X=%d, Y=%d" $x $y]
     }

Other Tcl Hacks
===============

Dynamic variable creation

     # Dynamically create a bunch of variables.
     for { set x 0  } { $x < 32 } { set x [expr $x + 1]} {
         # Create var name
         set vn [format "BIT%d" $x]
         # Make it a global
         global $vn
         # Set it.
         set $vn   [expr (1 << $x)]
     }

Dynamic proc/command creation

     # One "X" function - 5 uart functions.
     foreach who {A B C D E}
        proc [format "show_uart%c" $who] { } "show_UARTx $who"
     }

Target Library
**************

OpenOCD comes with a target configuration script library. These scripts can be used as-is or serve as a starting point.

The target library is published together with the OpenOCD executable and the path to the target library is in the OpenOCD script search path. Similarly there are example scripts for configuring the JTAG interface.

The command line below uses the example parport configuration script that ship with OpenOCD, then configures the str710.cfg target and finally issues the init and reset commands. The communication speed is set to 10kHz for reset and 8MHz for post reset.

     openocd -f interface/parport.cfg -f target/str710.cfg \
             -c "init" -c "reset"

To list the target scripts available:

     $ ls  /usr/local/lib/openocd/target

     arm7_fast.cfg    lm3s6965.cfg  pxa255.cfg      stm32.cfg   xba_revA3.cfg
     at91eb40a.cfg    lpc2148.cfg   pxa255_sst.cfg  str710.cfg  zy1000.cfg
     at91r40008.cfg   lpc2294.cfg   sam7s256.cfg    str912.cfg
     at91sam9260.cfg  nslu2.cfg     sam7x256.cfg    wi-9c.cfg

     [file fdl.texi not included]