+# SRSR - SDRAM Setup?\r
+# P7_8(RD#), P7_7(WE1#), P7_6(WE0#), P7_5(RD/WR#), P7_4(CKE), P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#)\r
+mem set 0xfcfe341c 16 0xffff # PMC7\r
+mem set 0xfcfe3A1c 16 0x0000 # PFCAE7\r
+mem set 0xfcfe361c 16 0x0000 # PFCE7\r
+mem set 0xfcfe351c 16 0x0000 # PFC7\r
+mem set 0xfcfe721c 16 0xffff # PIPC7\r
+# P5_8(CS2#),\r
+mem set 0xfcfe3414 16 0x0100 # PMC5\r
+mem set 0xfcfe3A14 16 0x0100 # PFCAE5\r
+mem set 0xfcfe3614 16 0x0000 # PFCE5\r
+mem set 0xfcfe3514 16 0x0100 # PFC5\r
+mem set 0xfcfe7214 16 0x0100 # PIPC5\r
+\r
+# disable verify on SDRAM setup registers\r
+memory S:0x3fffc000 S:0x3fffffff nocache noverify\r
+\r
+######################################\r
+# CS2 SDRAM Setting ##\r
+######################################\r
+mem set 0x3fffc00c 32 0x00004C00 # CS2BCR - SDRAM\r
+mem set 0x3fffc030 32 0x00000080 # CS2WCR - SDRAM\r
+mem set 0x3fffd040 16 0x0000 # SDRAM_MODE_CS2\r
+\r
+######################################\r
+# CS3 SDRAM Setting ##\r
+######################################\r
+wait 0.5s\r
+mem set 0x3fffc010 32 0x00004C00 # CS3BCR - SDRAM\r
+mem set 0x3fffc034 32 0x00002492 # CS3WCR - SDRAM\r
+mem set 0x3fffc04c 32 0x00120812 # SDCR\r
+mem set 0x3fffc058 32 0xA55A0020 # RTCOR\r
+mem set 0x3fffc050 32 0xA55A0010 # RTCSR\r
+mem set 0x3fffe040 16 0x0000 # SDRAM_MODE_CS3\r
+# SRSR - SDRAM Setup?\r
+\r
+#SRSR - Not used - updated to include SDRAM setup\r
+# P7_6(WE0#), P7_8(RD#), P7_0(CS0#),\r
+#mem set 0xfcfe341c 16 0xff41 # PMC7\r
+#mem set 0xfcfe3A1c 16 0x0000 # PFCAE7\r
+#mem set 0xfcfe361c 16 0x0000 # PFCE7\r
+#mem set 0xfcfe351c 16 0x0000 # PFC7\r
+#mem set 0xfcfe721c 16 0xff41 # PIPC7\r
+#SRSR - Not used - updated to include SDRAM setup\r