Update library files used in STM32F7 demo to the latest version released by ST.

[freertos] / FreeRTOS / Demo / CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil / CMSIS / Include / core_cm3.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h
index d41ac3f0bee01c2a2c535dd80ff09e3d344ab31f..d324f9b78764036c28bb07ab66099c2802fa87c8 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h
+++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h
@@ -1,13 +1,13 @@
 /**************************************************************************//**\r
  * @file     core_cm3.h\r
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
 /**************************************************************************//**\r
  * @file     core_cm3.h\r
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r

- * @version  V4.00\r
- * @date     22. August 2014\r
+ * @version  V4.10\r
+ * @date     18. March 2015\r

  *\r
  * @note\r
  *\r
  ******************************************************************************/\r
  *\r
  * @note\r
  *\r
  ******************************************************************************/\r

-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r

 \r
    All rights reserved.\r
    Redistribution and use in source and binary forms, with or without\r
 \r
    All rights reserved.\r
    Redistribution and use in source and binary forms, with or without\r


@@ -232,13 +232,7 @@ typedef union
 {\r
   struct\r
   {\r
 {\r
   struct\r
   {\r

-#if (__CORTEX_M != 0x04)\r

     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */\r
     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */\r

-#else\r
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */\r
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */\r
-#endif\r

     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */\r
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */\r
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */\r
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */\r
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */\r
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */\r


@@ -248,6 +242,22 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } APSR_Type;\r
 \r
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } APSR_Type;\r
 \r

+/* APSR Register Definitions */\r
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */\r
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */\r
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */\r
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */\r
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */\r
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r
+\r

 \r
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
  */\r
 \r
 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).\r
  */\r


@@ -261,6 +271,10 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } IPSR_Type;\r
 \r
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } IPSR_Type;\r
 \r

+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r
+\r

 \r
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
  */\r
 \r
 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r
  */\r


@@ -269,13 +283,7 @@ typedef union
   struct\r
   {\r
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */\r
   struct\r
   {\r
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */\r

-#if (__CORTEX_M != 0x04)\r

     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */\r
     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */\r

-#else\r
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */\r
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */\r
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */\r
-#endif\r

     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */\r
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */\r
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */\r
     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */\r
     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */\r
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */\r


@@ -287,6 +295,31 @@ typedef union
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } xPSR_Type;\r
 \r
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } xPSR_Type;\r
 \r

+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */\r
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */\r
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */\r
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */\r
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r
+\r

 \r
 /** \brief  Union type to access the Control Registers (CONTROL).\r
  */\r
 \r
 /** \brief  Union type to access the Control Registers (CONTROL).\r
  */\r


@@ -296,12 +329,18 @@ typedef union
   {\r
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */\r
   {\r
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r
     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */\r

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */\r
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */\r
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */\r

   } b;                                   /*!< Structure used for bit  access                  */\r
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } CONTROL_Type;\r
 \r
   } b;                                   /*!< Structure used for bit  access                  */\r
   uint32_t w;                            /*!< Type      used for word access                  */\r
 } CONTROL_Type;\r
 \r

+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r
+\r

 /*@} end of group CMSIS_CORE */\r
 \r
 \r
 /*@} end of group CMSIS_CORE */\r
 \r
 \r


@@ -332,7 +371,7 @@ typedef struct
 \r
 /* Software Triggered Interrupt Register Definitions */\r
 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */\r
 \r
 /* Software Triggered Interrupt Register Definitions */\r
 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */\r

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r

 \r
 /*@} end of group CMSIS_NVIC */\r
 \r
 \r
 /*@} end of group CMSIS_NVIC */\r
 \r


@@ -384,7 +423,7 @@ typedef struct
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
 \r
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */\r
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
 \r
 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */\r

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r

 \r
 /* SCB Interrupt Control State Register Definitions */\r
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */\r
 \r
 /* SCB Interrupt Control State Register Definitions */\r
 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */\r


@@ -415,7 +454,7 @@ typedef struct
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
 \r
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */\r
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
 \r
 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */\r

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r

 \r
 /* SCB Vector Table Offset Register Definitions */\r
 #if (__CM3_REV < 0x0201)                   /* core r2p1 */\r
 \r
 /* SCB Vector Table Offset Register Definitions */\r
 #if (__CM3_REV < 0x0201)                   /* core r2p1 */\r


@@ -449,7 +488,7 @@ typedef struct
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
 \r
 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */\r
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
 \r
 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */\r

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r

 \r
 /* SCB System Control Register Definitions */\r
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */\r
 \r
 /* SCB System Control Register Definitions */\r
 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */\r


@@ -478,7 +517,7 @@ typedef struct
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
 \r
 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */\r
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
 \r
 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */\r

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r

 \r
 /* SCB System Handler Control and State Register Definitions */\r
 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */\r
 \r
 /* SCB System Handler Control and State Register Definitions */\r
 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */\r


@@ -521,7 +560,7 @@ typedef struct
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
 \r
 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */\r
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
 \r
 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */\r

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r

 \r
 /* SCB Configurable Fault Status Registers Definitions */\r
 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */\r
 \r
 /* SCB Configurable Fault Status Registers Definitions */\r
 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */\r


@@ -531,7 +570,7 @@ typedef struct
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
 \r
 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
 \r
 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r

 \r
 /* SCB Hard Fault Status Registers Definitions */\r
 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */\r
 \r
 /* SCB Hard Fault Status Registers Definitions */\r
 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */\r


@@ -557,7 +596,7 @@ typedef struct
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
 \r
 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */\r
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
 \r
 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */\r

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r

 \r
 /*@} end of group CMSIS_SCB */\r
 \r
 \r
 /*@} end of group CMSIS_SCB */\r
 \r


@@ -583,7 +622,7 @@ typedef struct
 \r
 /* Interrupt Controller Type Register Definitions */\r
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */\r
 \r
 /* Interrupt Controller Type Register Definitions */\r
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */\r

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r

 \r
 /* Auxiliary Control Register Definitions */\r
 \r
 \r
 /* Auxiliary Control Register Definitions */\r
 \r


@@ -594,7 +633,7 @@ typedef struct
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
 \r
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */\r
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r
 \r
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */\r

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r

 \r
 /*@} end of group CMSIS_SCnotSCB */\r
 \r
 \r
 /*@} end of group CMSIS_SCnotSCB */\r
 \r


@@ -626,15 +665,15 @@ typedef struct
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
 \r
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
 \r
 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r

 \r
 /* SysTick Reload Register Definitions */\r
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
 \r
 /* SysTick Reload Register Definitions */\r
 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r

 \r
 /* SysTick Current Register Definitions */\r
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
 \r
 /* SysTick Current Register Definitions */\r
 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r

 \r
 /* SysTick Calibration Register Definitions */\r
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
 \r
 /* SysTick Calibration Register Definitions */\r
 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r


@@ -644,7 +683,7 @@ typedef struct
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
 \r
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
 \r
 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r

 \r
 /*@} end of group CMSIS_SysTick */\r
 \r
 \r
 /*@} end of group CMSIS_SysTick */\r
 \r


@@ -695,7 +734,7 @@ typedef struct
 \r
 /* ITM Trace Privilege Register Definitions */\r
 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */\r
 \r
 /* ITM Trace Privilege Register Definitions */\r
 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */\r

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r

 \r
 /* ITM Trace Control Register Definitions */\r
 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */\r
 \r
 /* ITM Trace Control Register Definitions */\r
 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */\r


@@ -723,19 +762,19 @@ typedef struct
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
 \r
 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */\r
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
 \r
 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */\r

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r

 \r
 /* ITM Integration Write Register Definitions */\r
 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */\r
 \r
 /* ITM Integration Write Register Definitions */\r
 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */\r

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r

 \r
 /* ITM Integration Read Register Definitions */\r
 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */\r
 \r
 /* ITM Integration Read Register Definitions */\r
 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */\r

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r

 \r
 /* ITM Integration Mode Control Register Definitions */\r
 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */\r
 \r
 /* ITM Integration Mode Control Register Definitions */\r
 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */\r

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r

 \r
 /* ITM Lock Status Register Definitions */\r
 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */\r
 \r
 /* ITM Lock Status Register Definitions */\r
 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */\r


@@ -745,7 +784,7 @@ typedef struct
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
 \r
 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */\r
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
 \r
 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */\r

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r

 \r
 /*@}*/ /* end of group CMSIS_ITM */\r
 \r
 \r
 /*@}*/ /* end of group CMSIS_ITM */\r
 \r


@@ -838,31 +877,31 @@ typedef struct
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
 \r
 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */\r
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r
 \r
 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */\r

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r

 \r
 /* DWT CPI Count Register Definitions */\r
 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */\r
 \r
 /* DWT CPI Count Register Definitions */\r
 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */\r

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r

 \r
 /* DWT Exception Overhead Count Register Definitions */\r
 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */\r
 \r
 /* DWT Exception Overhead Count Register Definitions */\r
 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */\r

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r

 \r
 /* DWT Sleep Count Register Definitions */\r
 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
 \r
 /* DWT Sleep Count Register Definitions */\r
 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */\r

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r

 \r
 /* DWT LSU Count Register Definitions */\r
 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */\r
 \r
 /* DWT LSU Count Register Definitions */\r
 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */\r

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r

 \r
 /* DWT Folded-instruction Count Register Definitions */\r
 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */\r
 \r
 /* DWT Folded-instruction Count Register Definitions */\r
 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */\r

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r

 \r
 /* DWT Comparator Mask Register Definitions */\r
 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */\r
 \r
 /* DWT Comparator Mask Register Definitions */\r
 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */\r

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r

 \r
 /* DWT Comparator Function Register Definitions */\r
 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */\r
 \r
 /* DWT Comparator Function Register Definitions */\r
 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */\r


@@ -890,7 +929,7 @@ typedef struct
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
 \r
 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */\r
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r
 \r
 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */\r

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r

 \r
 /*@}*/ /* end of group CMSIS_DWT */\r
 \r
 \r
 /*@}*/ /* end of group CMSIS_DWT */\r
 \r


@@ -933,11 +972,11 @@ typedef struct
 \r
 /* TPI Asynchronous Clock Prescaler Register Definitions */\r
 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */\r
 \r
 /* TPI Asynchronous Clock Prescaler Register Definitions */\r
 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */\r

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r

 \r
 /* TPI Selected Pin Protocol Register Definitions */\r
 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */\r
 \r
 /* TPI Selected Pin Protocol Register Definitions */\r
 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */\r

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r

 \r
 /* TPI Formatter and Flush Status Register Definitions */\r
 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */\r
 \r
 /* TPI Formatter and Flush Status Register Definitions */\r
 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */\r


@@ -950,7 +989,7 @@ typedef struct
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
 \r
 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */\r
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r
 \r
 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */\r

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r

 \r
 /* TPI Formatter and Flush Control Register Definitions */\r
 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */\r
 \r
 /* TPI Formatter and Flush Control Register Definitions */\r
 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */\r


@@ -961,7 +1000,7 @@ typedef struct
 \r
 /* TPI TRIGGER Register Definitions */\r
 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */\r
 \r
 /* TPI TRIGGER Register Definitions */\r
 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */\r

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r

 \r
 /* TPI Integration ETM Data Register Definitions (FIFO0) */\r
 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */\r
 \r
 /* TPI Integration ETM Data Register Definitions (FIFO0) */\r
 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */\r


@@ -983,11 +1022,11 @@ typedef struct
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
 \r
 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */\r
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r
 \r
 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */\r

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r

 \r
 /* TPI ITATBCTR2 Register Definitions */\r
 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */\r
 \r
 /* TPI ITATBCTR2 Register Definitions */\r
 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */\r

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r

 \r
 /* TPI Integration ITM Data Register Definitions (FIFO1) */\r
 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */\r
 \r
 /* TPI Integration ITM Data Register Definitions (FIFO1) */\r
 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */\r


@@ -1009,15 +1048,15 @@ typedef struct
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
 \r
 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */\r
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r
 \r
 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */\r

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r

 \r
 /* TPI ITATBCTR0 Register Definitions */\r
 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */\r
 \r
 /* TPI ITATBCTR0 Register Definitions */\r
 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */\r

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r

 \r
 /* TPI Integration Mode Control Register Definitions */\r
 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */\r
 \r
 /* TPI Integration Mode Control Register Definitions */\r
 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */\r

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r

 \r
 /* TPI DEVID Register Definitions */\r
 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */\r
 \r
 /* TPI DEVID Register Definitions */\r
 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */\r


@@ -1036,15 +1075,15 @@ typedef struct
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
 \r
 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */\r
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r
 \r
 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */\r

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r

 \r
 /* TPI DEVTYPE Register Definitions */\r
 \r
 /* TPI DEVTYPE Register Definitions */\r

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */\r
-\r

 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */\r
 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
 \r
 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */\r
 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r
 \r

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r
+\r

 /*@}*/ /* end of group CMSIS_TPI */\r
 \r
 \r
 /*@}*/ /* end of group CMSIS_TPI */\r
 \r
 \r


@@ -1080,7 +1119,7 @@ typedef struct
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
 \r
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */\r
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
 \r
 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */\r

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r

 \r
 /* MPU Control Register */\r
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */\r
 \r
 /* MPU Control Register */\r
 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */\r


@@ -1090,11 +1129,11 @@ typedef struct
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
 \r
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */\r
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
 \r
 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */\r

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r

 \r
 /* MPU Region Number Register */\r
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */\r
 \r
 /* MPU Region Number Register */\r
 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */\r

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r

 \r
 /* MPU Region Base Address Register */\r
 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */\r
 \r
 /* MPU Region Base Address Register */\r
 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */\r


@@ -1104,7 +1143,7 @@ typedef struct
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
 \r
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */\r
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
 \r
 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */\r

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r

 \r
 /* MPU Region Attribute and Size Register */\r
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */\r
 \r
 /* MPU Region Attribute and Size Register */\r
 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */\r


@@ -1135,7 +1174,7 @@ typedef struct
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
 \r
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */\r
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
 \r
 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */\r

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r

 \r
 /*@} end of group CMSIS_MPU */\r
 #endif\r
 \r
 /*@} end of group CMSIS_MPU */\r
 #endif\r


@@ -1192,14 +1231,14 @@ typedef struct
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
 \r
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
 \r
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r

 \r
 /* Debug Core Register Selector Register */\r
 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */\r
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
 \r
 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */\r
 \r
 /* Debug Core Register Selector Register */\r
 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */\r
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
 \r
 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */\r

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r

 \r
 /* Debug Exception and Monitor Control Register */\r
 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */\r
 \r
 /* Debug Exception and Monitor Control Register */\r
 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */\r


@@ -1239,7 +1278,7 @@ typedef struct
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
 \r
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
 \r
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */\r

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r

 \r
 /*@} end of group CMSIS_CoreDebug */\r
 \r
 \r
 /*@} end of group CMSIS_CoreDebug */\r
 \r


@@ -1311,13 +1350,13 @@ typedef struct
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
 {\r
   uint32_t reg_value;\r
 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
 {\r
   uint32_t reg_value;\r

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r

 \r
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
 \r
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */\r
-  reg_value  =  (reg_value                                 |\r
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */\r
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\r
+  reg_value  =  (reg_value                                   |\r
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */\r

   SCB->AIRCR =  reg_value;\r
 }\r
 \r
   SCB->AIRCR =  reg_value;\r
 }\r
 \r


@@ -1330,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  */\r
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
 {\r

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */\r
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1342,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  */\r
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
 {\r

-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1354,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
 {\r

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1370,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
 {\r

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1382,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
 {\r

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1394,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
 {\r

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1409,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
 {\r

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1424,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
 {\r

-  if(IRQn < 0) {\r
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */\r
+  if((int32_t)IRQn < 0) {\r
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r

   else {\r
   else {\r

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */\r
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+  }\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1445,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
 {\r
 \r
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
 {\r
 \r

-  if(IRQn < 0) {\r
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */\r
+  if((int32_t)IRQn < 0) {\r
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));\r
+  }\r

   else {\r
   else {\r

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */\r
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));\r
+  }\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1466,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  */\r
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
 {\r

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r

   uint32_t PreemptPriorityBits;\r
   uint32_t SubPriorityBits;\r
 \r
   uint32_t PreemptPriorityBits;\r
   uint32_t SubPriorityBits;\r
 \r

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r

 \r
   return (\r
 \r
   return (\r

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))\r
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r

          );\r
 }\r
 \r
          );\r
 }\r
 \r


@@ -1494,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
  */\r
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
 {\r

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r

   uint32_t PreemptPriorityBits;\r
   uint32_t SubPriorityBits;\r
 \r
   uint32_t PreemptPriorityBits;\r
   uint32_t SubPriorityBits;\r
 \r

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r

 \r
 \r

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r

 }\r
 \r
 \r
 }\r
 \r
 \r


@@ -1512,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
  */\r
 __STATIC_INLINE void NVIC_SystemReset(void)\r
 {\r
  */\r
 __STATIC_INLINE void NVIC_SystemReset(void)\r
 {\r

-  __DSB();                                                     /* Ensure all outstanding memory accesses included\r
-                                                                  buffered write are completed before reset */\r
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |\r
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */\r
-  __DSB();                                                     /* Ensure completion of memory access */\r
-  while(1);                                                    /* wait until reset */\r
+  __DSB();                                                          /* Ensure all outstanding memory accesses included\r
+                                                                       buffered write are completed before reset */\r
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r
+  __DSB();                                                          /* Ensure completion of memory access */\r
+  while(1) { __NOP(); }                                             /* wait until reset */\r

 }\r
 \r
 /*@} end of CMSIS_Core_NVICFunctions */\r
 }\r
 \r
 /*@} end of CMSIS_Core_NVICFunctions */\r


@@ -1551,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
  */\r
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
 {\r

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */\r
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */\r

 \r
 \r

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */\r
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */\r
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */\r
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r

   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
                    SysTick_CTRL_TICKINT_Msk   |\r
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
                    SysTick_CTRL_TICKINT_Msk   |\r

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
-  return (0);                                                  /* Function successful */\r
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0UL);                                                     /* Function successful */\r

 }\r
 \r
 #endif\r
 }\r
 \r
 #endif\r


@@ -1591,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
  */\r
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
 {\r
  */\r
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
 {\r

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */\r
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */\r
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r

   {\r
   {\r

-    while (ITM->PORT[0].u32 == 0);\r
-    ITM->PORT[0].u8 = (uint8_t) ch;\r
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }\r
+    ITM->PORT[0].u8 = (uint8_t)ch;\r

   }\r
   return (ch);\r
 }\r
   }\r
   return (ch);\r
 }\r