-\r
-/*\r
- * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other\r
- * registers. r0 is clobbered.\r
- */\r
-#define portSET_INTERRUPT_MASK() \\r
- __asm volatile \\r
- ( \\r
- " mov r0, %0 \n" \\r
- " msr basepri, r0 \n" \\r
- ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \\r
- )\r
-\r
-/*\r
- * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see\r
- * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
- */\r
-#define portCLEAR_INTERRUPT_MASK() \\r
- __asm volatile \\r
- ( \\r
- " mov r0, #0 \n" \\r
- " msr basepri, r0 \n" \\r
- :::"r0" \\r
- )\r
-\r
-/* FAQ: Setting BASEPRI to 0 in portCLEAR_INTERRUPT_MASK_FROM_ISR() is not a\r
-bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before\r
-disagreeing. */\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x\r
-\r
-\r