+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif\r
+\r
+/* portNOP() is not required by this port. */\r
+#define portNOP()\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline))\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\r
+{\r
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;\r
+\r
+ __asm volatile\r
+ (\r
+ " mrs %0, basepri \n" \\r
+ " mov %1, %2 \n" \\r
+ " msr basepri, %1 \n" \\r
+ " isb \n" \\r
+ " dsb \n" \\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ );\r
+\r
+ /* This return will not be reached but is necessary to prevent compiler\r
+ warnings. */\r
+ return ulOriginalBASEPRI;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portFORCE_INLINE static void vPortYield( void )\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+ /* Barriers are normally not required but do ensure the code is completely\r
+ within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+}\r