+#define portCONTEXT_SIZE 160\r
+#define portEPC_STACK_LOCATION 152\r
+#define portSTATUS_STACK_LOCATION 156\r
+#define portFPCSR_STACK_LOCATION 0\r
+#define portTASK_HAS_FPU_STACK_LOCATION 0\r
+#define portFPU_CONTEXT_SIZE 264\r
+\r
+/******************************************************************/\r
+.macro portSAVE_FPU_REGS offset, base\r
+ /* Macro to assist with saving just the FPU registers to the\r
+ * specified address and base offset,\r
+ * offset is a constant, base is the base pointer register */\r
+\r
+ sdc1 $f31, \offset + 248(\base)\r
+ sdc1 $f30, \offset + 240(\base)\r
+ sdc1 $f29, \offset + 232(\base)\r
+ sdc1 $f28, \offset + 224(\base)\r
+ sdc1 $f27, \offset + 216(\base)\r
+ sdc1 $f26, \offset + 208(\base)\r
+ sdc1 $f25, \offset + 200(\base)\r
+ sdc1 $f24, \offset + 192(\base)\r
+ sdc1 $f23, \offset + 184(\base)\r
+ sdc1 $f22, \offset + 176(\base)\r
+ sdc1 $f21, \offset + 168(\base)\r
+ sdc1 $f20, \offset + 160(\base)\r
+ sdc1 $f19, \offset + 152(\base)\r
+ sdc1 $f18, \offset + 144(\base)\r
+ sdc1 $f17, \offset + 136(\base)\r
+ sdc1 $f16, \offset + 128(\base)\r
+ sdc1 $f15, \offset + 120(\base)\r
+ sdc1 $f14, \offset + 112(\base)\r
+ sdc1 $f13, \offset + 104(\base)\r
+ sdc1 $f12, \offset + 96(\base)\r
+ sdc1 $f11, \offset + 88(\base)\r
+ sdc1 $f10, \offset + 80(\base)\r
+ sdc1 $f9, \offset + 72(\base)\r
+ sdc1 $f8, \offset + 64(\base)\r
+ sdc1 $f7, \offset + 56(\base)\r
+ sdc1 $f6, \offset + 48(\base)\r
+ sdc1 $f5, \offset + 40(\base)\r
+ sdc1 $f4, \offset + 32(\base)\r
+ sdc1 $f3, \offset + 24(\base)\r
+ sdc1 $f2, \offset + 16(\base)\r
+ sdc1 $f1, \offset + 8(\base)\r
+ sdc1 $f0, \offset + 0(\base)\r
+\r
+ .endm\r
+\r
+/******************************************************************/\r
+.macro portLOAD_FPU_REGS offset, base\r
+ /* Macro to assist with loading just the FPU registers from the\r
+ * specified address and base offset, offset is a constant,\r
+ * base is the base pointer register */\r
+\r
+ ldc1 $f0, \offset + 0(\base)\r
+ ldc1 $f1, \offset + 8(\base)\r
+ ldc1 $f2, \offset + 16(\base)\r
+ ldc1 $f3, \offset + 24(\base)\r
+ ldc1 $f4, \offset + 32(\base)\r
+ ldc1 $f5, \offset + 40(\base)\r
+ ldc1 $f6, \offset + 48(\base)\r
+ ldc1 $f7, \offset + 56(\base)\r
+ ldc1 $f8, \offset + 64(\base)\r
+ ldc1 $f9, \offset + 72(\base)\r
+ ldc1 $f10, \offset + 80(\base)\r
+ ldc1 $f11, \offset + 88(\base)\r
+ ldc1 $f12, \offset + 96(\base)\r
+ ldc1 $f13, \offset + 104(\base)\r
+ ldc1 $f14, \offset + 112(\base)\r
+ ldc1 $f15, \offset + 120(\base)\r
+ ldc1 $f16, \offset + 128(\base)\r
+ ldc1 $f17, \offset + 136(\base)\r
+ ldc1 $f18, \offset + 144(\base)\r
+ ldc1 $f19, \offset + 152(\base)\r
+ ldc1 $f20, \offset + 160(\base)\r
+ ldc1 $f21, \offset + 168(\base)\r
+ ldc1 $f22, \offset + 176(\base)\r
+ ldc1 $f23, \offset + 184(\base)\r
+ ldc1 $f24, \offset + 192(\base)\r
+ ldc1 $f25, \offset + 200(\base)\r
+ ldc1 $f26, \offset + 208(\base)\r
+ ldc1 $f27, \offset + 216(\base)\r
+ ldc1 $f28, \offset + 224(\base)\r
+ ldc1 $f29, \offset + 232(\base)\r
+ ldc1 $f30, \offset + 240(\base)\r
+ ldc1 $f31, \offset + 248(\base)\r
+\r
+ .endm\r