+#if (SELECTED_PORT == PORT_ARM_CortexM)\r
+/******************************************************************************\r
+ * (Advanced...)\r
+ *\r
+ * ISR_TAILCHAINING_THRESHOLD (For Cortex-M devices only)\r
+ *\r
+ * ARM Cortex-M devices may execute ISRs back-to-back (tail-chained) without \r
+ * resuming the previous context in between. Since this is decided in \r
+ * hardware, we can only detect this indirectly, in the following manner:\r
+ *\r
+ * When entering vTraceStoreISRBegin, we check the number of CPU cycles since \r
+ * the last return of vTraceStoreISREnd. If less or equal to the constant\r
+ * ISR_TAILCHAINING_THRESHOLD it is assumed that the ISRs executed back-to-back\r
+ * (tail-chained). In that case, the previously stored RESUME event \r
+ * (pointed to by ptrLastISRExitEvent) is then deleted to avoid showing a \r
+ * fragment of the previous context in between the ISR events. The delete is\r
+ * made by replacing the event code with a XTS16L event, that serves to keep\r
+ * the differential timestamp from the earlier event.\r
+ *\r
+ * The value of ISR_TAILCHAINING_THRESHOLD depends on the interrupt latency of \r
+ * the processor, on the compiler and on the compiler settings, but should be \r
+ * around 70 cycles. The default value is 66 cycles, which should be correct when \r
+ * using GCC with optimizations disabled (-O0) and Cortex-M3/M4.\r
+ *\r
+ * To measure this value, see MEASURE_ISR_TAILCHAINING_THRESHOLD below.\r
+ *\r
+ * If this value set too low, tail-chained ISRs will incorrectly be shown \r
+ * separated, with a short fragment of the previous task or ISR in between.\r
+ * If this value is set too high, you get the opposite effect - separate ISRs \r
+ * will appear to execute tail-chained and will appear to have higher execution \r
+ * time and response time (maximum ISR_TAILCHAINING_THRESHOLD cycles more).\r
+ *****************************************************************************/\r
+#define ISR_TAILCHAINING_THRESHOLD 66\r
+\r
+uint8_t* ptrLastISRExitEvent = NULL;\r
+uint32_t DWTCycleCountAtLastISRExit = 0;\r
+\r
+/******************************************************************************\r
+ * (Advanced...)\r
+ *\r
+ * MEASURE_ISR_TAILCHAINING_THRESHOLD (For Cortex-M devices only)\r
+ *\r
+ * Allows for measuring the value of ISR_TAILCHAINING_THRESHOLD (see above).\r
+ *\r
+ * This is intended to measure the minimum number of clock cycles from the end\r
+ * of vTraceStoreISREnd to the beginning of the following vTraceStoreISRBegin.\r
+ * For this purpose, we assume a test setup using the SysTick interrupt, which \r
+ * is available on most Cortex-M devices and typically used by the RTOS kernel. \r
+ * To do the measurement, follow these steps:\r
+ * \r
+ * 1. Make sure MEASURE_ISR_TAILCHAINING_THRESHOLD is enabled (defined as 1)\r
+ *\r
+ * 2. Temporarily replace your SysTick handler with the following:\r
+ * \r
+ * void xPortSysTickHandler( void )\r
+ * {\r
+ * vTraceStoreISRBegin(1); \r
+ * vTraceStoreISREnd();\r
+ * }\r
+ *\r
+ * 3. To make sure that the ISRs execute back-to-back, increase the OS tick \r
+ * frequency to a very high level so that the OS tick interrupt execute \r
+ * continuously with no application tasks in between. A tick frequency of \r
+ * 1 MHz (1.000.000) should be sufficient.\r
+ *\r
+ * 4. Put a breakpoint in the highest priority task and make sure it is not \r
+ * reached. This means that the SysTick handler is executing at maximum rate\r
+ * and thereby tail-chained, where the interrupt latency is 6 cycles.\r
+ *\r
+ * 5. Let the system run without breakpoints and inspect the value of \r
+ * threshold_low_watermark. This is the minimum total latency observed. \r
+ * The hardware latency is 6 clock cycles due to the tail-chaining, so the \r
+ * software latency (SL) is then SL = threshold_low_watermark - 6.\r
+ * \r
+ * The threshold value ISR_TAILCHAINING_THRESHOLD should be SL + 2 * HL, where \r
+ * HL is the normal hardware interrupt latency, i.e., the number of CPU \r
+ * cycles to enter or exit the exception handler for an exception in task \r
+ * context. The HL value is 12-16 depending on core, as shown below.\r
+ * \r
+ * Values for ISR_TAILCHAINING_THRESHOLD, assuming SL = 42\r
+ * Cortex-M3 and M4 (HL = 12): 66 cycles\r
+ * Cortex-M0 (HL = 16): 74 cycles\r
+ * Cortex-M0+ (HL = 15): 72 cycles\r
+ *\r
+ * If the ISR_TAILCHAINING_THRESHOLD value is set too low, some tail-chained\r
+ * ISRs be shown separated, with a short fragment of the previous actor. If \r
+ * the value is set too high, separate ISRs will appear to execute tail-chained\r
+ * and for too long time.\r
+ *****************************************************************************/\r
+#define MEASURE_ISR_TAILCHAINING_THRESHOLD 1\r
+\r
+#if (MEASURE_ISR_TAILCHAINING_THRESHOLD == 1)\r
+volatile uint32_t threshold_low_watermark = 2000000000;\r
+#endif\r
+\r
+#endif\r
+\r