Comment the new MicroBlaze port layer files.

[freertos] / Demo / ARM7_STR75x_IAR / 75x_init.s

diff --git a/Demo/ARM7_STR75x_IAR/75x_init.s b/Demo/ARM7_STR75x_IAR/75x_init.s
index a4b018b670d48fa168d471feff456995e45f6dba..850cf11a6164cfe4de04417a035421e34a70efa9 100644 (file)
--- a/Demo/ARM7_STR75x_IAR/75x_init.s
+++ b/Demo/ARM7_STR75x_IAR/75x_init.s
@@ -88,19 +88,19 @@ SIR0_off_addr    EQU    0x60        ; Source Interrupt Register 0
 ; ?program_start\r
 ;---------------------------------------------------------------\r
                MODULE  ?program_start\r
-               RSEG    IRQ_STACK:DATA(2)\r
-               RSEG    FIQ_STACK:DATA(2)\r
-               RSEG    UND_STACK:DATA(2)\r
-               RSEG    ABT_STACK:DATA(2)               \r
-               RSEG    SVC_STACK:DATA(2)\r
-               RSEG    CSTACK:DATA(2)\r
-               RSEG    ICODE:CODE(2)\r
-               PUBLIC  __program_start\r
+               SECTION IRQ_STACK:DATA:NOROOT(3)\r
+               SECTION FIQ_STACK:DATA:NOROOT(3)\r
+               SECTION UND_STACK:DATA:NOROOT(3)\r
+               SECTION ABT_STACK:DATA:NOROOT(3)        \r
+               SECTION SVC_STACK:DATA:NOROOT(3)\r
+               SECTION CSTACK:DATA:NOROOT(3)\r
+               SECTION .text:CODE(2)\r
+               PUBLIC  __iar_program_start\r
                EXTERN  ?main\r
                 CODE32\r
 \r
 \r
-__program_start:\r
+__iar_program_start:\r
         LDR     pc, =NextInst\r
 \r
 NextInst\r
@@ -134,19 +134,19 @@ NextInst
 \r
 \r
         MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit    ; No interrupts\r
-        ldr      sp,=SFE(FIQ_STACK) & 0xFFFFFFF8  ; End of FIQ_STACK\r
+        ldr      sp,=SFE(FIQ_STACK)              ; End of FIQ_STACK\r
 \r
         MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit    ; No interrupts\r
-        ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8  ; End of IRQ_STACK\r
+        ldr     sp,=SFE(IRQ_STACK)               ; End of IRQ_STACK\r
 \r
         MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit    ; No interrupts\r
-        ldr     sp,=SFE(ABT_STACK) & 0xFFFFFFF8   ; End of ABT_STACK\r
+        ldr     sp,=SFE(ABT_STACK)               ; End of ABT_STACK\r
 \r
         MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit    ; No interrupts\r
-        ldr     sp,=SFE(UND_STACK) & 0xFFFFFFF8  ; End of UND_STACK\r
+        ldr     sp,=SFE(UND_STACK)               ; End of UND_STACK\r
 \r
         MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit    ; No interrupts\r
-        ldr     sp,=SFE(SVC_STACK) & 0xFFFFFFF8  ; End of SVC_STACK\r
+        ldr     sp,=SFE(SVC_STACK)               ; End of SVC_STACK\r
 \r
 ; ------------------------------------------------------------------------------\r
 ; Description  :  Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register,\r