Remove ACE files that are not necessary for the SmartFusion demo.

[freertos] / Demo / CORTEX_A2F200_IAR_and_Keil / MicroSemi_Code / drivers / mss_ace / mss_ace.c

diff --git a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.c b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.c
index cd717f036df7664df6f2d9636a2574ad6687d245..ebd1e8dde12cf8996f83323f65d17fae248a4180 100644 (file)
--- a/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.c
+++ b/Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/mss_ace.c
@@ -1,6 +1,6 @@
 /*******************************************************************************\r
  * (c) Copyright 2009 Actel Corporation.  All rights reserved.\r
- * \r
+ *\r
  * SVN $Revision: 2905 $\r
  * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
  */\r
@@ -16,7 +16,7 @@
 \r
 #ifdef __cplusplus\r
 extern "C" {\r
-#endif \r
+#endif\r
 \r
 #define START_ADC_CONVERSION    0x80uL\r
 \r
@@ -31,8 +31,10 @@ void ace_init_convert(void);
 void ACE_init( void )\r
 {\r
     /* Initialize driver's internal data. */\r
-    ace_init_flags();\r
-    \r
+       #if (ACE_NB_OF_PPE_FLAGS > 0)\r
+           ace_init_flags();\r
+       #endif\r
+\r
     /* Initialize the data structures used by conversion functions. */\r
     ace_init_convert();\r
 }\r
@@ -70,13 +72,13 @@ uint16_t ACE_get_adc_result
     uint32_t data_valid;\r
 \r
     ASSERT( adc_id < NB_OF_ANALOG_MODULES );\r
-    \r
+\r
     if ( adc_id < (uint8_t)NB_OF_ANALOG_MODULES )\r
     {\r
         do {\r
             data_valid = *adc_status_reg_lut[adc_id] & ADC_DATAVALID_MASK;\r
         } while ( !data_valid );\r
-        \r
+\r
         result = (uint16_t)(*adc_status_reg_lut[adc_id] & ADC_RESULT_MASK);\r
     }\r
     return result;\r
@@ -88,7 +90,7 @@ uint16_t ACE_get_adc_result
 \r
 #define SDD_ENABLE_MASK     0x20uL\r
 #define SDD_REG_SEL_MASK    0x40uL\r
- \r
+\r
 #define DAC0_SYNC_EN_MASK   0x10uL\r
 #define DAC1_SYNC_EN_MASK   0x20uL\r
 #define DAC2_SYNC_EN_MASK   0x40uL\r
@@ -149,7 +151,7 @@ void ACE_configure_sdd
 )\r
 {\r
     ASSERT( sdd_id < NB_OF_SDD );\r
-    \r
+\r
     if ( sdd_id < NB_OF_SDD )\r
     {\r
         const uint8_t sdd_2_quad_lut[NB_OF_SDD] = {0u, 2u, 4u};\r
@@ -157,16 +159,16 @@ void ACE_configure_sdd
         uint8_t obd_mode_idx = 1u;\r
         uint8_t chopping_mode_idx = 0u;\r
         uint32_t saved_pc2_ctrl;\r
-        \r
+\r
         quad_id = sdd_2_quad_lut[sdd_id];\r
-        \r
+\r
         /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
         saved_pc2_ctrl = ACE->PC2_CTRL;\r
         ACE->PC2_CTRL = 0u;\r
-        \r
+\r
         /* Select between voltage/current and RTZ modes.*/\r
         ACE->ACB_DATA[quad_id].b6 = mode;\r
-        \r
+\r
         /* Load manufacturing generated trim value. */\r
         if ( (mode & OBD_MODE_MASK) > 0u )\r
         {\r
@@ -178,17 +180,17 @@ void ACE_configure_sdd
         }\r
         ACE->ACB_DATA[quad_id].b4\r
             = p_mtd_data->odb_trimming[sdd_id][obd_mode_idx][chopping_mode_idx];\r
-        \r
+\r
         /* Restore SSE PC2 operations since no ACB accesses should take place\r
          * beyond this point. */\r
         ACE->PC2_CTRL = saved_pc2_ctrl;\r
-    \r
+\r
         /* Set SDD resolution. */\r
         *dac_ctrl_reg_lut[sdd_id] = (uint32_t)resolution;\r
-        \r
+\r
         /* Update SDD value through SSE_DACn_BYTES01. */\r
         *dac_ctrl_reg_lut[sdd_id] |= SDD_REG_SEL_MASK;\r
-        \r
+\r
         /* Synchronous or individual SDD update. */\r
         if ( INDIVIDUAL_UPDATE == sync_update )\r
         {\r
@@ -210,7 +212,7 @@ void ACE_enable_sdd
 )\r
 {\r
     ASSERT( sdd_id < NB_OF_SDD );\r
-    \r
+\r
     if ( sdd_id < NB_OF_SDD )\r
     {\r
         *dac_ctrl_reg_lut[sdd_id] |= SDD_ENABLE_MASK;\r
@@ -226,7 +228,7 @@ void ACE_disable_sdd
 )\r
 {\r
     ASSERT( sdd_id < NB_OF_SDD );\r
-    \r
+\r
     if ( sdd_id < NB_OF_SDD )\r
     {\r
         *dac_ctrl_reg_lut[sdd_id] &= ~SDD_ENABLE_MASK;\r
@@ -243,7 +245,7 @@ void ACE_set_sdd_value
 )\r
 {\r
     ASSERT( sdd_id < NB_OF_SDD );\r
-    \r
+\r
     if ( sdd_id < NB_OF_SDD )\r
     {\r
         *dac_byte2_reg_lut[sdd_id] = sdd_value >> 16;\r
@@ -262,9 +264,9 @@ void ACE_set_sdd_value_sync
 )\r
 {\r
     uint32_t dac_sync_ctrl;\r
-    \r
+\r
     dac_sync_ctrl = ACE->DAC_SYNC_CTRL;\r
-    \r
+\r
     if ( SDD_NO_UPDATE != sdd0_value )\r
     {\r
         ACE->DAC0_BYTE2 = sdd0_value >> 16;\r
@@ -286,7 +288,7 @@ void ACE_set_sdd_value_sync
         ACE->SSE_DAC2_BYTES01 = sdd2_value;\r
         dac_sync_ctrl |= DAC2_SYNC_UPDATE;\r
     }\r
-    \r
+\r
     ACE->DAC_SYNC_CTRL = dac_sync_ctrl;\r
 }\r
 \r
@@ -357,23 +359,23 @@ void ACE_set_comp_reference
 {\r
     uint8_t scb_id;\r
     uint32_t odd;\r
-    \r
+\r
     odd = (uint32_t)comp_id & 0x01uL;\r
-    \r
+\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
     ASSERT( reference < NB_OF_COMP_REF );\r
     ASSERT( odd );    /* Only Temperature block comparators have configurable reference input. */\r
-    \r
+\r
     if ( (comp_id < NB_OF_COMPARATORS) && (reference < NB_OF_COMP_REF) && (odd) )\r
     {\r
         uint32_t saved_pc2_ctrl;\r
-        \r
+\r
         scb_id = comp_id_2_scb_lut[comp_id];\r
-        \r
+\r
         /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
         saved_pc2_ctrl = ACE->PC2_CTRL;\r
         ACE->PC2_CTRL = 0u;\r
-    \r
+\r
         if ( ADC_IN_COMP_REF == reference )\r
         {\r
             ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
@@ -384,7 +386,7 @@ void ACE_set_comp_reference
             ACE->ACB_DATA[scb_id].b10 &= (uint8_t)~B10_COMP_VREF_SW_MASK;\r
             ACE->ACB_DATA[scb_id].b11 = (ACE->ACB_DATA[scb_id].b11 & (uint8_t)~B11_DAC_MUXSEL_MASK) + (uint8_t)reference;\r
         }\r
-    \r
+\r
         /* Restore SSE PC2 operations since no ACB accesses should take place\r
          * beyond this point. */\r
         ACE->PC2_CTRL = saved_pc2_ctrl;\r
@@ -401,22 +403,22 @@ void ACE_set_comp_hysteresis
 )\r
 {\r
     uint8_t scb_id;\r
-    \r
+\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
     ASSERT( hysteresis < NB_OF_HYSTERESIS );\r
-    \r
+\r
     if ( (comp_id < NB_OF_COMPARATORS) && (hysteresis < NB_OF_HYSTERESIS) )\r
     {\r
         uint32_t odd;\r
         uint32_t saved_pc2_ctrl;\r
-        \r
+\r
         scb_id = comp_id_2_scb_lut[comp_id];\r
         odd = (uint32_t)comp_id & 0x01uL;\r
-        \r
+\r
         /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
         saved_pc2_ctrl = ACE->PC2_CTRL;\r
         ACE->PC2_CTRL = 0u;\r
-    \r
+\r
         if ( odd )\r
         {\r
             /* Temperature monitor block comparator. */\r
@@ -427,7 +429,7 @@ void ACE_set_comp_hysteresis
             /* Current monitor block comparator. */\r
             ACE->ACB_DATA[scb_id].b9 = (ACE->ACB_DATA[scb_id].b9 & HYSTERESIS_MASK) | (uint8_t)((uint8_t)hysteresis << HYSTERESIS_SHIFT);\r
         }\r
-        \r
+\r
         /* Restore SSE PC2 operations since no ACB accesses should take place\r
          * beyond this point. */\r
         ACE->PC2_CTRL = saved_pc2_ctrl;\r
@@ -435,7 +437,7 @@ void ACE_set_comp_hysteresis
 }\r
 \r
 /*-------------------------------------------------------------------------*//**\r
-  \r
+\r
  */\r
 void ACE_enable_comp\r
 (\r
@@ -443,21 +445,21 @@ void ACE_enable_comp
 )\r
 {\r
     uint8_t scb_id;\r
-    \r
+\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     if ( comp_id < NB_OF_COMPARATORS )\r
     {\r
         uint32_t odd;\r
         uint32_t saved_pc2_ctrl;\r
-        \r
+\r
         scb_id = comp_id_2_scb_lut[comp_id];\r
         odd = (uint32_t)comp_id & 0x01uL;\r
-        \r
+\r
         /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
         saved_pc2_ctrl = ACE->PC2_CTRL;\r
         ACE->PC2_CTRL = 0u;\r
-        \r
+\r
         if ( odd )\r
         {\r
             /* Temperature monitor block comparator. */\r
@@ -468,7 +470,7 @@ void ACE_enable_comp
             /* Current monitor block comparator. */\r
             ACE->ACB_DATA[scb_id].b9 |= COMPARATOR_ENABLE_MASK;\r
         }\r
-        \r
+\r
         /* Restore SSE PC2 operations since no ACB accesses should take place\r
          * beyond this point. */\r
         ACE->PC2_CTRL = saved_pc2_ctrl;\r
@@ -484,21 +486,21 @@ void ACE_disable_comp
 )\r
 {\r
     uint8_t scb_id;\r
-    \r
+\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     if ( comp_id < NB_OF_COMPARATORS )\r
     {\r
         uint32_t odd;\r
         uint32_t saved_pc2_ctrl;\r
-        \r
+\r
         scb_id = comp_id_2_scb_lut[comp_id];\r
         odd = (uint32_t)comp_id & 0x01uL;\r
-        \r
+\r
         /* Pause the SSE PC2 while accesses to ACB from APB3 are taking place. */\r
         saved_pc2_ctrl = ACE->PC2_CTRL;\r
         ACE->PC2_CTRL = 0u;\r
-        \r
+\r
         if ( odd )\r
         {\r
             /* Temperature monitor block comparator. */\r
@@ -509,7 +511,7 @@ void ACE_disable_comp
             /* Current monitor block comparator. */\r
             ACE->ACB_DATA[scb_id].b9 &= (uint8_t)~COMPARATOR_ENABLE_MASK;\r
         }\r
-        \r
+\r
         /* Restore SSE PC2 operations since no ACB accesses should take place\r
          * beyond this point. */\r
         ACE->PC2_CTRL = saved_pc2_ctrl;\r
@@ -539,7 +541,7 @@ void ACE_enable_comp_rise_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_EN |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -552,7 +554,7 @@ void ACE_disable_comp_rise_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_EN &= ~(FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -565,7 +567,7 @@ void ACE_clear_comp_rise_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_CLR |= (FIRST_RISE_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -578,7 +580,7 @@ void ACE_enable_comp_fall_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_EN |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -591,7 +593,7 @@ void ACE_disable_comp_fall_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_EN &= ~(FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -604,7 +606,7 @@ void ACE_clear_comp_fall_irq
 )\r
 {\r
     ASSERT( comp_id < NB_OF_COMPARATORS );\r
-    \r
+\r
     ACE->COMP_IRQ_CLR |= (FIRST_FALL_IRQ_MASK << (uint32_t)comp_id);\r
 }\r
 \r
@@ -643,9 +645,9 @@ ACE_get_first_channel
 )\r
 {\r
     ace_channel_handle_t channel_handle;\r
-    \r
+\r
     channel_handle = (ace_channel_handle_t)0;\r
-    \r
+\r
     return channel_handle;\r
 }\r
 \r
@@ -659,12 +661,12 @@ ACE_get_next_channel
 )\r
 {\r
     ++channel_handle;\r
-    \r
+\r
     if ( channel_handle >= NB_OF_ACE_CHANNEL_HANDLES )\r
     {\r
          channel_handle = (ace_channel_handle_t)0;\r
     }\r
-    \r
+\r
     return channel_handle;\r
 }\r
 \r
@@ -679,7 +681,7 @@ ACE_get_channel_handle
 {\r
     uint16_t channel_idx;\r
     ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
-    \r
+\r
     for ( channel_idx = 0u;  channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
     {\r
         if ( g_ace_channel_desc_table[channel_idx].p_sz_channel_name != 0 )\r
@@ -708,7 +710,7 @@ ACE_get_input_channel_handle
 {\r
     uint16_t channel_idx;\r
     ace_channel_handle_t channel_handle = INVALID_CHANNEL_HANDLE;\r
-    \r
+\r
     for ( channel_idx = 0u;  channel_idx < (uint16_t)ACE_NB_OF_INPUT_CHANNELS; ++channel_idx )\r
     {\r
         if ( g_ace_channel_desc_table[channel_idx].signal_id == channel_id )\r
@@ -732,10 +734,10 @@ ACE_get_ppe_sample
 {\r
     uint16_t sample;\r
     uint16_t ppe_offset;\r
-    \r
+\r
     ppe_offset = g_ace_channel_desc_table[channel_handle].signal_ppe_offset;\r
     sample = (uint16_t)(ACE->PPE_RAM_DATA[ppe_offset] >> 16u);\r
-    \r
+\r
     return sample;\r
 }\r
 \r