Add FreeRTOS-Plus directory.

[freertos] / Demo / CORTEX_EFMG890F128_IAR / CMSIS / CM3 / DeviceSupport / EnergyMicro / EFM32 / system_efm32.c

diff --git a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c b/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c
deleted file mode 100644 (file)
index a5bbf09..0000000
--- a/Demo/CORTEX_EFMG890F128_IAR/CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32/system_efm32.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/**************************************************************************//**\r
- * @file\r
- * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM32 devices\r
- *\r
- * @author Energy Micro AS\r
- * @version 1.0.2\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>\r
- ******************************************************************************\r
- *\r
- * This source code is the property of Energy Micro AS. The source and compiled\r
- * code may only be used on Energy Micro "EFM32" microcontrollers.\r
- *\r
- * This copyright notice may not be removed from the source code nor changed.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no\r
- * obligation to support this Software. Energy Micro AS is providing the\r
- * Software "AS IS", with no express or implied warranties of any kind,\r
- * including, but not limited to, any implied warranties of merchantability\r
- * or fitness for any particular purpose or warranties against infringement\r
- * of any proprietary rights of a third party.\r
- *\r
- * Energy Micro AS will not be liable for any consequential, incidental, or\r
- * special damages, or any other relief, or for any claim by any third party,\r
- * arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#include <stdint.h>\r
-#include "efm32.h"\r
-\r
-uint32_t SystemCoreClock;     /**< System Clock Frequency (Core Clock)  */\r
-\r
-#ifndef EFM32_HFXO_FREQ\r
-#define EFM32_HFXO_FREQ 32000000\r
-#endif\r
-#ifndef EFM32_LFXO_FREQ \r
-#define EFM32_LFXO_FREQ 32768\r
-#endif\r
-#ifndef EFM32_LFRCO_FREQ\r
-#define EFM32_LFRCO_FREQ 32768\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @brief Initialize the system\r
- *\r
- * @param  none\r
- * @return none\r
- *\r
- * @brief  Setup the microcontroller system.\r
- *         Initialize the System and update the SystemCoreClock variable.\r
- *****************************************************************************/\r
-void SystemInit(void)\r
-{\r
-#if EFM32_AUXHFROCO_ENABLE\r
-  CMU_TypeDef *cmu = CMU;\r
-\r
-  /* Enable clocks to debug modules in Cortex */\r
-  /* This will enable Debug Trace and MSC Flash programming clocks */\r
-  cmu->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;\r
-#endif\r
-}\r
-\r
-/**************************************************************************//**\r
- * @brief Update SystemCoreClock variable\r
- *\r
- * @param  none\r
- * @return none\r
- *\r
- * @brief  Updates the SystemCoreClock with current core Clock\r
- *         retrieved from cpu registers.\r
- *****************************************************************************/\r
-void SystemCoreClockUpdate(void)\r
-{\r
-  CMU_TypeDef *cmu = CMU;\r
-  uint32_t inputClock;\r
-\r
-  /* Check source for core clock */\r
-  switch (cmu->STATUS &\r
-          (CMU_STATUS_HFRCOSEL |\r
-           CMU_STATUS_HFXOSEL |\r
-           CMU_STATUS_LFRCOSEL |\r
-           CMU_STATUS_LFXOSEL))\r
-  {\r
-  case CMU_STATUS_HFXOSEL:\r
-    inputClock = EFM32_HFXO_FREQ;\r
-    break;\r
-  case CMU_STATUS_LFRCOSEL:\r
-    inputClock = EFM32_LFRCO_FREQ;\r
-    break;\r
-  case CMU_STATUS_LFXOSEL:\r
-    inputClock = EFM32_LFXO_FREQ;\r
-    break;\r
-  case CMU_STATUS_HFRCOSEL:\r
-  default:\r
-    switch ((cmu->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >> _CMU_HFRCOCTRL_BAND_SHIFT)\r
-    {\r
-    case _CMU_HFRCOCTRL_BAND_28MHZ:\r
-      inputClock = 28000000;\r
-      break;\r
-    case _CMU_HFRCOCTRL_BAND_21MHZ:\r
-      inputClock = 21000000;\r
-      break;\r
-    case _CMU_HFRCOCTRL_BAND_14MHZ:\r
-      inputClock = 14000000;\r
-      break;\r
-    case _CMU_HFRCOCTRL_BAND_11MHZ:\r
-      inputClock = 11000000;\r
-      break;\r
-    case _CMU_HFRCOCTRL_BAND_7MHZ:\r
-      inputClock = 7000000;\r
-      break;\r
-    case _CMU_HFRCOCTRL_BAND_1MHZ:\r
-      inputClock = 1500000;\r
-      break;\r
-    default:\r
-      inputClock = 0;\r
-      break;\r
-    }\r
-    break;\r
-  }\r
-  /* Adjust according to clock divisor */\r
-  SystemCoreClock = inputClock / (1<<((cmu->HFCORECLKDIV & _CMU_HFCORECLKDIV_MASK)>>_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT));\r
-}\r
-\r