Work in progress - checked in for backup only.

[freertos] / Demo / CORTEX_STM32F103_GCC_Rowley / main.c

diff --git a/Demo/CORTEX_STM32F103_GCC_Rowley/main.c b/Demo/CORTEX_STM32F103_GCC_Rowley/main.c
index 7aa1bc3ed24142cc4a3f4387d7ff1529117b594d..ba3761bc4b5cbb18dfddd51a7ce4e8dafe6a27ec 100644 (file)
--- a/Demo/CORTEX_STM32F103_GCC_Rowley/main.c
+++ b/Demo/CORTEX_STM32F103_GCC_Rowley/main.c
@@ -100,28 +100,16 @@ check task has detected an error or not. */
 #define mainCHECK_DELAY_ERROR                          ( ( portTickType ) 500 / portTICK_RATE_MS )\r
 \r
 /* The LED controlled by the 'check' task. */\r
-#define mainCHECK_LED                                          ( 7 )\r
+#define mainCHECK_LED                                          ( 3 )\r
 \r
 /* Task priorities. */\r
 #define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
 #define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
 #define mainCHECK_TASK_PRIORITY                                ( tskIDLE_PRIORITY + 3 )\r
 #define mainFLASH_TASK_PRIORITY                                ( tskIDLE_PRIORITY + 2 )\r
-#define mainLCD_TASK_PRIORITY                          ( tskIDLE_PRIORITY + 3 )\r
 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
 #define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
 \r
-/* The WEB server has a larger stack as it utilises stack hungry string\r
-handling library calls. */\r
-#define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 4 )\r
-\r
-/* The length of the queue used to send messages to the LCD task. */\r
-#define mainQUEUE_SIZE                                         ( 3 )\r
-\r
-/* The period of the system clock in nano seconds.  This is used to calculate\r
-the jitter time in nano seconds. */\r
-#define mainNS_PER_CLOCK                                       ( ( unsigned long ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
-\r
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
@@ -222,31 +210,31 @@ static void prvSetupHardware( void )
        RCC_DeInit ();                        \r
 \r
     /* Enable HSE. */\r
-       RCC_HSEConfig (RCC_HSE_ON);           \r
+       RCC_HSEConfig( RCC_HSE_ON );           \r
        \r
        /* Wait till HSE is ready. */\r
        while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);\r
        \r
     /* HCLK = SYSCLK. */\r
-       RCC_HCLKConfig   (RCC_SYSCLK_Div1);   \r
+       RCC_HCLKConfig( RCC_SYSCLK_Div1 );   \r
 \r
     /* PCLK2  = HCLK. */\r
-       RCC_PCLK2Config  (RCC_HCLK_Div1);     \r
+       RCC_PCLK2Config( RCC_HCLK_Div1 );     \r
 \r
     /* PCLK1  = HCLK/2. */\r
-       RCC_PCLK1Config  (RCC_HCLK_Div2);     \r
+       RCC_PCLK1Config( RCC_HCLK_Div2 );     \r
 \r
        /* ADCCLK = PCLK2/4. */\r
-       RCC_ADCCLKConfig (RCC_PCLK2_Div4);    \r
+       RCC_ADCCLKConfig( RCC_PCLK2_Div4 );    \r
        \r
     /* Flash 2 wait state. */\r
        *( volatile unsigned long  * )0x40022000 = 0x01;           \r
        \r
        /* PLLCLK = 8MHz * 9 = 72 MHz */\r
-       RCC_PLLConfig (RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);\r
+       RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_9 );\r
        \r
     /* Enable PLL. */\r
-       RCC_PLLCmd (ENABLE);                  \r
+       RCC_PLLCmd( ENABLE );\r
        \r
        /* Wait till PLL is ready. */\r
        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);\r
@@ -271,6 +259,12 @@ static void prvSetupHardware( void )
 \r
        /* Initialise the IO used for the LED outputs. */\r
        vParTestInitialise();\r
+\r
+       /* SPI2 Periph clock enable */\r
+       RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );\r
+\r
+       /* Initialize the SPI FLASH driver */\r
+       SPI_FLASH_Init();\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r