]> git.sur5r.net Git - freertos/blobdiff - Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/main.c
Ready for V5.1.1 release.
[freertos] / Demo / ColdFire_MCF52233_Eclipse / RTOSDemo / main.c
index a5915d5ff2e243536ecfd3418838e97bd8dcb48e..45c83512fa807a1e0fa6598c712782a24f885205 100644 (file)
@@ -1,5 +1,5 @@
 /*\r
-       FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+       FreeRTOS.org V5.1.1 - Copyright (C) 2003-2008 Richard Barry.\r
 \r
        This file is part of the FreeRTOS.org distribution.\r
 \r
  * In addition to the standard demo tasks, the following tasks and tests are\r
  * defined and/or created within this file:\r
  *\r
+ * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP\r
+ * processing is performed in this task.  It manages the WEB server functionality.\r
+ *\r
  * "Check" task -  This only executes every five seconds but has a high priority\r
  * to ensure it gets processor time.  Its main function is to check that all the\r
- * standard demo tasks are still operational.  While no errors have been\r
- * discovered the check task will toggle an LED every 5 seconds - the toggle\r
- * rate increasing to 500ms being a visual indication that at least one task has\r
- * reported unexpected behaviour.\r
+ * standard demo tasks are still operational.  An error found in any task will be\r
+ * latched in the ulErrorCode variable for display through the WEB server (the\r
+ * error code is displayed at the foot of the table that contains information on\r
+ * the state of each task).\r
  *\r
  * "Reg test" tasks - These fill the registers with known values, then check\r
  * that each register still contains its expected value.  Each task uses\r
 /* Demo app includes. */\r
 #include "BlockQ.h"\r
 #include "death.h"\r
+#include "blocktim.h"\r
 #include "flash.h"\r
 #include "partest.h"\r
 #include "semtest.h"\r
 #include "PollQ.h"\r
 #include "GenQTest.h"\r
 #include "QPeek.h"\r
+#include "recmutex.h"\r
 #include "IntQueue.h"\r
 #include "comtest2.h"\r
 \r
 \r
 /* The time between cycles of the 'check' functionality - as described at the\r
 top of this file. */\r
-#define mainNO_ERROR_PERIOD                                    ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
-\r
-/* The rate at which the LED controlled by the 'check' task will flash should an\r
-error have been detected. */\r
-#define mainERROR_PERIOD                                       ( ( portTickType ) 500 / portTICK_RATE_MS )\r
-\r
-/* The LED controlled by the 'check' task. */\r
-#define mainCHECK_LED                                          ( 3 )\r
-\r
-/* ComTest constants - there is no free LED for the comtest tasks. */\r
-#define mainCOM_TEST_BAUD_RATE                         ( ( unsigned portLONG ) 19200 )\r
-#define mainCOM_TEST_LED                                       ( 5 )\r
+#define mainCHECK_TASK_PERIOD                                  ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
 \r
 /* Task priorities. */\r
-#define mainCOM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 2 )\r
 #define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2 )\r
 #define mainCHECK_TASK_PRIORITY                                ( tskIDLE_PRIORITY + 3 )\r
 #define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
 #define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
-#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
 #define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
 \r
 /* The WEB server task uses more stack than most other tasks because of its\r
-reliance on using sprintf(). */
+reliance on using sprintf(). */\r
 #define mainBASIC_WEB_STACK_SIZE                       ( configMINIMAL_STACK_SIZE * 2 )\r
 \r
-static unsigned portLONG ulErrorCode = 0UL;\r
-\r
 /*\r
  * Configure the hardware for the demo.\r
  */\r
@@ -134,10 +124,25 @@ static void prvSetupHardware( void );
 static void prvCheckTask( void *pvParameters );\r
 \r
 /*\r
- * The task that implements the WEB server.
+ * The task that implements the WEB server.\r
  */\r
 extern void vuIP_Task( void *pvParameters );\r
 \r
+/*\r
+ * Implement the 'Reg test' functionality as described at the top of this file.\r
+ */\r
+static void vRegTest1Task( void *pvParameters );\r
+static void vRegTest2Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counters used to detect errors within the reg test tasks. */\r
+static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
+\r
+/* Any errors that the check task finds in any tasks are latched into \r
+ulErrorCode, and then displayed via the WEB server. */\r
+static unsigned portLONG ulErrorCode = 0UL;\r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 int main( void )\r
@@ -151,10 +156,16 @@ int main( void )
        /* Start the standard demo tasks. */\r
        vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
        vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+    vCreateBlockTimeTasks();\r
        vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
        vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
        vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
        vStartQueuePeekTasks();\r
+    vStartRecursiveMutexTasks();\r
+\r
+       /* Start the reg test tasks - defined in this file. */\r
+       xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
+       xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 \r
        /* Create the check task. */\r
        xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
@@ -162,7 +173,7 @@ int main( void )
        /* Start the scheduler. */\r
        vTaskStartScheduler();\r
 \r
-    /* Will only get here if there was insufficient memory to create the idle\r
+    /* Will only get here if there was insufficient heap to create the idle\r
     task. */\r
        for( ;; );\r
 }\r
@@ -170,8 +181,10 @@ int main( void )
 \r
 static void prvCheckTask( void *pvParameters )\r
 {\r
+unsigned ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 portTickType xLastExecutionTime;\r
 \r
+       /* To prevent compiler warnings. */\r
        ( void ) pvParameters;\r
 \r
        /* Initialise the variable used to control our iteration rate prior to\r
@@ -181,7 +194,7 @@ portTickType xLastExecutionTime;
        for( ;; )\r
        {\r
                /* Wait until it is time to run the tests again. */\r
-               vTaskDelayUntil( &xLastExecutionTime, mainNO_ERROR_PERIOD );\r
+               vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD );\r
 \r
                /* Has an error been found in any task? */\r
                if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
@@ -208,12 +221,38 @@ portTickType xLastExecutionTime;
            {\r
                ulErrorCode |= 0x40UL;\r
            }\r
+\r
+               if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+               {\r
+                       ulErrorCode |= 0x80UL;\r
+               }\r
+\r
+           if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+           {\r
+               ulErrorCode |= 0x100UL;\r
+           }\r
+\r
+               if( ulLastRegTest1Count == ulRegTest1Counter )\r
+               {\r
+                       ulErrorCode |= 0x200UL;\r
+               }\r
+\r
+               if( ulLastRegTest2Count == ulRegTest2Counter )\r
+               {\r
+                       ulErrorCode |= 0x200UL;\r
+               }\r
+\r
+               /* Remember the reg test counts so a stall in their values can be\r
+               detected next time around. */\r
+               ulLastRegTest1Count = ulRegTest1Counter;\r
+               ulLastRegTest2Count = ulRegTest2Counter;\r
        }\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 unsigned portLONG ulGetErrorCode( void )\r
 {\r
+       /* Returns the error code for display via the WEB server. */\r
        return ulErrorCode;\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -282,3 +321,157 @@ void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTask
 }\r
 /*-----------------------------------------------------------*/\r
 \r
+static void vRegTest1Task( void *pvParameters )\r
+{\r
+       /* Sanity check - did we receive the parameter expected? */\r
+       if( pvParameters != &ulRegTest1Counter )\r
+       {\r
+               /* Change here so the check task can detect that an error occurred. */\r
+               for( ;; );\r
+       }\r
+\r
+       /* Set all the registers to known values, then check that each retains its\r
+       expected value - as described at the top of this file.  If an error is\r
+       found then the loop counter will no longer be incremented allowing the check\r
+       task to recognise the error. */\r
+       asm volatile    (       "reg_test_1_start:                                              \n\t"\r
+                                               "       moveq           #1, %d0                                 \n\t"\r
+                                               "       moveq           #2, %d1                                 \n\t"\r
+                                               "       moveq           #3, %d2                                 \n\t"\r
+                                               "       moveq           #4, %d3                                 \n\t"\r
+                                               "       moveq           #5, %d4                                 \n\t"\r
+                                               "       moveq           #6, %d5                                 \n\t"\r
+                                               "       moveq           #7, %d6                                 \n\t"\r
+                                               "       moveq           #8, %d7                                 \n\t"\r
+                                               "       move            #9, %a0                                 \n\t"\r
+                                               "       move            #10, %a1                                \n\t"\r
+                                               "       move            #11, %a2                                \n\t"\r
+                                               "       move            #12, %a3                                \n\t"\r
+                                               "       move            #13, %a4                                \n\t"\r
+                                               "       move            #14, %a5                                \n\t"\r
+                                               "       move            #15, %a6                                \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #1, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #2, %d1                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #3, %d2                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #4, %d3                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #5, %d4                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #6, %d5                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #7, %d6                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #8, %d7                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #9, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #10, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #11, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #12, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #13, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #14, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #15, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest1Counter  \n\t"\r
+                                               "       bra                     reg_test_1_start                \n\t"\r
+                                               "reg_test_1_error:                                              \n\t"\r
+                                               "       bra                     reg_test_1_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+       /* Sanity check - did we receive the parameter expected? */\r
+       if( pvParameters != &ulRegTest2Counter )\r
+       {\r
+               /* Change here so the check task can detect that an error occurred. */\r
+               for( ;; );\r
+       }\r
+\r
+       /* Set all the registers to known values, then check that each retains its\r
+       expected value - as described at the top of this file.  If an error is\r
+       found then the loop counter will no longer be incremented allowing the check\r
+       task to recognise the error. */\r
+       asm volatile    (       "reg_test_2_start:                                              \n\t"\r
+                                               "       moveq           #10, %d0                                \n\t"\r
+                                               "       moveq           #20, %d1                                \n\t"\r
+                                               "       moveq           #30, %d2                                \n\t"\r
+                                               "       moveq           #40, %d3                                \n\t"\r
+                                               "       moveq           #50, %d4                                \n\t"\r
+                                               "       moveq           #60, %d5                                \n\t"\r
+                                               "       moveq           #70, %d6                                \n\t"\r
+                                               "       moveq           #80, %d7                                \n\t"\r
+                                               "       move            #90, %a0                                \n\t"\r
+                                               "       move            #100, %a1                               \n\t"\r
+                                               "       move            #110, %a2                               \n\t"\r
+                                               "       move            #120, %a3                               \n\t"\r
+                                               "       move            #130, %a4                               \n\t"\r
+                                               "       move            #140, %a5                               \n\t"\r
+                                               "       move            #150, %a6                               \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #10, %d0                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #20, %d1                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #30, %d2                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #40, %d3                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #50, %d4                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #60, %d5                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #70, %d6                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #80, %d7                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #90, %d0                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #100, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #110, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #120, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #130, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #140, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #150, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest2Counter  \n\t"\r
+                                               "       bra                     reg_test_2_start                \n\t"\r
+                                               "reg_test_2_error:                                              \n\t"\r
+                                               "       bra                     reg_test_2_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r