]> git.sur5r.net Git - freertos/blobdiff - Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/main.c
Remove unnecessary use of portLONG, portCHAR and portSHORT.
[freertos] / Demo / ColdFire_MCF5282_Eclipse / RTOSDemo / main.c
index 1f1b3978bc424e1720dfac3a8d81e1e5eca13fa1..9f588b8a8e4ff1c2eb69a79656a55fd0fb2f726f 100644 (file)
@@ -1,50 +1,49 @@
 /*\r
-       FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+    FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.\r
 \r
-       This file is part of the FreeRTOS.org distribution.\r
+    This file is part of the FreeRTOS distribution.\r
 \r
-       FreeRTOS.org is free software; you can redistribute it and/or modify\r
-       it under the terms of the GNU General Public License as published by\r
-       the Free Software Foundation; either version 2 of the License, or\r
-       (at your option) any later version.\r
+    FreeRTOS is free software; you can redistribute it and/or modify it    under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation and modified by the FreeRTOS exception.\r
+    **NOTE** The exception to the GPL is included to allow you to distribute a\r
+    combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    Alternative commercial license and support terms are also available upon\r
+    request.  See the licensing section of http://www.FreeRTOS.org for full\r
+    license details.\r
 \r
-       FreeRTOS.org is distributed in the hope that it will be useful,\r
-       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
-       GNU General Public License for more details.\r
+    FreeRTOS is distributed in the hope that it will be useful,    but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details.\r
 \r
-       You should have received a copy of the GNU General Public License\r
-       along with FreeRTOS.org; if not, write to the Free Software\r
-       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+    You should have received a copy of the GNU General Public License along\r
+    with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+    Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
 \r
-       A special exception to the GPL can be applied should you wish to distribute\r
-       a combined work that includes FreeRTOS.org, without being obliged to provide\r
-       the source code for any proprietary components.  See the licensing section\r
-       of http://www.FreeRTOS.org for full details of how and when the exception\r
-       can be applied.\r
 \r
-    ***************************************************************************\r
     ***************************************************************************\r
     *                                                                         *\r
-    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *\r
-    * and even write all or part of your application on your behalf.          *\r
-    * See http://www.OpenRTOS.com for details of the services we provide to   *\r
-    * expedite your project.                                                  *\r
+    * The FreeRTOS eBook and reference manual are available to purchase for a *\r
+    * small fee. Help yourself get started quickly while also helping the     *\r
+    * FreeRTOS project! See http://www.FreeRTOS.org/Documentation for details *\r
     *                                                                         *\r
     ***************************************************************************\r
-    ***************************************************************************\r
 \r
-       Please ensure to read the configuration and relevant port sections of the\r
-       online documentation.\r
+    1 tab == 4 spaces!\r
+\r
+    Please ensure to read the configuration and relevant port sections of the\r
+    online documentation.\r
 \r
-       http://www.FreeRTOS.org - Documentation, latest information, license and\r
-       contact details.\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
 \r
-       http://www.SafeRTOS.com - A version that is certified for use in safety\r
-       critical systems.\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
 \r
-       http://www.OpenRTOS.com - Commercial support, development, porting,\r
-       licensing and training services.\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
 */\r
 \r
 \r
  * to ensure it gets processor time.  Its main function is to check that all the\r
  * standard demo tasks are still operational.  While no errors have been\r
  * discovered the check task will toggle an LED every 5 seconds - the toggle\r
- * rate increasing to 500ms then being a visual indication that at least one\r
- * task has reported unexpected behaviour.\r
+ * rate increasing to 500ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value.  Each task uses\r
+ * different values.  The tasks run with very low priority so get preempted very\r
+ * frequently.  A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
  *\r
  */\r
 \r
@@ -76,7 +81,6 @@
 #include "BlockQ.h"\r
 #include "death.h"\r
 #include "integer.h"\r
-#include "blocktim.h"\r
 #include "flash.h"\r
 #include "partest.h"\r
 #include "semtest.h"\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
-/* The time between cycles of the 'check' functionality (defined within the\r
-tick hook. */\r
+/* The time between cycles of the 'check' functionality - as described at the\r
+top of this file. */\r
 #define mainNO_ERROR_PERIOD                                    ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
 \r
-/* The rate at which the LED controlled by the 'check' task will flash when an\r
-error has been detected. */\r
-#define mainERROR_PERIOD                                       ( 500 )\r
+/* The rate at which the LED controlled by the 'check' task will flash should an\r
+error have been detected. */\r
+#define mainERROR_PERIOD                                       ( ( portTickType ) 500 / portTICK_RATE_MS )\r
 \r
 /* The LED controlled by the 'check' task. */\r
 #define mainCHECK_LED                                          ( 3 )\r
 \r
-/* Contest constants - there is no free LED for the comtest. */\r
-#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
-#define mainCOM_TEST_LED               ( 5 )\r
+/* ComTest constants - there is no free LED for the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE                         ( ( unsigned portLONG ) 19200 )\r
+#define mainCOM_TEST_LED                                       ( 5 )\r
 \r
 /* Task priorities. */\r
 #define mainCOM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 2 )\r
@@ -110,7 +114,7 @@ error has been detected. */
 #define mainCHECK_TASK_PRIORITY                                ( tskIDLE_PRIORITY + 3 )\r
 #define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
 #define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
-#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 3 )\r
+#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
 #define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
 \r
@@ -125,17 +129,27 @@ static void prvSetupHardware( void );
  */\r
 static void prvCheckTask( void *pvParameters );\r
 \r
+/*\r
+ * Implement the 'Reg test' functionality as described at the top of this file.\r
+ */\r
+static void vRegTest1Task( void *pvParameters );\r
+static void vRegTest2Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counters used to detect errors within the reg test tasks. */\r
+static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
 int main( void )\r
 {\r
+       /* Setup the hardware ready for this demo. */\r
        prvSetupHardware();\r
 \r
        /* Start the standard demo tasks. */\r
        vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
        vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
-       vCreateBlockTimeTasks();\r
        vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
        vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
        vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
@@ -143,6 +157,11 @@ int main( void )
        vStartQueuePeekTasks();\r
        vStartRecursiveMutexTasks();\r
        vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+       vStartInterruptQueueTasks();\r
+\r
+       /* Start the reg test tasks - defined in this file. */\r
+       xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
+       xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 \r
        /* Create the check task. */\r
        xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
@@ -163,7 +182,7 @@ int main( void )
 \r
 static void prvCheckTask( void *pvParameters )\r
 {\r
-unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0;\r
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 portTickType xLastExecutionTime;\r
 \r
        ( void ) pvParameters;\r
@@ -182,48 +201,73 @@ portTickType xLastExecutionTime;
                {\r
                        ulError |= 0x01UL;\r
                }\r
-               else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
                {\r
                        ulError |= 0x02UL;\r
                }\r
-               else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+\r
+               if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
                {\r
                        ulError |= 0x04UL;\r
                }\r
-               else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
-               {\r
-                       ulError |= 0x10UL;\r
-               }\r
-           else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x20UL;\r
            }\r
-           else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+\r
+               if( xArePollingQueuesStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x40UL;\r
            }\r
-           else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+\r
+               if( xIsCreateTaskStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x80UL;\r
            }\r
-           else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+\r
+               if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x100UL;\r
            }\r
-           else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x200UL;\r
            }\r
-           else if( xAreComTestTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreComTestTasksStillRunning() != pdTRUE )\r
                {\r
                ulError |= 0x400UL;\r
                }\r
 \r
+               if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+           {\r
+               ulError |= 0x800UL;\r
+           }\r
+\r
+               if( ulLastRegTest1Count == ulRegTest1Counter )\r
+               {\r
+                       ulError |= 0x1000UL;\r
+               }\r
+\r
+               if( ulLastRegTest2Count == ulRegTest2Counter )\r
+               {\r
+                       ulError |= 0x1000UL;\r
+               }\r
+\r
+               ulLastRegTest1Count = ulRegTest1Counter;\r
+               ulLastRegTest2Count = ulRegTest2Counter;\r
+\r
+               /* If an error has been found then increase our cycle rate, and in so\r
+               going increase the rate at which the check task LED toggles. */\r
                if( ulError != 0 )\r
                {\r
                ulTicksToWait = mainERROR_PERIOD;\r
                }\r
 \r
+               /* Toggle the LED each itteration. */\r
                vParTestToggleLED( mainCHECK_LED );\r
        }\r
 }\r
@@ -231,6 +275,14 @@ portTickType xLastExecutionTime;
 \r
 void prvSetupHardware( void )\r
 {\r
+extern void mcf5xxx_wr_cacr( unsigned portLONG );\r
+\r
+       portDISABLE_INTERRUPTS();\r
+\r
+       /* Enable the cache. */\r
+       mcf5xxx_wr_cacr( MCF5XXX_CACR_CENB | MCF5XXX_CACR_CINV | MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB | MCF5XXX_CACR_CLNF_00 );\r
+       asm volatile( "NOP" ); /* As per errata. */\r
+\r
        /* Multiply 8Mhz reference crystal by 8 to achieve system clock of 64Mhz. */\r
        MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD( 2 );\r
 \r
@@ -240,16 +292,176 @@ void prvSetupHardware( void )
                __asm__ volatile ( "NOP" );\r
        }\r
 \r
+       /* Setup the port used to toggle LEDs. */\r
        vParTestInitialise();\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
 {\r
+       /* This will get called if a stack overflow is detected during the context\r
+       switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
+       problems within nested interrupts, but only do this for debug purposes as\r
+       it will increase the context switch time. */\r
+\r
        ( void ) pxTask;\r
        ( void ) pcTaskName;\r
 \r
        for( ;; );\r
 }\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest1Task( void *pvParameters )\r
+{\r
+       /* Sanity check - did we receive the parameter expected? */\r
+       if( pvParameters != &ulRegTest1Counter )\r
+       {\r
+               /* Change here so the check task can detect that an error occurred. */\r
+               for( ;; );\r
+       }\r
+\r
+       /* Set all the registers to known values, then check that each retains its\r
+       expected value - as described at the top of this file.  If an error is\r
+       found then the loop counter will no longer be incremented allowing the check\r
+       task to recognise the error. */\r
+       asm volatile    (       "reg_test_1_start:                                              \n\t"\r
+                                               "       moveq           #1, %d0                                 \n\t"\r
+                                               "       moveq           #2, %d1                                 \n\t"\r
+                                               "       moveq           #3, %d2                                 \n\t"\r
+                                               "       moveq           #4, %d3                                 \n\t"\r
+                                               "       moveq           #5, %d4                                 \n\t"\r
+                                               "       moveq           #6, %d5                                 \n\t"\r
+                                               "       moveq           #7, %d6                                 \n\t"\r
+                                               "       moveq           #8, %d7                                 \n\t"\r
+                                               "       move            #9, %a0                                 \n\t"\r
+                                               "       move            #10, %a1                                \n\t"\r
+                                               "       move            #11, %a2                                \n\t"\r
+                                               "       move            #12, %a3                                \n\t"\r
+                                               "       move            #13, %a4                                \n\t"\r
+                                               "       move            #14, %a5                                \n\t"\r
+                                               "       move            #15, %a6                                \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #1, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #2, %d1                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #3, %d2                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #4, %d3                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #5, %d4                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #6, %d5                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #7, %d6                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #8, %d7                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #9, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #10, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #11, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #12, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #13, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #14, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #15, %d0                                \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest1Counter  \n\t"\r
+                                               "       bra                     reg_test_1_start                \n\t"\r
+                                               "reg_test_1_error:                                              \n\t"\r
+                                               "       bra                     reg_test_1_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
 \r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+       /* Sanity check - did we receive the parameter expected? */\r
+       if( pvParameters != &ulRegTest2Counter )\r
+       {\r
+               /* Change here so the check task can detect that an error occurred. */\r
+               for( ;; );\r
+       }\r
+\r
+       /* Set all the registers to known values, then check that each retains its\r
+       expected value - as described at the top of this file.  If an error is\r
+       found then the loop counter will no longer be incremented allowing the check\r
+       task to recognise the error. */\r
+       asm volatile    (       "reg_test_2_start:                                              \n\t"\r
+                                               "       moveq           #10, %d0                                \n\t"\r
+                                               "       moveq           #20, %d1                                \n\t"\r
+                                               "       moveq           #30, %d2                                \n\t"\r
+                                               "       moveq           #40, %d3                                \n\t"\r
+                                               "       moveq           #50, %d4                                \n\t"\r
+                                               "       moveq           #60, %d5                                \n\t"\r
+                                               "       moveq           #70, %d6                                \n\t"\r
+                                               "       moveq           #80, %d7                                \n\t"\r
+                                               "       move            #90, %a0                                \n\t"\r
+                                               "       move            #100, %a1                               \n\t"\r
+                                               "       move            #110, %a2                               \n\t"\r
+                                               "       move            #120, %a3                               \n\t"\r
+                                               "       move            #130, %a4                               \n\t"\r
+                                               "       move            #140, %a5                               \n\t"\r
+                                               "       move            #150, %a6                               \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #10, %d0                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #20, %d1                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #30, %d2                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #40, %d3                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #50, %d4                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #60, %d5                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #70, %d6                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #80, %d7                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #90, %d0                                \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #100, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #110, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #120, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #130, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #140, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #150, %d0                               \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest2Counter  \n\t"\r
+                                               "       bra                     reg_test_2_start                \n\t"\r
+                                               "reg_test_2_error:                                              \n\t"\r
+                                               "       bra                     reg_test_2_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
 \r