Update Cortex M3 ports to ensure 8 byte alignment.

[freertos] / Demo / PPC440_DP_FPU_Xilinx_Virtex5_GCC / system_incl.make

diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system_incl.make b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system_incl.make
index 2a92ab54435a64ac5c43bfafcff609b1434c41c8..8330c1299f9abc07ebeedf7a3aadc42f647d2fc8 100644 (file)
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system_incl.make
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system_incl.make
@@ -57,9 +57,9 @@ TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
 \r
 DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)\r
 \r
-MIX_LANG_SIM_OPT = -mixed yes\r
+MIX_LANG_SIM_OPT = -mixed no\r
 \r
-SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/\r
+SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -sd implementation/ -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/\r
 \r
 \r
 LIBRARIES =  \\r