New MicroBlaze port: Added a FreeRTOS exception handler, and installed it in each...

[freertos] / Demo / PPC440_Xilinx_Virtex5_GCC / system.log

diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/system.log b/Demo/PPC440_Xilinx_Virtex5_GCC/system.log
index 6ce55ba3fb66a5df01c9fead9e32e333a6f7eb88..179be9a5f0124ba7a9f8347b765631005b89f1a8 100644 (file)
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/system.log
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/system.log
@@ -223,6 +223,4342 @@ rm -f __xps/ise/_xmsgs/libgen.xmsgs
 rm -f RTOSDemo/executable.elf \r
 \r
 \r
+Done!
+\r
+Writing filter settings....
+\r
+Done writing filter settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
+\r
+Done writing Tab View settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
+\r
+Xilinx Platform Studio (XPS)\r
+Xilinx EDK 11.2 Build EDK_LS3.47
+\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
+\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
+\r
+Generating Block Diagram to Buffer 
+\r
+Generated Block Diagram SVG
+\r
+At Local date and time: Tue Jun 30 20:53:14 2009
+ make -f system.make program started...
+\r
+*********************************************\r
+Creating software libraries...\r
+*********************************************\r
+libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss\r
+libgen\r\r
+Xilinx EDK 11.2 Build EDK_LS3.47\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+\r\r
+Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
+__xps/ise/xmsgprops.lst system.mss \r\r
+\r\r
+Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   251 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   251 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - deprecated core for architecture 'virtex5fx'!\r\r
+\r\r
+Checking platform configuration ...\r\r
+IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+107 - 1 master(s) : 12 slave(s)\r\r
+IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+288 - 1 master(s) : 1 slave(s)\r\r
+\r\r
+Checking port drivers...\r\r
+WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   446 - floating connection!\r\r
+\r\r
+Performing Clock DRCs...\r\r
+\r\r
+Performing Reset DRCs...\r\r
+\r\r
+Overriding system level properties...\r\r
+\r\r
+Running system level update procedures...\r\r
+\r\r
+Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
+\r\r
+Running system level DRCs...\r\r
+\r\r
+Performing System level DRCs on properties...\r\r
+\r\r
+Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
+WARNING:EDK:494 -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not\r\r
+   found.\r\r
+WARNING:EDK:2530 - Timing and Resource utilization information not added\r\r
+WARNING:EDK:411 - pcie -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
+   77 - deprecated driver!\r\r
+WARNING:EDK:411 - emaclite -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
+   83 - deprecated driver!\r\r
+INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
+  - DDR2_SDRAM\r\r
+  - DIP_Switches_8Bit\r\r
+  - Ethernet_MAC\r\r
+  - IIC_EEPROM\r\r
+  - LEDs_8Bit\r\r
+  - LEDs_Positions\r\r
+  - PCIe_Bridge\r\r
+  - Push_Buttons_5Bit\r\r
+  - RS232_Uart_1\r\r
+  - SRAM\r\r
+  - SysACE_CompactFlash\r\r
+  - xps_bram_if_cntlr_1\r\r
+  - xps_intc_0\r\r
+\r\r
+-- Generating libraries for processor: ppc440_0 --\r\r
+\r\r
+\r\r
+Staging source files.\r\r
+Running DRCs.\r\r
+Running generate.\r\r
+Running post_generate.\r\r
+Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
+"EXTRA_COMPILER_FLAGS=-g"'.\r\r
+\r\r
+Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
+"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
+"EXTRA_COMPILER_FLAGS=-g"'.\r\r
+Compiling common\r
+powerpc-eabi-ar: creating ../../../lib/libxil.a
+\r
+Compiling lldma\r
+Compiling standalone\r
+Compiling gpio\r
+Compiling emaclite\r
+Compiling iic\r
+Compiling pci\r
+Compiling uartlite\r
+Compiling sysace\r
+Compiling intc\r
+Compiling cpu_ppc440\r
+Running execs_generate.\r\r
+powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
+    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
+-D GCC_PPC440 -mregnames  \r
+powerpc-eabi-size RTOSDemo/executable.elf \r
+   text           data     bss     dec     hex filename\r
+  53754            372   86524  140650   2256a RTOSDemo/executable.elf\r
+\r
+\r
+Done!
+\r
+Writing filter settings....
+\r
+Done writing filter settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
+\r
+Done writing Tab View settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
+\r
+Xilinx Platform Studio (XPS)\r
+Xilinx EDK 11.2 Build EDK_LS3.47
+\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
+\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
+\r
+Generating Block Diagram to Buffer 
+\r
+Generated Block Diagram SVG
+\r
+At Local date and time: Tue Jun 30 21:05:40 2009
+ make -f system.make bits started...
+\r
+****************************************************\r
+Creating system netlist for hardware specification..\r
+****************************************************\r
+platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs\r
+\r\r
+Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
+ (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+\r\r
+\r\r
+Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
+__xps/ise/xmsgprops.lst system.mhs \r\r
+\r\r
+Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs\r\r
+...\r\r
+\r\r
+Read MPD definitions ...\r\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   251 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   251 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - deprecated core for architecture 'virtex5fx'!\r\r
+\r\r
+Overriding IP level properties ...\r\r
+\r\r
+Performing IP level DRCs on properties...\r\r
+\r\r
+Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
+Address Map for Processor ppc440_0\r\r
+  (0b0000000000-0b0011111111) ppc440_0 \r\r
+  (0000000000-0x0fffffff) DDR2_SDRAM   ppc440_0_PPC440MC\r\r
+  (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
+  (0x81400000-0x8140ffff) Push_Buttons_5Bit    plb_v46_0\r\r
+  (0x81420000-0x8142ffff) LEDs_Positions       plb_v46_0\r\r
+  (0x81440000-0x8144ffff) LEDs_8Bit    plb_v46_0\r\r
+  (0x81460000-0x8146ffff) DIP_Switches_8Bit    plb_v46_0\r\r
+  (0x81600000-0x8160ffff) IIC_EEPROM   plb_v46_0\r\r
+  (0x81800000-0x8180ffff) xps_intc_0   plb_v46_0\r\r
+  (0x83600000-0x8360ffff) SysACE_CompactFlash  plb_v46_0\r\r
+  (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
+  (0x85c00000-0x85c0ffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xc0000000-0xdfffffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xe0000000-0xefffffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
+  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1  plb_v46_0\r\r
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
+   01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
+   C_SPLB0_P2P value to 0\r\r
+\r\r
+Computing clock values...\r\r
+INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
+   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
+   performed for IPs connected to that clock port, unless they are connected\r\r
+   through the clock generator IP. \r\r
+\r\r
+INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
+   'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
+   performed for IPs connected to that clock port, unless they are connected\r\r
+   through the clock generator IP. \r\r
+\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_SLAVES value to 12\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_PLBV46_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
+   PARAMETER C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
+   PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
+   PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
+   value to 0x2000\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PORT_DWIDTH value to 64\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
+   value to 8\r\r
+INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
+   _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
+   ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
+   a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
+   a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
+   C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
+   C_MPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
+   C_MPLB_SMALLEST_SLAVE value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
+   C_SPLB_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
+   C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
+   C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_SLAVES value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_PLBV46_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
+   2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
+   PARAMETER C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
+   C_SPLB_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
+   C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
+   ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+\r\r
+Checking platform address map ...\r\r
+\r\r
+Checking platform configuration ...\r\r
+INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - This design requires design constraints to guarantee performance.\r\r
+   Please refer to the xps_ethernetlite_v2_00_a data sheet for details.  \r\r
+   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
+   Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
+   operation.\r\r
+IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+107 - 1 master(s) : 12 slave(s)\r\r
+IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+288 - 1 master(s) : 1 slave(s)\r\r
+\r\r
+Checking port drivers...\r\r
+WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   446 - floating connection!\r\r
+\r\r
+Performing Clock DRCs...\r\r
+\r\r
+Performing Reset DRCs...\r\r
+\r\r
+Overriding system level properties...\r\r
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
+   01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
+   C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
+   01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
+   C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
+INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
+   1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
+   C_NUM_PPC_USED value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
+   ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
+   value to 0b00000000000000000000000000000001\r\r
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
+   ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
+   value to 0b00000000000000000000000000000001\r\r
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
+   ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
+   value to 0b00000000000000000000000000000000\r\r
+\r\r
+Running system level update procedures...\r\r
+\r\r
+Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
+\r\r
+Running system level DRCs...\r\r
+\r\r
+Performing System level DRCs on properties...\r\r
+\r\r
+Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
+\r\r
+Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
+INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
+implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
+It can be overridden by constraints placed in the system.ucf file.\r\r\r
+\r\r
+\r\r\r
+\r\r
+INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
+implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
+It can be overridden by constraints placed in the system.ucf file.\r\r\r
+\r\r
+\r\r\r
+\r\r
+INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
+implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
+It can be overridden by constraints placed in the system.ucf file.\r\r\r
+\r\r
+\r\r\r
+\r\r
+\r\r
+Modify defaults ...\r\r
+\r\r
+Creating stub ...\r\r
+\r\r
+Processing licensed instances ...\r\r
+Completion time: 0.00 seconds\r\r
+\r\r
+Creating hardware output directories ...\r\r
+\r\r
+Managing hardware (BBD-specified) netlist files ...\r\r
+IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+251 - Copying (BBD-specified) netlist files.\r\r
+IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+296 - Copying (BBD-specified) netlist files.\r\r
+\r\r
+Managing cache ...\r\r
+\r\r
+Elaborating instances ...\r\r
+IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+129 - elaborating IP\r\r
+\r\r
+Writing HDL for elaborated instances ...\r\r
+\r\r
+Inserting wrapper level ...\r\r
+Completion time: 1.00 seconds\r\r
+\r\r
+Constructing platform-level connectivity ...\r\r
+Completion time: 1.00 seconds\r\r
+\r\r
+Writing (top-level) BMM ...\r\r
+\r\r
+Writing (top-level and wrappers) HDL ...\r\r
+\r\r
+Generating synthesis project file ...\r\r
+\r\r
+Running XST synthesis ...\r\r
+\r\r
+INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
+   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
+   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
+INSTANCE:ppc440_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
+- Running XST synthesis\r\r
+INSTANCE:plb_v46_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+107 - Running XST synthesis\r\r
+INSTANCE:xps_bram_if_cntlr_1 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+116 - Running XST synthesis\r\r
+INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+129 - Running XST synthesis\r\r
+INSTANCE:rs232_uart_1 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+136 - Running XST synthesis\r\r
+INSTANCE:leds_8bit -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+152 - Running XST synthesis\r\r
+INSTANCE:leds_positions -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+166 - Running XST synthesis\r\r
+INSTANCE:push_buttons_5bit -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+180 - Running XST synthesis\r\r
+INSTANCE:dip_switches_8bit -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+194 - Running XST synthesis\r\r
+INSTANCE:iic_eeprom -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+208 - Running XST synthesis\r\r
+INSTANCE:sram -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+221 - Running XST synthesis\r\r
+INSTANCE:pcie_bridge -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+251 - Running XST synthesis\r\r
+INSTANCE:ppc440_0_splb0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+288 - Running XST synthesis\r\r
+INSTANCE:ethernet_mac -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+296 - Running XST synthesis\r\r
+INSTANCE:ddr2_sdram -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+315 - Running XST synthesis\r\r
+INSTANCE:sysace_compactflash -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+375 - Running XST synthesis\r\r
+INSTANCE:clock_generator_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+392 - Running XST synthesis\r\r
+INSTANCE:jtagppc_cntlr_inst -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+431 - Running XST synthesis\r\r
+INSTANCE:proc_sys_reset_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+437 - Running XST synthesis\r\r
+INSTANCE:xps_intc_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+449 - Running XST synthesis\r\r
+\r\r
+Running NGCBUILD ...\r\r
+IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
+- Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
+ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp\r\r
+c440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
+\r\r
+Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  7 sec\r\r
+Total CPU time to NGCBUILD completion:   6 sec\r\r
+\r\r
+Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+136 - Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
+../rs232_uart_1_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/rs\r\r
+232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  8 sec\r\r
+Total CPU time to NGCBUILD completion:   2 sec\r\r
+\r\r
+Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+251 - Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
+pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc\r\r
+ie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
+Executing edif2ngd -noa\r\r
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
+ie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
+"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
+Release 11.2 - edif2ngd L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
+INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
+with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
+Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
+Loading design module\r\r
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
+ie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
+Loading design module\r\r
+"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
+Loading design module\r\r
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
+ie_bridge_wrapper/dpram_70_512.ngc"...\r\r
+Loading design module\r\r
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
+ie_bridge_wrapper/fifo_71x512.ngc"...\r\r
+\r\r
+Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  13 sec\r\r
+Total CPU time to NGCBUILD completion:   9 sec\r\r
+\r\r
+Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+296 - Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
+ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/et\r\r
+hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
+Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
+"ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
+Release 11.2 - edif2ngd L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
+INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
+with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
+Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
+Loading design module\r\r
+"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\et\r\r
+hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
+\r\r
+Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  9 sec\r\r
+Total CPU time to NGCBUILD completion:   6 sec\r\r
+\r\r
+Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+315 - Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
+ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd\r\r
+r2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
+\r\r
+Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  7 sec\r\r
+Total CPU time to NGCBUILD completion:   7 sec\r\r
+\r\r
+Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
+C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+449 - Running NGCBUILD\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
+xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
+../xps_intc_0_wrapper.ngc\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xp\r\r
+s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  1 sec\r\r
+Total CPU time to NGCBUILD completion:   1 sec\r\r
+\r\r
+Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+\r\r
+Rebuilding cache ...\r\r
+\r\r
+Total run time: 1039.00 seconds\r\r
+Running synthesis...\r
+bash -c "cd synthesis; ./synthesis.sh"\r
+xst -ifn system_xst.scr -intstyle silent\r
+Running XST synthesis ...\r
+XST completed\r
+Release 11.2 - ngcbuild L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+Overriding Xilinx file <ngcflow.csf> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
+\r\r
+Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
+./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
+../__xps/ise/system.ise\r\r
+\r\r
+Reading NGO file\r\r
+"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/synthesis/system.\r\r
+ngc" ...\r\r
+Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
+Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
+Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
+Loading design module\r\r
+"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
+Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
+Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
+Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
+Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
+Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
+Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
+Loading design module "../implementation/sram_wrapper.ngc"...\r\r
+Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
+Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
+Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
+Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
+Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
+Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
+Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
+Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
+Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGCBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings:   0\r\r
+\r\r
+Writing NGC file "../implementation/system.ngc" ...\r\r
+Total REAL time to NGCBUILD completion:  10 sec\r\r
+Total CPU time to NGCBUILD completion:   9 sec\r\r
+\r\r
+Writing NGCBUILD log file "../implementation/system.blc"...\r\r
+\r\r
+NGCBUILD done.\r\r
+*********************************************\r
+Running Xilinx Implementation tools..\r
+*********************************************\r
+xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
+Release 11.2 - Xflow L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
+../__xps/ise/system.ise system.ngc  \r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
+working directory\r\r
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation \r\r
+\r\r
+Using Flow File:\r\r
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/fpg\r\r
+a.flw \r\r
+Using Option File(s): \r\r
+ C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xf\r\r
+low.opt \r\r
+\r\r
+Creating Script File ... \r\r
+\r\r
+#----------------------------------------------#\r\r
+# Starting program ngdbuild\r\r
+# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
+system.bmm\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
+stem.ngc" -uc system.ucf system.ngd \r\r
+#----------------------------------------------#\r\r
+Release 11.2 - ngdbuild L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+\r\r
+Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
+timestamp -bm system.bmm\r\r
+C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sys\r\r
+tem.ngc -uc system.ucf system.ngd\r\r
+\r\r
+Reading NGO file\r\r
+"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
+stem.ngc" ...\r\r
+Gathering constraint information from source properties...\r\r
+Done.\r\r
+\r\r
+Applying constraints in "system.ucf" to the design...\r\r
+WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
+   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
+   ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
+   'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
+   In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
+   should be changed in this same manner in the source netlist or constraint\r\r
+   file.\r\r
+Resolving constraint associations...\r\r
+Checking Constraint Associations...\r\r
+WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
+   "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
+   * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
+   clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
+   found.\r\r
+\r\r
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
+   'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
+   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
+   The following new TNM groups and period specifications were generated at the\r\r
+   PLL_ADV output(s): \r\r
+   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
+   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
+   1.25 PHASE 2 ns HIGH 50%>\r\r
+\r\r
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
+   'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
+   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
+   The following new TNM groups and period specifications were generated at the\r\r
+   PLL_ADV output(s): \r\r
+   CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
+   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
+   1.25 HIGH 50%>\r\r
+\r\r
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
+   'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
+   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
+   The following new TNM groups and period specifications were generated at the\r\r
+   PLL_ADV output(s): \r\r
+   CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
+   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
+   1.25 HIGH 50%>\r\r
+\r\r
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
+   'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
+   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
+   The following new TNM groups and period specifications were generated at the\r\r
+   PLL_ADV output(s): \r\r
+   CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
+   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
+   2 HIGH 50%>\r\r
+\r\r
+INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
+   'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
+   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
+   The following new TNM groups and period specifications were generated at the\r\r
+   PLL_ADV output(s): \r\r
+   CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
+   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
+   0.625 HIGH 50%>\r\r
+\r\r
+Done...\r\r
+Checking Partitions ...\r\r
+\r\r
+Processing BMM file ...\r\r
+\r\r
+WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
+   (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
+   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
+    This does not match the PERIOD constraint value (5 ns.).  The uncertainty\r\r
+   calculation will use the non-default attribute value.  This could result in\r\r
+   incorrect uncertainty calculated for DCM output clocks.\r\r
+Checking expanded design ...\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
+   ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
+   ALIGN_PIPE' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
+   RE_I' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
+   E_I' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
+   ' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
+   ' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
+   ' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
+   ' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
+   ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
+   ' has unconnected output pin\r\r
+WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
+   "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
+   v_i" of type "PLL_ADV".  This attribute will be ignored.\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
+   _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
+   _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
+   _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
+   _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
+   E0to3' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
+   E0to3' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
+   E0to3' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
+   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
+   E0to3' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
+   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
+   _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
+   E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
+   SIZE2_REG0' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
+   SIZE2_REG1' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
+   SIZE2_REG2' has unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
+   unconnected output pin\r\r
+WARNING:NgdBuild:443 - SFF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
+   output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
+   has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:440 - FF primitive\r\r
+   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
+   /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
+WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
+   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
+   of type "PLL_ADV".  This attribute will be ignored.\r\r
+WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
+   has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
+   has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
+   has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
+   has no driver\r\r
+WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
+   has no driver\r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+NGDBUILD Design Results Summary:\r\r
+  Number of errors:     0\r\r
+  Number of warnings: 348\r\r
+\r\r
+Writing NGD file "system.ngd" ...\r\r
+Total REAL time to NGDBUILD completion: 1 min  58 sec\r\r
+Total CPU time to NGDBUILD completion:  1 min  28 sec\r\r
+\r\r
+Writing NGDBUILD log file "system.bld"...\r\r
+\r\r
+NGDBUILD done.\r\r
+\r\r
+\r\r
+\r\r
+#----------------------------------------------#\r\r
+# Starting program map\r\r
+# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
+system.ngd system.pcf \r\r
+#----------------------------------------------#\r\r
+Release 11.2 - Map L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
+Using target part "5vfx70tff1136-1".\r\r
+WARNING:LIT:243 - Logical network N194 has no load.\r\r
+WARNING:LIT:395 - The above warning message is repeated 1200 more times for the\r\r
+   following (max. 5 shown):\r\r
+   N195,\r\r
+   N196,\r\r
+   N197,\r\r
+   N198,\r\r
+   N199\r\r
+   To see the details of these warning messages, please use the -detail switch.\r\r
+Mapping design into LUTs...\r\r
+WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
+   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
+   been removed.\r\r
+WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
+   level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
+WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
+   optimized out of the design.\r\r
+Writing file system_map.ngm...\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
+   of frag REGCLKAU connected to power/ground net\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
+   of frag REGCLKAL connected to power/ground net\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
+   of frag REGCLKAU connected to power/ground net\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
+   of frag REGCLKAL connected to power/ground net\r\r
+   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
+   of frag REGCLKAU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
+   of frag REGCLKAL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
+   of frag REGCLKAU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
+   of frag REGCLKAL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
+   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
+   x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
+   of frag RDRCLKU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
+   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
+   x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
+   of frag RDRCLKL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
+   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
+   /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
+   noeccerr.SDP\r\r
+   of frag RDRCLKU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
+   /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
+   noeccerr.SDP_RDRCLKU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
+   /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
+   noeccerr.SDP\r\r
+   of frag RDRCLKL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
+   /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
+   noeccerr.SDP_RDRCLKL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
+   em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
+   ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
+   of frag RDRCLKU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
+   em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
+   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
+   em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
+   ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
+   of frag RDRCLKL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
+   em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
+   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
+   P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
+   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
+   of frag RDRCLKU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
+   P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
+   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
+   P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
+   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
+   of frag RDRCLKL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
+   P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
+   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
+   /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
+   36.noeccerr.SDP\r\r
+   of frag RDRCLKU connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
+   /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
+   36.noeccerr.SDP_RDRCLKU_tiesig\r\r
+WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
+   /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
+   36.noeccerr.SDP\r\r
+   of frag RDRCLKL connected to power/ground net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
+   /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
+   36.noeccerr.SDP_RDRCLKL_tiesig\r\r
+Running directed packing...\r\r
+Running delay-based LUT packing...\r\r
+Updating timing models...\r\r
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
+   TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
+   timing analysis.\r\r
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
+   (.mrp).\r\r
+Running timing-driven placement...\r\r
+Total REAL time at the beginning of Placer: 1 mins 55 secs \r\r
+Total CPU  time at the beginning of Placer: 1 mins 43 secs \r\r
+\r\r
+Phase 1.1  Initial Placement Analysis\r\r
+Phase 1.1  Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs \r\r
+\r\r
+Phase 2.7  Design Feasibility Check\r\r
+WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
+   Components associated with this bus are as follows: \r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7>   IOSTANDARD = LVCMOS25\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5>   IOSTANDARD = LVCMOS25\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3>   IOSTANDARD = LVCMOS25\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1>   IOSTANDARD = LVCMOS18\r\r
+        Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18\r\r
+\r\r
+\r\r
+WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
+   Components associated with this bus are as follows: \r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<31>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<29>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<27>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<25>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<23>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<21>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<19>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<17>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<15>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<13>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<11>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<9>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<7>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<5>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<3>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<1>   IOSTANDARD = LVCMOS33\r\r
+        Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33\r\r
+\r\r
+\r\r
+Phase 2.7  Design Feasibility Check (Checksum:150b88e2) REAL time: 2 mins 14 secs \r\r
+\r\r
+Phase 3.31  Local Placement Optimization\r\r
+Phase 3.31  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
+\r\r
+Phase 4.37  Local Placement Optimization\r\r
+Phase 4.37  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
+\r\r
+Phase 5.33  Local Placement Optimization\r\r
+Phase 5.33  Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs \r\r
+\r\r
+Phase 6.32  Local Placement Optimization\r\r
+Phase 6.32  Local Placement Optimization (Checksum:f23945c2) REAL time: 9 mins 1 secs \r\r
+\r\r
+Phase 7.2  Initial Clock and IO Placement\r\r
+\r\r
+\r\r
+\r\r
+There are 16 clock regions on the target FPGA device:\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y7:                        | CLOCKREGION_X1Y7:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   4 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   0 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   2 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   2 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   2 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   2 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use\r
+      |\r\r
+|   4 edge BUFIOs available, 2 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   0 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+| CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |\r\r
+|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
+|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
+|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
+|   4 center BUFIOs available, 0 in use    |                                          |\r\r
+|                                          |                                          |\r\r
+|------------------------------------------|------------------------------------------|\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y1>\r\r
+  key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
+|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
+|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| clock |    region   |                                                                                      -----------------------------------------------\r\r
+|  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y2>\r\r
+  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
+|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
+|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
+|-------|-------------|------|-----|----|--------|-------\r
+-|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| clock |    region   |                                                                                      -----------------------------------------------\r\r
+|  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y6>\r\r
+  key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
+|-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
+|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
+|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+|       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| clock |    region   |                                                                                      -----------------------------------------------\r\r
+|  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 | \r
+    0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
+|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
+\r\r
+\r\r
+\r\r
+\r\r
+######################################################################################\r\r
+# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
+#\r\r
+# Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)\r\r
+# Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
+# composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
+# \r\r
+######################################################################################\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y27" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
+CLOCKREGION_X0Y6;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y9" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
+CLOCKREGION_X0Y2;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y11" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
+CLOCKREGION_X0Y2;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y4" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
+CLOCKREGION_X0Y1;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y25" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
+CLOCKREGION_X0Y6;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y7" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
+CLOCKREGION_X0Y1;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y26" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
+CLOCKREGION_X0Y6;\r\r
+\r\r
+\r\r
+# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
+INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
+"BUFIO_X0Y10" ;\r\r
+NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
+"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
+TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
+"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
+AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
+CLOCKREGION_X0Y2;\r\r
+\r\r
+\r\r
+Phase 7.2  Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
+\r\r
+Phase 8.36  Local Placement Optimization\r\r
+Phase 8.36  Local Placement Optimization (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
+\r\r
+....................\r
+.................\r\r
+.....\r
+......\r
+.....\r
+......\r
+.....\r
+.....\r
+......\r
+......\r
+.......\r
+......\r
+.......\r
+.......\r
+.......\r
+..\r\r
+Phase 9.30  Global Clock Region Assignment\r\r
+\r\r
+\r\r
+######################################################################################\r\r
+# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
+#\r\r
+# Number of Global Clock Regions : 16\r\r
+# Number of Global Clock Networks: 15\r\r
+#\r\r
+# Clock Region Assignment: SUCCESSFUL\r\r
+\r\r
+# Location of Clock Components\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
+INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
+INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
+INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
+INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
+INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
+INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
+INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
+INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
+INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
+INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
+INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
+INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
+INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
+INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
+INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
+INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
+INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
+\r\r
+# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
+NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
+TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
+AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
+NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
+TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
+AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
+\r\r
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
+NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
+TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
+AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
+NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
+TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
+AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;\r\r
+\r\r
+# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
+NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
+TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
+AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
+NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
+TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
+AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
+\r\r
+# clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
+NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
+TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
+AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
+NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
+TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
+AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
+NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
+TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
+AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
+\r\r
+# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
+NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
+TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
+AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
+NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
+TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
+AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
+\r\r
+# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
+NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
+TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
+AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
+\r\r
+# NOTE: \r\r
+# This report is provided to help reproduce successful clock-region \r\r
+# assignments. The report provides range constraints for all global \r\r
+# clock networks, in a format that is directly usable in ucf files. \r\r
+#\r\r
+#END of Global Clock Net Distribution UCF Constraints\r\r
+######################################################################################\r\r
+\r\r
+\r\r
+######################################################################################\r\r
+GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
+\r\r
+Number of Global Clock Regions : 16\r\r
+Number of Global Clock Networks: 15\r\r
+\r\r
+Clock Region Assignment: SUCCESSFUL\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y0> \r\r
+ key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     44 |    548 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    202 |clk_125_0000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    750 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y0> \r\r
+ key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     38 |    934 |PCIe_Bridge/Bridge_Clk\r\r
+      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |     62 |    986 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y1> \r\r
+ key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     13 |    195 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      0 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    719 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |clk_62_5000MHzPLL0_ADJUST\r\r
+      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     17 |    918 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y1> \r\r
+ key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    500 |PCIe_Bridge/Bridge_Clk\r\r
+      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |    364 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |    884 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y2> \r\r
+ key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      5 |      0 |      0 |      0 |      9 |     15 |      0 |      0 |      0 |      0 |      0 |      0 |     58 |    913 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    142 |clk_62_5000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      7 |      0 |      0 |      0 |      9 |     42 |      0 |      0 |      0 |      0 |      1 |      0 |     58 |   1072 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y2> \r\r
+ key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     94 |    387 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
+      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |    500 |clk_125_0000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    130 |    970 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y3> \r\r
+ key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     36 |    272 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    154 |clk_62_5000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     36 |    512 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y3> \r\r
+ key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     44 |    290 |PCIe_Bridge/Bridge_Clk\r\r
+      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    659 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      9 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     66 |    950 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y4> \r\r
+ key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      1 |PCIe_Bridge/Bridge_Clk\r\r
+      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    231 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    200 |clk_62_5000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     18 |    466 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y4> \r\r
+ key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     54 |    367 |PCIe_Bridge/Bridge_Clk\r\r
+      3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |    602 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      3 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     74 |    985 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y5> \r\r
+ key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |      2 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    517 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    206 |clk_62_5000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    773 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y5> \r\r
+ key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     68 |    285 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     50 |    333 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    118 |    639 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y6> \r\r
+ key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
+      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
+      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    605 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    158 |clk_62_5000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |     12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     27 |    777 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y6> \r\r
+ key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    103 |PCIe_Bridge/Bridge_Clk\r\r
+      0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    413 |clk_125_0000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     26 |    516 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X0Y7> \r\r
+ key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    495 |clk_125_0000MHzPLL0_ADJUST\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     19 |clk_62_5000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    514 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+\r\r
+Clock-Region: <CLOCKREGION_X1Y7> \r\r
+ key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
+   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+        |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 |clk_125_0000MHzPLL0_ADJUST\r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 | Total \r\r
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
+\r\r
+NOTE:\r\r
+The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
+may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
+maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
+\r\r
+\r\r
+# END of Global Clock Net Loads Distribution Report:\r\r
+######################################################################################\r\r
+\r\r
+\r\r
+Phase 9.30  Global Clock Region Assignment (Checksum:7e049af9) REAL time: 10 mins 42 secs \r\r
+\r\r
+Phase 10.3  Local Placement Optimization\r\r
+Phase 10.3  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs \r\r
+\r\r
+Phase 11.5  Local Placement Optimization\r\r
+Phase 11.5  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 45 secs \r\r
+\r\r
+Phase 12.8  Global Placement\r\r
+.............................\r
+....\r\r
+.\r
+.......\r
+.....\r
+.......\r
+.......\r
+.......\r
+......\r
+........\r
+........\r
+........\r
+.........\r
+.........\r
+.........\r\r
+.\r
+.......\r
+......\r
+........\r
+.......\r
+.........\r
+........\r
+.........\r
+.......\r\r
+.\r
+.......\r
+.....\r
+.......\r
+.\r
+....\r
+...\r
+...\r
+......\r
+......\r
+......\r
+....\r
+.......\r
+......\r
+....\r
+.\r
+......\r
+......\r
+......\r\r
+....\r
+......\r
+.\r
+....\r
+...\r
+....\r
+.......\r
+......\r
+....\r
+...\r
+.......\r
+.........\r\r
+..\r
+.\r
+.....\r
+..\r
+...\r
+.......\r
+......\r
+.....\r
+......\r
+.....\r
+......\r
+......\r
+......\r
+.....\r\r
+.\r
+.....\r
+..\r
+.....\r
+...\r\r
+..\r
+......\r
+.......\r
+.......\r
+........\r
+...\r\r
+Phase 12.8  Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
+\r\r
+Phase 13.29  Local Placement Optimization\r\r
+Phase 13.29  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
+\r\r
+Phase 14.5  Local Placement Optimization\r\r
+Phase 14.5  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs \r\r
+\r\r
+Phase 15.18  Placement Optimization\r\r
+Phase 15.18  Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 1 secs \r\r
+\r\r
+Phase 16.5  Local Placement Optimization\r\r
+Phase 16.5  Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs \r\r
+\r\r
+Phase 17.34  Placement Validation\r\r
+Phase 17.34  Placement Validation (Checksum:f81b02a1) REAL time: 18 mins 5 secs \r\r
+\r\r
+Total REAL time to Placer completion: 18 mins 7 secs \r\r
+Total CPU  time to Placer completion: 17 mins 4 secs \r\r
+Running post-placement packing...\r\r
+Writing output files...\r\r
+\r\r
+Design Summary:\r\r
+Number of errors:      0\r\r
+Number of warnings:   50\r\r
+Slice Logic Utilization:\r\r
+  Number of Slice Registers:                12,128 out of  44,800   27%\r\r
+    Number used as Flip Flops:              12,127\r\r
+    Number used as Latches:                      1\r\r
+  Number of Slice LUTs:                     12,266 out of  44,800   27%\r\r
+    Number used as logic:                   11,767 out of  44,800   26%\r\r
+      Number using O6 output only:          10,791\r\r
+      Number using O5 output only:             282\r\r
+      Number using O5 and O6:                  694\r\r
+    Number used as Memory:                     392 out of  13,120    2%\r\r
+      Number used as Dual Port RAM:             56\r\r
+        Number using O6 output only:            12\r\r
+        Number using O5 and O6:                 44\r\r
+      Number used as Single Port RAM:            4\r\r
+        Number using O6 output only:             4\r\r
+      Number used as Shift Register:           332\r\r
+        Number using O6 output only:           332\r\r
+    Number used as exclusive route-thru:       107\r\r
+  Number of route-thrus:                       438\r\r
+    Number using O6 output only:               382\r\r
+    Number using O5 output only:                51\r\r
+    Number using O5 and O6:                      5\r\r
+\r\r
+Slice Logic Distribution:\r\r
+  Number of occupied Slices:                 6,488 out of  11,200   57%\r\r
+  Number of LUT Flip Flop pairs used:       17,046\r\r
+    Number with an unused Flip Flop:         4,918 out of  17,046   28%\r\r
+    Number with an unused LUT:               4,780 out of  17,046   28%\r\r
+    Number of fully used LUT-FF pairs:       7,348 out of  17,046   43%\r\r
+    Number of unique control sets:           1,288\r\r
+    Number of slice register sites lost\r\r
+      to control set restrictions:           3,000 out of  44,800    6%\r\r
+\r\r
+  A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
+  one Flip Flop within a slice.  A control set is a unique combination of\r\r
+  clock, reset, set, and enable signals for a registered element.\r\r
+  The Slice Logic Distribution report is not meaningful if the design is\r\r
+  over-mapped for a non-slice resource or if Placement fails.\r\r
+  OVERMAPPING of BRAM resources should be ignored if the design is\r\r
+  over-mapped for a non-BRAM resource or if placement fails.\r\r
+\r\r
+IO Utilization:\r\r
+  Number of bonded IOBs:                       255 out of     640   39%\r\r
+    Number of LOCed IOBs:                      255 out of     255  100%\r\r
+    IOB Flip Flops:                            494\r\r
+    Number of bonded IPADs:                      4 out of      50    8%\r\r
+    Number of bonded OPADs:                      2 out of      32    6%\r\r
+\r\r
+Specific Feature Utilization:\r\r
+  Number of BlockRAM/FIFO:                      23 out of     148   15%\r\r
+    Number using BlockRAM only:                 21\r\r
+    Number using FIFO only:                      2\r\r
+    Total primitives used:\r\r
+      Number of 36k BlockRAM used:              16\r\r
+      Number of 18k BlockRAM used:               6\r\r
+      Number of 36k FIFO used:                   2\r\r
+    Total Memory used (KB):                    756 out of   5,328   14%\r\r
+  Number of BUFG/BUFGCTRLs:                     15 out of      32   46%\r\r
+    Number used as BUFGs:                       15\r\r
+  Number of IDELAYCTRLs:                         3 out of      22   13%\r\r
+  Number of BUFDSs:                              1 out of       8   12%\r\r
+  Number of BUFIOs:                              8 out of      80   10%\r\r
+  Number of DCM_ADVs:                            1 out of      12    8%\r\r
+  Number of GTX_DUALs:                           1 out of       8   12%\r\r
+  Number of PCIEs:                               1 out of       3   33%\r\r
+    Number of LOCed PCIEs:                       1 out of       1  100%\r\r
+  Number of PLL_ADVs:                            2 out of       6   33%\r\r
+  Number of PPC440s:                             1 out of       1  100%\r\r
+\r\r
+  Number of RPM macros:           64\r\r
+Average Fanout of Non-Clock Nets:                3.76\r\r
+\r\r
+Peak Memory Usage:  701 MB\r\r
+Total REAL time to MAP completion:  18 mins 45 secs \r\r
+Total CPU time to MAP completion:   17 mins 40 secs \r\r
+\r\r
+Mapping completed.\r\r
+See MAP report file "system_map.mrp" for details.\r\r
+\r\r
+\r\r
+\r\r
+#----------------------------------------------#\r\r
+# Starting program par\r\r
+# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
+system.pcf \r\r
+#----------------------------------------------#\r\r
+Release 11.2 - par L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
+\r\r
+\r\r
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
+   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
+\r\r
+Constraints file: system.pcf.\r\r
+   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
+WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]\r\r
+   overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
+\r\r
+\r\r
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
+Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
+\r\r
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP       \r\r
+   "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
+INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please\r\r
+   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
+\r\r
+Device speed data version:  "PRODUCTION 1.65 2009-06-01".\r\r
+\r\r
+\r\r
+\r\r
+Device Utilization Summary:\r\r
+\r\r
+   Number of BUFDSs                          1 out of 8      12%\r\r
+   Number of BUFGs                          15 out of 32     46%\r\r
+   Number of BUFIOs                          8 out of 80     10%\r\r
+   Number of DCM_ADVs                        1 out of 12      8%\r\r
+   Number of FIFO36_72_EXPs                  2 out of 148     1%\r\r
+      Number of LOCed FIFO36_72_EXPs         2 out of 2     100%\r\r
+\r\r
+   Number of GTX_DUALs                       1 out of 8      12%\r\r
+   Number of IDELAYCTRLs                     3 out of 22     13%\r\r
+      Number of LOCed IDELAYCTRLs            3 out of 3     100%\r\r
+\r\r
+   Number of ILOGICs                       131 out of 800    16%\r\r
+      Number of LOCed ILOGICs                8 out of 131     6%\r\r
+\r\r
+   Number of External IOBs                 255 out of 640    39%\r\r
+      Number of LOCed IOBs                 255 out of 255   100%\r\r
+\r\r
+   Number of IODELAYs                       80 out of 800    10%\r\r
+      Number of LOCed IODELAYs               8 out of 80     10%\r\r
+\r\r
+   Number of External IPADs                  4 out of 690     1%\r\r
+      Number of LOCed IPADs                  4 out of 4     100%\r\r
+\r\r
+   Number of JTAGPPCs                        1 out of 1     100%\r\r
+   Number of OLOGICs                       236 out of 800    29%\r\r
+   Number of External OPADs                  2 out of 32      6%\r\r
+      Number of LOCed OPADs                  2 out of 2     100%\r\r
+\r\r
+   Number of PCIEs                           1 out of 3      33%\r\r
+      Number of LOCed PCIEs                  1 out of 1     100%\r\r
+\r\r
+   Number of PLL_ADVs                        2 out of 6      33%\r\r
+   Number of PPC440s                         1 out of 1     100%\r\r
+   Number of RAMB18X2SDPs                    5 out of 148     3%\r\r
+   Number of RAMB36SDP_EXPs                  6 out of 148     4%\r\r
+      Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%\r\r
+\r\r
+   Number of RAMB36_EXPs                    10 out of 148     6%\r\r
+      Number of LOCed RAMB36_EXPs            6 out of 10     60%\r\r
+\r\r
+   Number of Slice Registers             12128 out of 44800  27%\r\r
+      Number used as Flip Flops          12127\r\r
+      Number used as Latches                 1\r\r
+      Number used as LatchThrus              0\r\r
+\r\r
+   Number of Slice LUTS                  12266 out of 44800  27%\r\r
+   Number of Slice LUT-Flip Flop pairs   17046 out of 44800  38%\r\r
+\r\r
+\r\r
+Overall effort level (-ol):   High \r\r
+Router effort level (-rl):    High \r\r
+\r\r
+Starting initial Timing Analysis.  REAL time: 51 secs \r\r
+Finished initial Timing Analysis.  REAL time: 52 secs \r\r
+\r\r
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this\r\r
+   signal.\r\r
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this\r\r
+   signal.\r\r
+WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this\r\r
+   signal.\r\r
+WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this\r\r
+   signal.\r\r
+WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this\r\r
+   signal.\r\r
+Starting Router\r\r
+\r\r
+INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
+   that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
+   verify that the same connectivity is available in the target device for this implementation. \r\r
+\r\r
+Phase  1  : 82160 unrouted;      REAL time: 1 mins 9 secs \r\r
+\r\r
+Phase  2  : 72970 unrouted;      REAL time: 1 mins 22 secs \r\r
+\r\r
+Phase  3  : 28783 unrouted;      REAL time: 3 mins 31 secs \r\r
+\r\r
+Phase  4  : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0)     REAL time: 3 mins 57 secs \r\r
+\r\r
+Updating file: system.ncd with current fully routed design.\r\r
+\r\r
+Phase  5  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
+\r\r
+Phase  6  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
+\r\r
+Phase  7  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
+\r\r
+Phase  8  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
+\r\r
+Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 25 secs \r\r
+\r\r
+Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 57 secs \r\r
+Total REAL time to Router completion: 7 mins 57 secs \r\r
+Total CPU time to Router completion: 7 mins 31 secs \r\r
+\r\r
+Partition Implementation Status\r\r
+-------------------------------\r\r
+\r\r
+  No Partitions were found in this design.\r\r
+\r\r
+-------------------------------\r\r
+\r\r
+Generating "PAR" statistics.\r\r
+\r\r
+**************************\r\r
+Generating Clock Report\r\r
+**************************\r\r
+\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|clk_125_0000MHzPLL0_ |              |      |      |            |             |\r\r
+|              ADJUST | BUFGCTRL_X0Y2| No   | 3176 |  0.533     |  2.076      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|PCIe_Bridge/Bridge_C |              |      |      |            |             |\r\r
+|                  lk |BUFGCTRL_X0Y28| No   | 1481 |  0.519     |  2.085      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|clk_62_5000MHzPLL0_A |              |      |      |            |             |\r\r
+|               DJUST | BUFGCTRL_X0Y6| No   |  501 |  0.313     |  2.062      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|clk_125_0000MHz90PLL |              |      |      |            |             |\r\r
+|            0_ADJUST | BUFGCTRL_X0Y5| No   |  165 |  0.262     |  2.028      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
+|dge/comp_block_plus/ |              |      |      |            |             |\r\r
+|comp_endpoint/core_c |              |      |      |            |             |\r\r
+|                  lk |BUFGCTRL_X0Y27| No   |   92 |  0.338     |  2.085      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|fpga_0_SysACE_Compac |              |      |      |            |             |\r\r
+|tFlash_SysACE_CLK_pi |              |      |      |            |             |\r\r
+|             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.171     |  1.797      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
+|dge/comp_block_plus/ |              |      |      |            |             |\r\r
+|comp_endpoint/pcie_b |              |      |      |            |             |\r\r
+|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.065     |  1.886      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
+|PHY_rx_clk_pin_BUFGP |              |      |      |            |             |\r\r
+|                     |BUFGCTRL_X0Y30| No   |   12 |  0.086     |  1.874      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
+|PHY_tx_clk_pin_BUFGP |              |      |      |            |             |\r\r
+|                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<0> |        IO Clk| No   |   18 |  0.095     |  0.419      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |\r
+      |            |             |\r\r
+| y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<4> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
+|M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
+|f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
+| y_io/delayed_dqs<7> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No   |    2 |  0.000     |  1.739      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.100     |  1.879      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|RS232_Uart_1_Interru |              |      |      |            |             |\r\r
+|                  pt |         Local|      |    1 |  0.000     |  0.625      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
+|dge/comp_block_plus/ |              |      |      |            |             |\r\r
+|comp_endpoint/pcie_b |              |      |      |            |             |\r\r
+|lk/SIO/.pcie_gt_wrap |              |      |      |            |             |\r\r
+|  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.590      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|Ethernet_MAC/Etherne |              |      |      |            |             |\r\r
+|  t_MAC/phy_tx_clk_i |         Local|      |    9 |  3.273     |  3.994      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+|ppc440_0_jtagppc_bus |              |      |      |            |             |\r\r
+|         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.699      |\r\r
++---------------------+--------------+------+------+------------+-------------+\r\r
+\r\r
+* Net Skew is the difference between the minimum and maximum routing\r\r
+only delays for the net. Note this is different from Clock Skew which\r\r
+is reported in TRCE timing report. Clock Skew is the difference between\r\r
+the minimum and maximum path delays which includes logic delays.\r\r
+\r\r
+Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
+\r\r
+Number of Timing Constraints that were not applied: 5\r\r
+\r\r
+Asterisk (*) preceding a constraint indicates it was not met.\r\r
+   This may be due to a setup or hold violation.\r\r
+\r\r
+----------------------------------------------------------------------------------------------------------\r\r
+  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   \r\r
+                                            |             |    Slack   | Achievable | Errors |    Score   \r\r
+----------------------------------------------------------------------------------------------------------\r\r
+  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.026ns|     7.974ns|       0|           0\r\r
+  s HIGH 50%                                | HOLD        |     0.030ns|            |       0|           0\r\r
+                                            | MINPERIOD   |     0.000ns|     8.000ns|       0|           0\r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.026ns|     3.974ns|       0|           0\r\r
+  lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.315ns|            |       0|           0\r\r
+      4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0\r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.012ns|     0.838ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.015ns|     0.835ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP       |     0.021ns|     1.879ns|       0|           0\r\r
+  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0\r\r
+     1.9 ns                                 |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     0.027ns|     7.973ns|       0|           0\r\r
+  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0\r\r
+  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
+  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
+  HIGH 50%                                  |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
+  dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
+  DELAY = 0.85 ns                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.068ns|     0.532ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
+  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
+  qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.188ns|     7.812ns|       0|           0\r\r
+  ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.516ns|            |       0|           0\r\r
+    DATAPATHONLY                            |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0\r\r
+  HIGH 50%                                  |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     1.252ns|     6.748ns|       0|           0\r\r
+  _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.451ns|            |       0|           0\r\r
+    DATAPATHONLY                            |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.700ns|     4.300ns|       0|           0\r\r
+  RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0\r\r
+  thernet_MAC" 6 ns                         |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.073ns|     5.466ns|       0|           0\r\r
+  L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.307ns|            |       0|           0\r\r
+  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
+  LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
+  PHASE 2 ns HIGH 50%                       |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0\r\r
+  pin" 100 MHz HIGH 50%                     |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.700ns|     8.600ns|       0|           0\r\r
+  L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.153ns|            |       0|           0\r\r
+  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
+  LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |            \r\r
+   HIGH 50%                                 |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.950ns|     1.050ns|       0|           0\r\r
+  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0\r\r
+  lock_generator_0_clock_generator_0_PLL0_C | MINLOWPULSE |     3.946ns|     1.054ns|       0|           0\r\r
+  LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |            \r\r
+  H 50%                                     |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.392ns|     0.608ns|       0|           0\r\r
+  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.789ns|     0.211ns|       0|           0\r\r
+  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0\r\r
+  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |            \r\r
+  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
+  LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
+  HIGH 50%                                  |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0\r\r
+  GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |            \r\r
+  IMEGRP "PADS" 10 ns                       |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |    10.092ns|    11.165ns|       0|           0\r\r
+  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.473ns|            |       0|           0\r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    13.832ns|     6.168ns|       0|           0\r\r
+  M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.471ns|            |       0|           0\r\r
+      TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    16.202ns|     3.798ns|       0|           0\r\r
+   TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.049ns|            |       0|           0\r\r
+     TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.943ns|     2.057ns|       0|           0\r\r
+  NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.295ns|            |       0|           0\r\r
+    TS_MC_CLK * 4                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.975ns|     2.025ns|       0|           0\r\r
+  NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.030ns|            |       0|           0\r\r
+    TS_MC_CLK * 4                           |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.085ns|     1.915ns|       0|           0\r\r
+  P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.096ns|            |       0|           0\r\r
+  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.710ns|     3.290ns|       0|           0\r\r
+  K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.465ns|            |       0|           0\r\r
+   HIGH 50%                                 |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.431ns|     7.569ns|       0|           0\r\r
+  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.351ns|            |       0|           0\r\r
+------------------------------------------------------------------------------------------------------\r\r
+  Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0\r\r
+------------------------------------------------------------------------------------------------------\r\r
+  TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
+  P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |            \r\r
+  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
+  s HIGH 50%                                |             |            |            |        |            \r\r
+------------------------------------------------------------------------------------------------------\r\r
+\r\r
+\r\r
+Derived Constraint Report\r\r
+Derived Constraints for TS_MC_CLK\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+|TS_MC_CLK                      |      5.000ns|      3.990ns|      1.542ns|            0|            0|            0|          345|\r\r
+| TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      3.798ns|          N/A|            0|            0|           21|            0|\r\r
+| TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      6.168ns|          N/A|            0|            0|          274|            0|\r\r
+| TS_MC_GATE_DLY                |     20.000ns|      2.025ns|          N/A|            0|            0|           40|            0|\r\r
+| TS_MC_RDEN_DLY                |     20.000ns|      2.057ns|          N/A|            0|            0|            5|            0|\r\r
+| TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.915ns|          N/A|            0|            0|            5|            0|\r\r
+| TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+\r\r
+Derived Constraints for TS_sys_clk_pin\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+|TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.966ns|            0|            0|            0|       636358|\r\r
+| TS_clock_generator_0_clock_gen|      8.000ns|      5.466ns|          N/A|            0|            0|          626|            0|\r\r
+| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |\r\r
+| TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|\r\r
+| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |\r\r
+| TS_clock_generator_0_clock_gen|      8.000ns|      7.973ns|          N/A|            0|            0|       624688|            0|\r\r
+| erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |\r\r
+| TS_clock_generator_0_clock_gen|      5.000ns|      1.054ns|          N/A|            0|            0|            2|            0|\r\r
+| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |\r\r
+| TS_clock_generator_0_clock_gen|     16.000ns|      8.600ns|          N/A|            0|            0|        11042|            0|\r\r
+| erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |\r\r
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
+\r\r
+All constraints were met.\r\r
+INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
+   constraint does not cover any paths or that it has no requested value.\r\r
+\r\r
+\r\r
+Generating Pad Report.\r\r
+\r\r
+All signals are completely routed.\r\r
+\r\r
+WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
+\r\r
+Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
+INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
+INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
+   found: 128, number successful: 128\r\r
+Total REAL time to PAR completion: 9 mins 1 secs \r\r
+Total CPU time to PAR completion: 8 mins 19 secs \r\r
+\r\r
+Peak Memory Usage:  653 MB\r\r
+\r\r
+Placer: Placement generated during map.\r\r
+Routing: Completed - No errors found.\r\r
+Timing: Completed - No errors found.\r\r
+\r\r
+Number of error messages: 0\r\r
+Number of warning messages: 9\r\r
+Number of info messages: 4\r\r
+\r\r
+Writing design to file system.ncd\r\r
+\r\r
+\r\r
+\r\r
+PAR done!\r\r
+\r\r
+\r\r
+\r\r
+#----------------------------------------------#\r\r
+# Starting program post_par_trce\r\r
+# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
+#----------------------------------------------#\r\r
+Release 11.2 - Trace  (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+\r\r
+\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
+   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
+WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
+   8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET\r\r
+   "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
+\r\r
+WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
+   TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;\r\r
+   ignored during timing analysis.\r\r
+INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more\r\r
+   information, see the TSI report.  Please consult the Xilinx Command Line\r\r
+   Tools User Guide for information on generating a TSI report.\r\r
+--------------------------------------------------------------------------------\r\r
+Release 11.2 Trace  (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+\r\r
+trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
+\r\r
+\r\r
+Design file:              system.ncd\r\r
+Physical constraint file: system.pcf\r\r
+Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
+level 0)\r\r
+Report level:             error report\r\r
+--------------------------------------------------------------------------------\r\r
+\r\r
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
+   option. All paths that are not constrained will be reported in the\r\r
+   unconstrained paths section(s) of the report.\r\r
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
+   50 Ohm transmission line loading model.  For the details of this model, and\r\r
+   for more information on accounting for different loading conditions, please\r\r
+   see the device datasheet.\r\r
+\r\r
+\r\r
+Timing summary:\r\r
+---------------\r\r
+\r\r
+Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)\r\r
+\r\r
+Constraints cover 826342 paths, 18 nets, and 74598 connections\r\r
+\r\r
+Design statistics:\r\r
+   Minimum period:  11.165ns (Maximum frequency:  89.566MHz)\r\r
+   Maximum path delay from/to any node:   7.812ns\r\r
+   Maximum net delay:   0.838ns\r\r
+   Maximum net skew:   0.608ns\r\r
+\r\r
+\r\r
+Analysis completed Tue Jun 30 21:57:31 2009\r\r
+--------------------------------------------------------------------------------\r\r
+\r\r
+Generating Report ...\r\r
+\r\r
+Number of warnings: 2\r\r
+Number of info messages: 3\r\r
+Total time: 1 mins 36 secs \r\r
+\r\r
+\r\r
+xflow done!\r\r
+touch __xps/system_routed\r
+xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
+Analyzing implementation/system.par\r\r
+*********************************************\r
+Running Bitgen..\r
+*********************************************\r
+cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
+Release 11.2 - Bitgen L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+PMSPEC -- Overriding Xilinx file\r\r
+<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
+<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
+Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
+c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
+   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
+Opened constraints file system.pcf.\r\r
+\r\r
+Tue Jun 30 21:58:01 2009\r\r
+\r\r
+Running DRC.\r\r
+WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
+   Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
+   Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
+   guidelines to minimize the impact on GTX performance. \r\r
+WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
+   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
+   rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
+   design practice. Use the CE pin to control the loading of data into the\r\r
+   flip-flop.\r\r
+WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
+   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
+   This is not good design practice. Use the CE pin to control the loading of\r\r
+   data into the flip-flop.\r\r
+WARNING:PhysDesignRules:367 - The signal\r\r
+   <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
+   not drive any load pins in the design.\r\r
+WARNING:PhysDesignRules:367 - The signal\r\r
+   <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
+   drive any load pins in the design.\r\r
+WARNING:PhysDesignRules:367 - The signal\r\r
+   <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
+   drive any load pins in the design.\r\r
+WARNING:PhysDesignRules:367 - The signal\r\r
+   <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
+   drive any load pins in the design.\r\r
+WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
+   is incomplete. The signal does not drive any load pins in the design.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
+   used.\r\r
+WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
+   block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
+   qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
+   Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
+DRC detected 0 errors and 24 warnings.  Please see the previously displayed\r\r
+individual error or warning messages for more details.\r\r
+Creating bit map...\r\r
+Saving bit stream in "system.bit".\r\r
+Bitstream generation is complete.\r\r
+\r
+\r
+Done!
+\r
+Writing filter settings....
+\r
+Done writing filter settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
+\r
+Done writing Tab View settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
+\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
+\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
+\r
+Generating Block Diagram to Buffer 
+\r
+Generated Block Diagram SVG
+\r
+At Local date and time: Sat Jul 04 20:43:06 2009
+ make -f system.make download started...
+\r
+cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
+*********************************************\r
+Initializing BRAM contents of the bitstream\r
+*********************************************\r
+bitinit -p xc5vfx70tff1136-1 system.mhs  -pe ppc440_0  bootloops/ppc440_0.elf  \\r
+-bt implementation/system.bit -o implementation/download.bit\r
+\r\r
+bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
+Copyright (c) Xilinx Inc. 2002.\r\r
+\r\r
+Parsing MHS File system.mhs...\r\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   251 - deprecated core for architecture 'virtex5fx'!\r\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
+   296 - deprecated core for architecture 'virtex5fx'!\r\r
+\r\r
+Overriding IP level properties ...\r\r
+\r\r
+Performing IP level DRCs on properties...\r\r
+\r\r
+Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
+Address Map for Processor ppc440_0\r\r
+  (0b0000000000-0b0011111111) ppc440_0 \r\r
+  (0000000000-0x0fffffff) DDR2_SDRAM   ppc440_0_PPC440MC\r\r
+  (0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0\r\r
+  (0x81400000-0x8140ffff) Push_Buttons_5Bit    plb_v46_0\r\r
+  (0x81420000-0x8142ffff) LEDs_Positions       plb_v46_0\r\r
+  (0x81440000-0x8144ffff) LEDs_8Bit    plb_v46_0\r\r
+  (0x81460000-0x8146ffff) DIP_Switches_8Bit    plb_v46_0\r\r
+  (0x81600000-0x8160ffff) IIC_EEPROM   plb_v46_0\r\r
+  (0x81800000-0x8180ffff) xps_intc_0   plb_v46_0\r\r
+  (0x83600000-0x8360ffff) SysACE_CompactFlash  plb_v46_0\r\r
+  (0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0\r\r
+  (0x85c00000-0x85c0ffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xc0000000-0xdfffffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xe0000000-0xefffffff) PCIe_Bridge  plb_v46_0\r\r
+  (0xf8000000-0xf80fffff) SRAM plb_v46_0\r\r
+  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1  plb_v46_0\r\r
+INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
+   01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
+   C_SPLB0_P2P value to 0\r\r
+\r\r
+Computing clock values...\r\r
+INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
+   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
+   performed for IPs connected to that clock port, unless they are connected\r\r
+   through the clock generator IP. \r\r
+\r\r
+INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
+   'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
+   performed for IPs connected to that clock port, unless they are connected\r\r
+   through the clock generator IP. \r\r
+\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_SLAVES value to 12\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_PLBV46_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
+   PARAMETER C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
+   PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
+   v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
+   PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
+   value to 0x2000\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PORT_DWIDTH value to 64\r\r
+INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
+   \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
+   value to 8\r\r
+INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
+   _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
+   ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
+   ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
+   a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
+   a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
+   C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
+   C_MPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
+   C_MPLB_SMALLEST_SLAVE value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
+   C_SPLB_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
+   C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
+   C_SPLB_SMALLEST_MASTER value to 128\r\r
+INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
+   b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
+   C_PLBV46_NUM_SLAVES value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_PLBV46_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
+   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
+   value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
+   2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
+   PARAMETER C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
+   C_SPLB_DWIDTH value to 128\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
+   C_SPLB_MID_WIDTH value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
+   \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
+   C_SPLB_NUM_MASTERS value to 1\r\r
+INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
+   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
+   ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
+   value to 128\r\r
+\r\r
+Checking platform address map ...\r\r
+\r\r
+Initializing Memory...\r\r
+Running Data2Mem with the following command:\r\r
+data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd\r\r
+"bootloops/ppc440_0.elf" tag ppc440_0  -o b implementation/download.bit \r\r
+Memory Initialization completed successfully.\r\r
+\r\r
+*********************************************\r
+Downloading Bitstream onto the target board\r
+*********************************************\r
+impact -batch etc/download.cmd\r
+Release 11.2 - iMPACT L.46 (nt)\r\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
+Preference Table\r\r
+Name                 Setting             \r\r
+StartupClock         Auto_Correction     \r\r
+AutoSignature        False               \r\r
+KeepSVF              False               \r\r
+ConcurrentMode       False               \r\r
+UseHighz             False               \r\r
+ConfigOnFailure      Stop                \r\r
+UserLevel            Novice              \r\r
+MessageLevel         Detailed            \r\r
+svfUseTime           false               \r\r
+SpiByteSwap          Auto_Correction     \r\r
+AutoDetecting cable. Please wait.\r\r
+Connecting to cable (Usb Port - USB21).\r\r
+Checking cable driver.\r\r
+ Driver file xusb_xp2.sys found.\r\r
+ Driver version: src=2301, dest=2301.\r\r
+ Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
+13:58:07, version = 900.\r\r
+ Cable PID = 0008.\r\r
+ Max current requested during enumeration is 300 mA.\r\r
+Type = 0x0005.\r\r
+ Cable Type = 3, Revision = 0.\r\r
+ Setting cable speed to 6 MHz.\r\r
+Cable connection established.\r\r
+Firmware version = 2401.\r\r
+File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
+Firmware hex file version = 2401.\r\r
+PLD file version = 200Dh.\r\r
+ PLD version = 200Dh.\r\r
+Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
+INFO:iMPACT:1777 - \r
+   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
+\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+'1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
+INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
+INFO:iMPACT:1777 - \r
+   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
+INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
+\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
+INFO:iMPACT:1777 - \r
+   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
+INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
+\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+done.\r\r
+Elapsed time =      0 sec.\r\r
+Elapsed time =      0 sec.\r\r
+'5': Loading file 'implementation/download.bit' ...\r\r
+INFO:iMPACT:1777 - \r
+   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
+INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
+INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
+\r
+done.\r\r
+UserID read from the bitstream file = 0xFFFFFFFF.\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+Maximum TCK operating frequency for this device chain: 10000000.\r\r
+Validating chain...\r\r
+Boundary-scan chain validated successfully.\r\r
+5: Device Temperature: Current Reading:   72.52 C, Min. Reading:   30.69 C, Max.\r\r
+Reading:   74.49 C\r\r
+5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.\r\r
+Reading:   1.002 V\r\r
+5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
+Reading:   2.508 V\r\r
+INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
+\r
+'5': Programming device...\r\r
+ Match_cycle = 2.\r\r
+done.\r\r
+'5': Reading status register contents...\r\r
+CRC error                                         :         0\r\r
+Decryptor security set                            :         0\r\r
+DCM locked                                        :         1\r\r
+DCI matched                                       :         1\r\r
+End of startup signal from Startup block          :         1\r\r
+status of GTS_CFG_B                               :         1\r\r
+status of GWE                                     :         1\r\r
+status of GHIGH                                   :         1\r\r
+value of MODE pin M0                              :         1\r\r
+value of MODE pin M1                              :         0\r\r
+Value of MODE pin M2                              :         1\r\r
+Internal signal indicates when housecleaning is completed:         1\r\r
+Value driver in from INIT pad                     :         1\r\r
+Internal signal indicates that chip is configured :         1\r\r
+Value of DONE pin                                 :         1\r\r
+Indicates when ID value written does not match chip ID:         0\r\r
+Decryptor error Signal                            :         0\r\r
+System Monitor Over-Temperature Alarm             :         0\r\r
+startup_state[18] CFG startup state machine       :         0\r\r
+startup_state[19] CFG startup state machine       :         0\r\r
+startup_state[20] CFG startup state machine       :         1\r\r
+E-fuse program voltage available                  :         0\r\r
+SPI Flash Type[22] Select                         :         1\r\r
+SPI Flash Type[23] Select                         :         1\r\r
+SPI Flash Type[24] Select                         :         1\r\r
+CFG bus width auto detection result               :         0\r\r
+CFG bus width auto detection result               :         0\r\r
+Reserved                                          :         0\r\r
+BPI address wrap around error                     :         0\r\r
+IPROG pulsed                                      :         0\r\r
+read back crc error                               :         0\r\r
+Indicates that efuse logic is busy                :         0\r\r
+ Match_cycle = 2.\r\r
+'5': Programmed successfully.\r\r
+Elapsed time =     11 sec.\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+----------------------------------------------------------------------\r\r
+INFO:iMPACT:2219 - Status register values:\r
+INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
+INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
+INFO:iMPACT - '5': Programing completed successfully.\r
+INFO:iMPACT - '5': Checking done pin....done.\r
+\r
+\r
+\r
+Done!
+\r
+At Local date and time: Sat Jul 04 20:43:42 2009
+ make -f system.make program started...
+\r
+powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
+    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
+-D GCC_PPC440 -mregnames  \r
+powerpc-eabi-size RTOSDemo/executable.elf \r
+   text           data     bss     dec     hex filename\r
+  53174            372   86528  140074   2232a RTOSDemo/executable.elf\r
+\r
+\r
+Done!
+\r
+start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
+\r
+Writing filter settings....
+\r
+Done writing filter settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
+\r
+Done writing Tab View settings to:
+       C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
+\r
+Xilinx Platform Studio (XPS)\r
+Xilinx EDK 11.2 Build EDK_LS3.47
+\r
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+\r
+WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
+\r
+WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
+\r
+Generating Block Diagram to Buffer 
+\r
+Generated Block Diagram SVG
+\r
+At Local date and time: Sun Jul 05 09:35:22 2009
+ make -f system.make hwclean started...
+\r
+rm -f implementation/system.ngc\r
+rm -f platgen.log\r
+rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
+rm -f implementation/system.bmm\r
+rm -f implementation/system.bit\r
+rm -f implementation/system.ncd\r
+rm -f implementation/system_bd.bmm \r
+rm -f implementation/system_map.ncd \r
+rm -f __xps/system_routed\r
+rm -rf implementation synthesis xst hdl\r
+rm -rf xst.srp system.srp\r
+rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
+\r
+\r
+Done!
+\r
+At Local date and time: Sun Jul 05 09:35:36 2009
+ make -f system.make swclean started...
+\r
+rm -rf ppc440_0/\r
+rm -f libgen.log\r
+rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
+rm -f RTOSDemo/executable.elf \r
+\r
+\r
 Done!
 \r
 Writing filter settings....