/******************************************************************************\r
* DISCLAIMER\r
\r
-* This software is supplied by Renesas Technology Corp. and is only\r
+* This software is supplied by Renesas Technology Corp. and is only \r
* intended for use with Renesas products. No other uses are authorized.\r
\r
-* This software is owned by Renesas Technology Corp. and is protected under\r
+* This software is owned by Renesas Technology Corp. and is protected under \r
* all applicable laws, including copyright laws.\r
\r
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES\r
-* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,\r
-* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\r
-* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY\r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
* DISCLAIMED.\r
\r
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
-* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES\r
-* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS \r
* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
\r
-* Renesas reserves the right, without notice, to make changes to this\r
-* software and to discontinue the availability of this software.\r
-* By using this software, you agree to the additional terms and\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software. \r
+* By using this software, you agree to the additional terms and \r
* conditions found by accessing the following link:\r
* http://www.renesas.com/disclaimer\r
******************************************************************************\r
/******************************************************************************\r
Includes <System Includes> , "Project Includes"\r
******************************************************************************/\r
-#include <iodefine.h>\r
+#include "iodefine.h"\r
#include "yrdkrx62ndef.h"\r
// #include "lcd.h" Uncomment this if an LCD is present.\r
-#include "r_ether.h"\r
\r
/******************************************************************************\r
Typedef definitions\r
/******************************************************************************\r
Private global variables and functions\r
******************************************************************************/\r
-void io_set_cpg(void);\r
-void ConfigurePortPins(void);\r
-void EnablePeripheralModules(void);\r
\r
/******************************************************************************\r
* Function Name: HardwareSetup\r
* Description : This function does initial setting for CPG port pins used in\r
-* : the Demo including the MII pins of the Ethernet PHY connection.\r
-* Arguments : none\r
+* : the Demo including the MII pins of the Ethernet PHY connection.\r
+* Arguments : none\r
* Return Value : none\r
******************************************************************************/\r
void HardwareSetup(void)\r
{\r
- /* CPG setting */\r
- io_set_cpg();\r
-\r
- /* Setup the port pins */\r
- ConfigurePortPins();\r
-\r
- /* Enables peripherals */\r
- EnablePeripheralModules();\r
-\r
-#if INCLUDE_LCD == 1\r
- /* Initialize display */\r
- InitialiseDisplay();\r
-#endif\r
-}\r
-\r
-/******************************************************************************\r
-* Function Name: EnablePeripheralModules\r
-* Description : Enables Peripheral Modules before use\r
-* Arguments : none\r
-* Return Value : none\r
-******************************************************************************/\r
-void EnablePeripheralModules(void)\r
-{\r
- /* Module standby clear */\r
- SYSTEM.MSTPCRB.BIT.MSTPB15 = 0; /* EtherC, EDMAC */\r
- SYSTEM.MSTPCRA.BIT.MSTPA15 = 0; /* CMT0 */\r
-}\r
-\r
-/******************************************************************************\r
-* Function Name: ConfigurePortPins\r
-* Description : Configures port pins.\r
-* Arguments : none\r
-* Return Value : none\r
-******************************************************************************/\r
-void ConfigurePortPins(void)\r
-{\r
-/* Port pins default to inputs. To ensure safe initialisation set the pin states\r
-before changing the data direction registers. This will avoid any unintentional\r
-state changes on the external ports.\r
-Many peripheral modules will override the setting of the port registers. Ensure\r
-that the state is safe for external devices if the internal peripheral module is\r
-disabled or powered down. */\r
-\r
- /* ==== MII/RMII Pins setting ==== */\r
- /*--------------------------------------*/\r
- /* Port Function Control Register */\r
- /*--------------------------------------*/\r
-#if ETH_MODE_SEL == ETH_MII_MODE\r
- /* EE=1, PHYMODE=1, ENETE3=1, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */\r
- IOPORT.PFENET.BYTE = 0x9A;\r
-#endif /* ETH_MODE_SEL */\r
-#if ETH_MODE_SEL == ETH_RMII_MODE\r
- /* EE=1, PHYMODE=0, ENETE3=0, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */\r
- IOPORT.PFENET.BYTE = 0x82;\r
-#endif /* ETH_MODE_SEL */\r
- /*-------------------------------------------*/\r
- /* Input Buffer Control Register (ICR) */\r
- /*-------------------------------------------*/\r
-#if ETH_MODE_SEL == ETH_MII_MODE\r
- /* P54=1 Set ET_LINKSTA input */\r
- PORT5.ICR.BIT.B4 = 1;\r
- /* P71=1 Set ET_MDIO input */\r
- PORT7.ICR.BIT.B1 = 1;\r
- /* P74=1 Set ET_ERXD1 input */\r
- PORT7.ICR.BIT.B4 = 1;\r
- /* P75=1 Set ET_ERXD0 input */\r
- PORT7.ICR.BIT.B5 = 1;\r
- /* P76=1 Set ET_RX_CLK input */\r
- PORT7.ICR.BIT.B6 = 1;\r
- /* P77=1 Set ET_RX_ER input */\r
- PORT7.ICR.BIT.B7 = 1;\r
- /* P83=1 Set ET_CRS input */\r
- PORT8.ICR.BIT.B3 = 1;\r
- /* PC0=1 Set ET_ERXD3 input */\r
- PORTC.ICR.BIT.B0 = 1;\r
- /* PC1=1 Set ET_ERXD2 input */\r
- PORTC.ICR.BIT.B1 = 1;\r
- /* PC2=1 Set ET_RX_DV input */\r
- PORTC.ICR.BIT.B2 = 1;\r
- /* PC4=1 Set EX_TX_CLK input */\r
- PORTC.ICR.BIT.B4 = 1;\r
- /* PC7=1 Set ET_COL input */\r
- PORTC.ICR.BIT.B7 = 1;\r
-#endif /* ETH_MODE_SEL */\r
-#if ETH_MODE_SEL == ETH_RMII_MODE\r
- /* P54=1 Set ET_LINKSTA input */\r
- PORT5.ICR.BIT.B4 = 1;\r
- /* P71=1 Set ET_MDIO input */\r
- PORT7.ICR.BIT.B1 = 1;\r
- /* P74=1 Set RMII_RXD1 input */\r
- PORT7.ICR.BIT.B4 = 1;\r
- /* P75=1 Set RMII_RXD0 input */\r
- PORT7.ICR.BIT.B5 = 1;\r
- /* P76=1 Set REF50CLK input */\r
- PORT7.ICR.BIT.B6 = 1;\r
- /* P77=1 Set RMII_RX_ER input */\r
- PORT7.ICR.BIT.B7 = 1;\r
- /* P83=1 Set RMII_CRS_DV input */\r
- PORT8.ICR.BIT.B3 = 1;\r
-#endif /* ETH_MODE_SEL */\r
-\r
- /* Configure LED 0-5 pin settings */\r
- PORT0.DR.BIT.B2 = 1; \r
- PORT0.DR.BIT.B3 = 1;\r
- PORT0.DR.BIT.B5 = 1;\r
- PORT3.DR.BIT.B4 = 1;\r
- PORT6.DR.BIT.B0 = 1;\r
- PORT7.DR.BIT.B3 = 1;\r
- PORT0.DDR.BIT.B2 = 1; \r
- PORT0.DDR.BIT.B3 = 1;\r
- PORT0.DDR.BIT.B5 = 1;\r
- PORT3.DDR.BIT.B4 = 1;\r
- PORT6.DDR.BIT.B0 = 1;\r
- PORT7.DDR.BIT.B3 = 1;\r
-\r
- /* Configure SW 1-3 pin settings */\r
- PORT0.DDR.BIT.B0 = 0;\r
- PORT0.DDR.BIT.B1 = 0;\r
- PORT0.DDR.BIT.B7 = 0;\r
- PORT0.ICR.BIT.B0 = 1;\r
- PORT0.ICR.BIT.B1 = 1;\r
- PORT0.ICR.BIT.B7 = 1;\r
-\r
-#if INCLUDE_LCD == 1\r
- /* Set LCD pins as outputs */\r
- /* LCD-RS */\r
- PORT8.DDR.BIT.B4 = 1;\r
- /* LCD-EN */\r
- PORT8.DDR.BIT.B5 = 1;\r
- /*LCD-data */\r
- PORT9.DDR.BYTE = 0xF0;\r
-#endif\r
+ unsigned long sckcr = 0;\r
+\r
+ /* Configure system clocks based on header */\r
+ sckcr += (ICLK_MUL==8) ? (0ul << 24) : (ICLK_MUL==4) ? (1ul << 24) : (ICLK_MUL==2) ? (2ul << 24) : (3ul << 24);\r
+ sckcr += (BCLK_MUL==8) ? (0ul << 16) : (BCLK_MUL==4) ? (1ul << 16) : (BCLK_MUL==2) ? (2ul << 16) : (3ul << 16);\r
+ sckcr += (PCLK_MUL==8) ? (0ul << 8) : (PCLK_MUL==4) ? (1ul << 8) : (PCLK_MUL==2) ? (2ul << 8) : (3ul << 8);\r
+ SYSTEM.SCKCR.LONG = sckcr;\r
+\r
+ /* Module standby clear - EtherC, EDMAC */\r
+ SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;\r
+\r
+ PORT0.DDR.BYTE = 0x00 ; // Port 0: inputs (IRQ's from ethernet & WiFi)\r
+ PORT1.DDR.BYTE = 0x00 ; // Port 1: inputs (IIC and USB settings will override these later)\r
+ PORT2.DDR.BYTE = 0x1A ; // Port 2: USB signals\r
+ PORT3.DDR.BYTE = 0x04 ; // Port 3: JTAG (P30, P31, P34), CAN (P32=Tx, P33=Rx), NMI (P35)\r
+ PORT4.DDR.BYTE = 0x00 ; // Port 4: Switches (P40-P42), AIN (P43-P47)\r
+ PORT5.DDR.BYTE = 0x3B ; // Port 5: Audio (P55,P54), BCLK (P53), SCI (P52=Rx, P50=Tx), LCD-RS (P51)\r
+\r
+ PORTA.DR.BYTE = 0x00 ; // Port A outputs all LOW to start\r
+ PORTA.DDR.BYTE = 0xFF ; // Port A: Expansion (PA0-PA2), Ether (PA3-PA5), Audio (PA6-PA7)\r
+\r
+ PORTB.DR.BYTE = 0x00 ;\r
+ PORTB.DDR.BYTE = 0x70 ; // Port B: Ether\r
+\r
+ PORTC.DR.BYTE = 0xF7 ; // Port C: Chip selects, clock = high; IO reset = low (not reset, needed by Ether PHY)\r
+ PORTC.DDR.BYTE = 0x7F ; // Port C: SPI (PC0-2, PC4-7), IO reset (PC3) \r
+\r
+ // Ethernet settings\r
+ IOPORT.PFENET.BYTE = 0x82; // Enable Ether poins, RMII mode, enable LINKSTA\r
+ PORTA.ICR.BIT.B5 = 1; // ET_LINKSTA \r
+ PORTA.ICR.BIT.B3 = 1; // ET_MDIO\r
+ PORTB.ICR.BIT.B0 = 1; // RMII_RXD1\r
+ PORTB.ICR.BIT.B1 = 1; // RMII_RXD0\r
+ PORTB.ICR.BIT.B2 = 1; // REF50CLK\r
+ PORTB.ICR.BIT.B3 = 1; // RMII_RX_ER\r
+ PORTB.ICR.BIT.B7 = 1; // RMII_CRS_DV\r
+\r
+\r
+ /* Configure LEDs */\r
+ LED4 = LED_OFF;\r
+ LED5 = LED_OFF;\r
+ LED6 = LED_OFF;\r
+ LED7 = LED_OFF;\r
+ LED8 = LED_OFF;\r
+ LED9 = LED_OFF;\r
+ LED10 = LED_OFF;\r
+ LED11 = LED_OFF;\r
+ LED12 = LED_OFF;\r
+ LED13 = LED_OFF;\r
+ LED14 = LED_OFF;\r
+ LED15 = LED_OFF;\r
+\r
+ LED4_DDR = 1;\r
+ LED5_DDR = 1;\r
+ LED6_DDR = 1;\r
+ LED7_DDR = 1;\r
+ LED8_DDR = 1;\r
+ LED9_DDR = 1;\r
+ LED10_DDR = 1;\r
+ LED11_DDR = 1;\r
+ LED12_DDR = 1;\r
+ LED13_DDR = 1;\r
+ LED14_DDR = 1;\r
+ LED15_DDR = 1;\r
+\r
+ /* Configure push button switches */\r
+ SW1_DDR = 0;\r
+ SW2_DDR = 0;\r
+ SW3_DDR = 0;\r
+ SW1_ICR = 1;\r
+ SW2_ICR = 1;\r
+ SW3_ICR = 1;\r
}\r
\r
-/******************************************************************************\r
-* Function Name: io_set_cpg\r
-* Description : Sets up operating speed\r
-* Arguments : none\r
-* Return Value : none\r
-******************************************************************************/\r
-void io_set_cpg(void)\r
-{\r
-/* Set CPU PLL operating frequencies. Changes to the peripheral clock will require\r
-changes to the debugger and flash kernel BRR settings. */\r
-\r
- /* ==== CPG setting ==== */\r
- SYSTEM.SCKCR.LONG = 0x00020100; /* Clockin = 12MHz */\r
- /* I Clock = 96MHz, B Clock = 24MHz, */\r
- /* P Clock = 48MHz */\r
-\r
-}\r
\r
projects / freertos / blobdiff