Work in progress.

[freertos] / Demo / SuperH_SH7216_Renesas / RTOSDemo / intprg.c

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
index 5afaa787aeb1f44e22e75b2809815dc9f600670f..e5fee0dce90cbdbbad2705d2db755c006e97f11e 100644 (file)
--- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
@@ -16,35 +16,35 @@
 #pragma section IntPRG\r
 \r
 // 4 Illegal code\r
-void INT_Illegal_code(void){/* sleep(); */}\r
+void INT_Illegal_code(void){for( ;; ); /* sleep(); */}\r
 // 5 Reserved\r
 \r
 // 6 Illegal slot\r
-void INT_Illegal_slot(void){/* sleep(); */}\r
+void INT_Illegal_slot(void){for( ;; ); /* sleep(); */}\r
 // 7 Reserved\r
 \r
 // 8 Reserved\r
 \r
 // 9 CPU Address error\r
-void INT_CPU_Address(void){/* sleep(); */}\r
+void INT_CPU_Address(void){for( ;; ); /* sleep(); */}\r
 // 10 DMAC Address error\r
-void INT_DMAC_Address(void){/* sleep(); */}\r
+void INT_DMAC_Address(void){for( ;; ); /* sleep(); */}\r
 // 11 NMI\r
-void INT_NMI(void){/* sleep(); */}\r
+void INT_NMI(void){for( ;; ); /* sleep(); */}\r
 // 12 User breakpoint trap\r
-void INT_User_Break(void){/* sleep(); */}\r
+void INT_User_Break(void){for( ;; ); /* sleep(); */}\r
 // 13 Reserved\r
 \r
 // 14 H-UDI\r
-void INT_HUDI(void){/* sleep(); */}\r
+void INT_HUDI(void){for( ;; ); /* sleep(); */}\r
 // 15 Register bank over\r
-void INT_Bank_Overflow(void){/* sleep(); */}\r
+void INT_Bank_Overflow(void){for( ;; ); /* sleep(); */}\r
 // 16 Register bank under\r
-void INT_Bank_Underflow(void){/* sleep(); */}\r
+void INT_Bank_Underflow(void){for( ;; ); /* sleep(); */}\r
 // 17 ZERO DIV\r
-void INT_Divide_by_Zero(void){/* sleep(); */}\r
+void INT_Divide_by_Zero(void){for( ;; ); /* sleep(); */}\r
 // 18 OVER DIV\r
-void INT_Divide_Overflow(void){/* sleep(); */}\r
+void INT_Divide_Overflow(void){for( ;; ); /* sleep(); */}\r
 // 19 Reserved\r
 \r
 // 20 Reserved\r
@@ -72,85 +72,85 @@ void INT_Divide_Overflow(void){/* sleep(); */}
 // 31 Reserved\r
 \r
 // 32 TRAPA (User Vecter)\r
-void INT_TRAPA32(void){/* sleep(); */}\r
+void INT_TRAPA32(void){ for( ;; ); /* sleep(); */ }\r
 // 33 TRAPA (User Vecter)\r
-void INT_TRAPA33(void){/* sleep(); */}\r
+void INT_TRAPA33(void){for( ;; ); /* sleep(); */}\r
 // 34 TRAPA (User Vecter)\r
-void INT_TRAPA34(void){/* sleep(); */}\r
+void INT_TRAPA34(void){for( ;; ); /* sleep(); */}\r
 // 35 TRAPA (User Vecter)\r
-void INT_TRAPA35(void){/* sleep(); */}\r
+void INT_TRAPA35(void){for( ;; ); /* sleep(); */}\r
 // 36 TRAPA (User Vecter)\r
-void INT_TRAPA36(void){/* sleep(); */}\r
+void INT_TRAPA36(void){for( ;; ); /* sleep(); */}\r
 // 37 TRAPA (User Vecter)\r
-void INT_TRAPA37(void){/* sleep(); */}\r
+void INT_TRAPA37(void){for( ;; ); /* sleep(); */}\r
 // 38 TRAPA (User Vecter)\r
-void INT_TRAPA38(void){/* sleep(); */}\r
+void INT_TRAPA38(void){for( ;; ); /* sleep(); */}\r
 // 39 TRAPA (User Vecter)\r
-void INT_TRAPA39(void){/* sleep(); */}\r
+void INT_TRAPA39(void){for( ;; ); /* sleep(); */}\r
 // 40 TRAPA (User Vecter)\r
-void INT_TRAPA40(void){/* sleep(); */}\r
+void INT_TRAPA40(void){for( ;; ); /* sleep(); */}\r
 // 41 TRAPA (User Vecter)\r
-void INT_TRAPA41(void){/* sleep(); */}\r
+void INT_TRAPA41(void){for( ;; ); /* sleep(); */}\r
 // 42 TRAPA (User Vecter)\r
-void INT_TRAPA42(void){/* sleep(); */}\r
+void INT_TRAPA42(void){for( ;; ); /* sleep(); */}\r
 // 43 TRAPA (User Vecter)\r
-void INT_TRAPA43(void){/* sleep(); */}\r
+void INT_TRAPA43(void){for( ;; ); /* sleep(); */}\r
 // 44 TRAPA (User Vecter)\r
-void INT_TRAPA44(void){/* sleep(); */}\r
+void INT_TRAPA44(void){for( ;; ); /* sleep(); */}\r
 // 45 TRAPA (User Vecter)\r
-void INT_TRAPA45(void){/* sleep(); */}\r
+void INT_TRAPA45(void){for( ;; ); /* sleep(); */}\r
 // 46 TRAPA (User Vecter)\r
-void INT_TRAPA46(void){/* sleep(); */}\r
+void INT_TRAPA46(void){for( ;; ); /* sleep(); */}\r
 // 47 TRAPA (User Vecter)\r
-void INT_TRAPA47(void){/* sleep(); */}\r
+void INT_TRAPA47(void){for( ;; ); /* sleep(); */}\r
 // 48 TRAPA (User Vecter)\r
-void INT_TRAPA48(void){/* sleep(); */}\r
+void INT_TRAPA48(void){for( ;; ); /* sleep(); */}\r
 // 49 TRAPA (User Vecter)\r
-void INT_TRAPA49(void){/* sleep(); */}\r
+void INT_TRAPA49(void){for( ;; ); /* sleep(); */}\r
 // 50 TRAPA (User Vecter)\r
-void INT_TRAPA50(void){/* sleep(); */}\r
+void INT_TRAPA50(void){for( ;; ); /* sleep(); */}\r
 // 51 TRAPA (User Vecter)\r
-void INT_TRAPA51(void){/* sleep(); */}\r
+void INT_TRAPA51(void){for( ;; ); /* sleep(); */}\r
 // 52 TRAPA (User Vecter)\r
-void INT_TRAPA52(void){/* sleep(); */}\r
+void INT_TRAPA52(void){for( ;; ); /* sleep(); */}\r
 // 53 TRAPA (User Vecter)\r
-void INT_TRAPA53(void){/* sleep(); */}\r
+void INT_TRAPA53(void){for( ;; ); /* sleep(); */}\r
 // 54 TRAPA (User Vecter)\r
-void INT_TRAPA54(void){/* sleep(); */}\r
+void INT_TRAPA54(void){for( ;; ); /* sleep(); */}\r
 // 55 TRAPA (User Vecter)\r
-void INT_TRAPA55(void){/* sleep(); */}\r
+void INT_TRAPA55(void){for( ;; ); /* sleep(); */}\r
 // 56 TRAPA (User Vecter)\r
-void INT_TRAPA56(void){/* sleep(); */}\r
+void INT_TRAPA56(void){for( ;; ); /* sleep(); */}\r
 // 57 TRAPA (User Vecter)\r
-void INT_TRAPA57(void){/* sleep(); */}\r
+void INT_TRAPA57(void){for( ;; ); /* sleep(); */}\r
 // 58 TRAPA (User Vecter)\r
-void INT_TRAPA58(void){/* sleep(); */}\r
+void INT_TRAPA58(void){for( ;; ); /* sleep(); */}\r
 // 59 TRAPA (User Vecter)\r
-void INT_TRAPA59(void){/* sleep(); */}\r
+void INT_TRAPA59(void){for( ;; ); /* sleep(); */}\r
 // 60 TRAPA (User Vecter)\r
-void INT_TRAPA60(void){/* sleep(); */}\r
+void INT_TRAPA60(void){for( ;; ); /* sleep(); */}\r
 // 61 TRAPA (User Vecter)\r
-void INT_TRAPA61(void){/* sleep(); */}\r
+void INT_TRAPA61(void){for( ;; ); /* sleep(); */}\r
 // 62 TRAPA (User Vecter)\r
-void INT_TRAPA62(void){/* sleep(); */}\r
+void INT_TRAPA62(void){for( ;; ); /* sleep(); */}\r
 // 63 TRAPA (User Vecter)\r
-void INT_TRAPA63(void){/* sleep(); */}\r
+void INT_TRAPA63(void){for( ;; ); /* sleep(); */}\r
 // 64 Interrupt IRQ0\r
-void INT_IRQ0(void){/* sleep(); */}\r
+void INT_IRQ0(void){for( ;; ); /* sleep(); */}\r
 // 65 Interrupt IRQ1\r
-void INT_IRQ1(void){/* sleep(); */}\r
+void INT_IRQ1(void){for( ;; ); /* sleep(); */}\r
 // 66 Interrupt IRQ2\r
-void INT_IRQ2(void){/* sleep(); */}\r
+void INT_IRQ2(void){for( ;; ); /* sleep(); */}\r
 // 67 Interrupt IRQ3\r
-void INT_IRQ3(void){/* sleep(); */}\r
+void INT_IRQ3(void){for( ;; ); /* sleep(); */}\r
 // 68 Interrupt IRQ4\r
-void INT_IRQ4(void){/* sleep(); */}\r
+void INT_IRQ4(void){for( ;; ); /* sleep(); */}\r
 // 69 Interrupt IRQ5\r
-void INT_IRQ5(void){/* sleep(); */}\r
+void INT_IRQ5(void){for( ;; ); /* sleep(); */}\r
 // 70 Interrupt IRQ6\r
-void INT_IRQ6(void){/* sleep(); */}\r
+void INT_IRQ6(void){for( ;; ); /* sleep(); */}\r
 // 71 Interrupt IRQ7\r
-void INT_IRQ7(void){/* sleep(); */}\r
+void INT_IRQ7(void){for( ;; ); /* sleep(); */}\r
 // 72 Reserved\r
 \r
 // 73 Reserved\r
@@ -168,21 +168,21 @@ void INT_IRQ7(void){/* sleep(); */}
 // 79 Reserved\r
 \r
 // 80 Interrupt PINT0\r
-void INT_PINT0(void){/* sleep(); */}\r
+void INT_PINT0(void){for( ;; ); /* sleep(); */}\r
 // 81 Interrupt PINT1\r
-void INT_PINT1(void){/* sleep(); */}\r
+void INT_PINT1(void){for( ;; ); /* sleep(); */}\r
 // 82 Interrupt PINT2\r
-void INT_PINT2(void){/* sleep(); */}\r
+void INT_PINT2(void){for( ;; ); /* sleep(); */}\r
 // 83 Interrupt PINT3\r
-void INT_PINT3(void){/* sleep(); */}\r
+void INT_PINT3(void){for( ;; ); /* sleep(); */}\r
 // 84 Interrupt PINT4\r
-void INT_PINT4(void){/* sleep(); */}\r
+void INT_PINT4(void){for( ;; ); /* sleep(); */}\r
 // 85 Interrupt PINT5\r
-void INT_PINT5(void){/* sleep(); */}\r
+void INT_PINT5(void){for( ;; ); /* sleep(); */}\r
 // 86 Interrupt PINT6\r
-void INT_PINT6(void){/* sleep(); */}\r
+void INT_PINT6(void){for( ;; ); /* sleep(); */}\r
 // 87 Interrupt PINT7\r
-void INT_PINT7(void){/* sleep(); */}\r
+void INT_PINT7(void){for( ;; ); /* sleep(); */}\r
 // 88 Reserved\r
 \r
 // 89 Reserved\r
@@ -190,9 +190,9 @@ void INT_PINT7(void){/* sleep(); */}
 // 90 Reserved\r
 \r
 // 91 ROM FIFE\r
-void INT_ROM_FIFE(void){/* sleep(); */}\r
+void INT_ROM_FIFE(void){for( ;; ); /* sleep(); */}\r
 // 92 A/D ADI0\r
-void INT_AD_ADI0(void){/* sleep(); */}\r
+void INT_AD_ADI0(void){for( ;; ); /* sleep(); */}\r
 // 93 Reserved\r
 \r
 // 94 Reserved\r
@@ -200,7 +200,7 @@ void INT_AD_ADI0(void){/* sleep(); */}
 // 95 Reserved\r
 \r
 // 96 A/D ADI1\r
-void INT_AD_ADI1(void){/* sleep(); */}\r
+void INT_AD_ADI1(void){for( ;; ); /* sleep(); */}\r
 // 97 Reserved\r
 \r
 // 98 Reserved\r
@@ -216,79 +216,79 @@ void INT_AD_ADI1(void){/* sleep(); */}
 // 103 Reserved\r
 \r
 // 104 RCANET0 ERS_0\r
-void INT_RCANET0_ERS_0(void){/* sleep(); */}\r
+void INT_RCANET0_ERS_0(void){for( ;; ); /* sleep(); */}\r
 // 105 RCANET0 OVR_0\r
-void INT_RCANET0_OVR_0(void){/* sleep(); */}\r
+void INT_RCANET0_OVR_0(void){for( ;; ); /* sleep(); */}\r
 // 106 RCANET0 RM01_0\r
-void INT_RCANET0_RM01_0(void){/* sleep(); */}\r
+void INT_RCANET0_RM01_0(void){for( ;; ); /* sleep(); */}\r
 // 107 RCANET0 SLE_0\r
-void INT_RCANET0_SLE_0(void){/* sleep(); */}\r
+void INT_RCANET0_SLE_0(void){for( ;; ); /* sleep(); */}\r
 // 108 DMAC0 DEI0\r
-void INT_DMAC0_DEI0(void){/* sleep(); */}\r
+void INT_DMAC0_DEI0(void){for( ;; ); /* sleep(); */}\r
 // 109 DMAC0 HEI0\r
-void INT_DMAC0_HEI0(void){/* sleep(); */}\r
+void INT_DMAC0_HEI0(void){for( ;; ); /* sleep(); */}\r
 // 110 Reserved\r
 \r
 // 111 Reserved\r
 \r
 // 112 DMAC1 DEI1\r
-void INT_DMAC1_DEI1(void){/* sleep(); */}\r
+void INT_DMAC1_DEI1(void){for( ;; ); /* sleep(); */}\r
 // 113 DMAC1 HEI1\r
-void INT_DMAC1_HEI1(void){/* sleep(); */}\r
+void INT_DMAC1_HEI1(void){for( ;; ); /* sleep(); */}\r
 // 114 Reserved\r
 \r
 // 115 Reserved\r
 \r
 // 116 DMAC2 DEI2\r
-void INT_DMAC2_DEI2(void){/* sleep(); */}\r
+void INT_DMAC2_DEI2(void){for( ;; ); /* sleep(); */}\r
 // 117 DMAC2 HEI2\r
-void INT_DMAC2_HEI2(void){/* sleep(); */}\r
+void INT_DMAC2_HEI2(void){for( ;; ); /* sleep(); */}\r
 // 118 Reserved\r
 \r
 // 119 Reserved\r
 \r
 // 120 DMAC3 DEI3\r
-void INT_DMAC3_DEI3(void){/* sleep(); */}\r
+void INT_DMAC3_DEI3(void){for( ;; ); /* sleep(); */}\r
 // 121 DMAC3 HEI3\r
-void INT_DMAC3_HEI3(void){/* sleep(); */}\r
+void INT_DMAC3_HEI3(void){for( ;; ); /* sleep(); */}\r
 // 122 Reserved\r
 \r
 // 123 Reserved\r
 \r
 // 124 DMAC4 DEI4\r
-void INT_DMAC4_DEI4(void){/* sleep(); */}\r
+void INT_DMAC4_DEI4(void){for( ;; ); /* sleep(); */}\r
 // 125 DMAC4 HEI4\r
-void INT_DMAC4_HEI4(void){/* sleep(); */}\r
+void INT_DMAC4_HEI4(void){for( ;; ); /* sleep(); */}\r
 // 126 Reserved\r
 \r
 // 127 Reserved\r
 \r
 // 128 DMAC5 DEI5\r
-void INT_DMAC5_DEI5(void){/* sleep(); */}\r
+void INT_DMAC5_DEI5(void){for( ;; ); /* sleep(); */}\r
 // 129 DMAC5 HEI5\r
-void INT_DMAC5_HEI5(void){/* sleep(); */}\r
+void INT_DMAC5_HEI5(void){for( ;; ); /* sleep(); */}\r
 // 130 Reserved\r
 \r
 // 131 Reserved\r
 \r
 // 132 DMAC6 DEI6\r
-void INT_DMAC6_DEI6(void){/* sleep(); */}\r
+void INT_DMAC6_DEI6(void){for( ;; ); /* sleep(); */}\r
 // 133 DMAC6 HEI6\r
-void INT_DMAC6_HEI6(void){/* sleep(); */}\r
+void INT_DMAC6_HEI6(void){for( ;; ); /* sleep(); */}\r
 // 134 Reserved\r
 \r
 // 135 Reserved\r
 \r
 // 136 DMAC7 DEI7\r
-void INT_DMAC7_DEI7(void){/* sleep(); */}\r
+void INT_DMAC7_DEI7(void){for( ;; ); /* sleep(); */}\r
 // 137 DMAC7 HEI7\r
-void INT_DMAC7_HEI7(void){/* sleep(); */}\r
+void INT_DMAC7_HEI7(void){for( ;; ); /* sleep(); */}\r
 // 138 Reserved\r
 \r
 // 139 Reserved\r
 \r
 // 140 CMT CMI0\r
-void INT_CMT_CMI0(void){/* sleep(); */}\r
+//void INT_CMT_CMI0(void){for( ;; ); /* sleep(); */}\r
 // 141 Reserved\r
 \r
 // 142 Reserved\r
@@ -296,7 +296,7 @@ void INT_CMT_CMI0(void){/* sleep(); */}
 // 143 Reserved\r
 \r
 // 144 CMT CMI1\r
-void INT_CMT_CMI1(void){/* sleep(); */}\r
+void INT_CMT_CMI1(void){for( ;; ); /* sleep(); */}\r
 // 145 Reserved\r
 \r
 // 146 Reserved\r
@@ -304,79 +304,79 @@ void INT_CMT_CMI1(void){/* sleep(); */}
 // 147 Reserved\r
 \r
 // 148 BSC CMTI\r
-void INT_BSC_CMTI(void){/* sleep(); */}\r
+void INT_BSC_CMTI(void){for( ;; ); /* sleep(); */}\r
 // 149 Reserved\r
 \r
 // 150 USB EP4FULL\r
-void INT_USB_EP4FULL(void){/* sleep(); */}\r
+void INT_USB_EP4FULL(void){for( ;; ); /* sleep(); */}\r
 // 151 USB EP5EMPTY\r
-void INT_USB_EP5EMPTY(void){/* sleep(); */}\r
+void INT_USB_EP5EMPTY(void){for( ;; ); /* sleep(); */}\r
 // 152 WDT ITI\r
-void INT_WDT_ITI(void){/* sleep(); */}\r
+void INT_WDT_ITI(void){for( ;; ); /* sleep(); */}\r
 // 153 E-DMAC EINT0\r
-void INT_EDMAC_EINT0(void){/* sleep(); */}\r
+void INT_EDMAC_EINT0(void){for( ;; ); /* sleep(); */}\r
 // 154 USB EP1FULL\r
-void INT_USB_EP1FULL(void){/* sleep(); */}\r
+void INT_USB_EP1FULL(void){for( ;; ); /* sleep(); */}\r
 // 155 USB EP2EMPTY\r
-void INT_USB_EP2EMPTY(void){/* sleep(); */}\r
+void INT_USB_EP2EMPTY(void){for( ;; ); /* sleep(); */}\r
 // 156 MTU2 MTU0 TGI0A\r
-void INT_MTU2_MTU0_TGI0A(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0A(void){for( ;; ); /* sleep(); */}\r
 // 157 MTU2 MTU0 TGI0B\r
-void INT_MTU2_MTU0_TGI0B(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0B(void){for( ;; ); /* sleep(); */}\r
 // 158 MTU2 MTU0 TGI0C\r
-void INT_MTU2_MTU0_TGI0C(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0C(void){for( ;; ); /* sleep(); */}\r
 // 159 MTU2 MTU0 TGI0D\r
-void INT_MTU2_MTU0_TGI0D(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0D(void){for( ;; ); /* sleep(); */}\r
 // 160 MTU2 MTU0 TGI0V\r
-void INT_MTU2_MTU0_TGI0V(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0V(void){for( ;; ); /* sleep(); */}\r
 // 161 MTU2 MTU0 TGI0E\r
-void INT_MTU2_MTU0_TGI0E(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0E(void){for( ;; ); /* sleep(); */}\r
 // 162 MTU2 MTU0 TGI0F\r
-void INT_MTU2_MTU0_TGI0F(void){/* sleep(); */}\r
+void INT_MTU2_MTU0_TGI0F(void){for( ;; ); /* sleep(); */}\r
 // 163 Reserved\r
 \r
 // 164 MTU2 MTU1 TGI1A\r
-void INT_MTU2_MTU1_TGI1A(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1A(void){for( ;; ); /* sleep(); */}\r
 // 165 MTU2 MTU1 TGI1B\r
-void INT_MTU2_MTU1_TGI1B(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1B(void){for( ;; ); /* sleep(); */}\r
 // 166 Reserved \r
 \r
 // 167 Reserved\r
 \r
 // 168 MTU2 MTU1 TGI1V\r
-void INT_MTU2_MTU1_TGI1V(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1V(void){for( ;; ); /* sleep(); */}\r
 // 169 MTU2 MTU1 TGI1U\r
-void INT_MTU2_MTU1_TGI1U(void){/* sleep(); */}\r
+void INT_MTU2_MTU1_TGI1U(void){for( ;; ); /* sleep(); */}\r
 // 170 Reserved \r
 \r
 // 171 Reserved\r
 \r
 // 172 MTU2 MTU2 TGI2A\r
-void INT_MTU2_MTU2_TGI2A(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2A(void){for( ;; ); /* sleep(); */}\r
 // 173 MTU2 MTU2 TGI2B\r
-void INT_MTU2_MTU2_TGI2B(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2B(void){for( ;; ); /* sleep(); */}\r
 // 174 Reserved \r
 \r
 // 175 Reserved\r
 \r
 // 176 MTU2 MTU2 TGI2V\r
-void INT_MTU2_MTU2_TGI2V(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2V(void){for( ;; ); /* sleep(); */}\r
 // 177 MTU2 MTU2 TGI2U\r
-void INT_MTU2_MTU2_TGI2U(void){/* sleep(); */}\r
+void INT_MTU2_MTU2_TGI2U(void){for( ;; ); /* sleep(); */}\r
 // 178 Reserved \r
 \r
 // 179 Reserved\r
 \r
 // 180 MTU2 MTU3 TGI3A\r
-void INT_MTU2_MTU3_TGI3A(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3A(void){for( ;; ); /* sleep(); */}\r
 // 181 MTU2 MTU3 TGI3B\r
-void INT_MTU2_MTU3_TGI3B(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3B(void){for( ;; ); /* sleep(); */}\r
 // 182 MTU2 MTU3 TGI3C\r
-void INT_MTU2_MTU3_TGI3C(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3C(void){for( ;; ); /* sleep(); */}\r
 // 183 MTU2 MTU3 TGI3D\r
-void INT_MTU2_MTU3_TGI3D(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3D(void){for( ;; ); /* sleep(); */}\r
 // 184 MTU2 MTU3 TGI3V\r
-void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */}\r
+void INT_MTU2_MTU3_TGI3V(void){for( ;; ); /* sleep(); */}\r
 // 185 Reserved \r
 \r
 // 186 Reserved\r
@@ -384,15 +384,15 @@ void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */}
 // 187 Reserved \r
 \r
 // 188 MTU2 MTU4 TGI4A\r
-void INT_MTU2_MTU4_TGI4A(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4A(void){for( ;; ); /* sleep(); */}\r
 // 189 MTU2 MTU4 TGI4B\r
-void INT_MTU2_MTU4_TGI4B(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4B(void){for( ;; ); /* sleep(); */}\r
 // 190 MTU2 MTU4 TGI4C\r
-void INT_MTU2_MTU4_TGI4C(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4C(void){for( ;; ); /* sleep(); */}\r
 // 191 MTU2 MTU4 TGI4D\r
-void INT_MTU2_MTU4_TGI4D(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4D(void){for( ;; ); /* sleep(); */}\r
 // 192 MTU2 MTU4 TGI4V\r
-void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */}\r
+void INT_MTU2_MTU4_TGI4V(void){for( ;; ); /* sleep(); */}\r
 // 193 Reserved \r
 \r
 // 194 Reserved\r
@@ -400,31 +400,31 @@ void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */}
 // 195 Reserved \r
 \r
 // 196 MTU2 MTU5 TGI5U\r
-void INT_MTU2_MTU5_TGI5U(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5U(void){for( ;; ); /* sleep(); */}\r
 // 197 MTU2 MTU5 TGI5V\r
-void INT_MTU2_MTU5_TGI5V(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5V(void){for( ;; ); /* sleep(); */}\r
 // 198 MTU2 MTU5 TGI5W\r
-void INT_MTU2_MTU5_TGI5W(void){/* sleep(); */}\r
+void INT_MTU2_MTU5_TGI5W(void){for( ;; ); /* sleep(); */}\r
 // 199 Reserved \r
 \r
 // 200 POE2 OEI1\r
-void INT_POE2_OEI1(void){/* sleep(); */}\r
+void INT_POE2_OEI1(void){for( ;; ); /* sleep(); */}\r
 // 201 POE2 OEI2 \r
-void INT_POE2_OEI2(void){/* sleep(); */}\r
+void INT_POE2_OEI2(void){for( ;; ); /* sleep(); */}\r
 // 202 Reserved \r
 \r
 // 203 Reserved\r
 \r
 // 204 MTU2S MTU3S TGI3A \r
-void INT_MTU2S_MTU3S_TGI3A(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3A(void){for( ;; ); /* sleep(); */}\r
 // 205 MTU2S MTU3S TGI3B\r
-void INT_MTU2S_MTU3S_TGI3B(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3B(void){for( ;; ); /* sleep(); */}\r
 // 206 MTU2S MTU3S TGI3C\r
-void INT_MTU2S_MTU3S_TGI3C(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3C(void){for( ;; ); /* sleep(); */}\r
 // 207 MTU2S MTU3S TGI3D \r
-void INT_MTU2S_MTU3S_TGI3D(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3D(void){for( ;; ); /* sleep(); */}\r
 // 208 MTU2S MTU3S TGI3V\r
-void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU3S_TGI3V(void){for( ;; ); /* sleep(); */}\r
 // 209 Reserved \r
 \r
 // 210 Reserved \r
@@ -432,15 +432,15 @@ void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */}
 // 211 Reserved\r
 \r
 // 212 MTU2S MTU4S TGI4A \r
-void INT_MTU2S_MTU4S_TGI4A(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4A(void){for( ;; ); /* sleep(); */}\r
 // 213 MTU2S MTU4S TGI4B \r
-void INT_MTU2S_MTU4S_TGI4B(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4B(void){for( ;; ); /* sleep(); */}\r
 // 214 MTU2S MTU4S TGI4C \r
-void INT_MTU2S_MTU4S_TGI4C(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4C(void){for( ;; ); /* sleep(); */}\r
 // 215 MTU2S MTU4S TGI4D \r
-void INT_MTU2S_MTU4S_TGI4D(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4D(void){for( ;; ); /* sleep(); */}\r
 // 216 MTU2S MTU4S TGI4V \r
-void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU4S_TGI4V(void){for( ;; ); /* sleep(); */}\r
 // 217 Reserved \r
 \r
 // 218 Reserved\r
@@ -448,78 +448,78 @@ void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */}
 // 219 Reserved \r
 \r
 // 220 MTU2S MTU5S TGI5U \r
-void INT_MTU2S_MTU5S_TGI5U(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5U(void){for( ;; ); /* sleep(); */}\r
 // 221 MTU2S MTU5S TGI5V\r
-void INT_MTU2S_MTU5S_TGI5V(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5V(void){for( ;; ); /* sleep(); */}\r
 // 222 MTU2S MTU5S TGI5W \r
-void INT_MTU2S_MTU5S_TGI5W(void){/* sleep(); */}\r
+void INT_MTU2S_MTU5S_TGI5W(void){for( ;; ); /* sleep(); */}\r
 // 223 Reserved\r
 \r
 // 224 POE2 OEI3\r
-void INT_POE2_OEI3(void){/* sleep(); */}\r
+void INT_POE2_OEI3(void){for( ;; ); /* sleep(); */}\r
 // 225 Reserved\r
 \r
 // 226 USB USI0\r
-void INT_USB_USI0(void){/* sleep(); */}\r
+void INT_USB_USI0(void){for( ;; ); /* sleep(); */}\r
 // 227 USB USI1\r
-void INT_USB_USI1(void){/* sleep(); */}\r
+void INT_USB_USI1(void){for( ;; ); /* sleep(); */}\r
 // 228 IIC3 STPI\r
-void INT_IIC3_STPI(void){/* sleep(); */}\r
+void INT_IIC3_STPI(void){for( ;; ); /* sleep(); */}\r
 // 229 IIC3 NAKI \r
-void INT_IIC3_NAKI(void){/* sleep(); */}\r
+void INT_IIC3_NAKI(void){for( ;; ); /* sleep(); */}\r
 // 230 IIC3 RXI \r
-void INT_IIC3_RXI(void){/* sleep(); */}\r
+void INT_IIC3_RXI(void){for( ;; ); /* sleep(); */}\r
 // 231 IIC3 TXI\r
-void INT_IIC3_TXI(void){/* sleep(); */}\r
+void INT_IIC3_TXI(void){for( ;; ); /* sleep(); */}\r
 // 232 IIC3 TEI \r
-void INT_IIC3_TEI(void){/* sleep(); */}\r
+void INT_IIC3_TEI(void){for( ;; ); /* sleep(); */}\r
 // 233 RSPI SPERI\r
-void INT_RSPI_SPERI(void){/* sleep(); */}\r
+void INT_RSPI_SPERI(void){for( ;; ); /* sleep(); */}\r
 // 234 RSPI SPRXI\r
-void INT_RSPI_SPRXI(void){/* sleep(); */}\r
+void INT_RSPI_SPRXI(void){for( ;; ); /* sleep(); */}\r
 // 235 RSPI SPTXI\r
-void INT_RSPI_SPTXI(void){/* sleep(); */}\r
+void INT_RSPI_SPTXI(void){for( ;; ); /* sleep(); */}\r
 // 236 SCI SCI4 ERI4\r
-void INT_SCI_SCI4_ERI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_ERI4(void){for( ;; ); /* sleep(); */}\r
 // 237 SCI SCI4 RXI4\r
-void INT_SCI_SCI4_RXI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_RXI4(void){for( ;; ); /* sleep(); */}\r
 // 238 SCI SCI4 TXI4\r
-void INT_SCI_SCI4_TXI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_TXI4(void){for( ;; ); /* sleep(); */}\r
 // 239 SCI SCI4 TEI4\r
-void INT_SCI_SCI4_TEI4(void){/* sleep(); */}\r
+void INT_SCI_SCI4_TEI4(void){for( ;; ); /* sleep(); */}\r
 // 240 SCI SCI0 ERI0\r
-void INT_SCI_SCI0_ERI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_ERI0(void){for( ;; ); /* sleep(); */}\r
 // 241 SCI SCI0 RXI0\r
-void INT_SCI_SCI0_RXI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_RXI0(void){for( ;; ); /* sleep(); */}\r
 // 242 SCI SCI0 TXI0\r
-void INT_SCI_SCI0_TXI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_TXI0(void){for( ;; ); /* sleep(); */}\r
 // 243 SCI SCI0 TEI0\r
-void INT_SCI_SCI0_TEI0(void){/* sleep(); */}\r
+void INT_SCI_SCI0_TEI0(void){for( ;; ); /* sleep(); */}\r
 // 244 SCI SCI1 ERI1\r
-void INT_SCI_SCI1_ERI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_ERI1(void){for( ;; ); /* sleep(); */}\r
 // 245 SCI SCI1 RXI1\r
-void INT_SCI_SCI1_RXI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_RXI1(void){for( ;; ); /* sleep(); */}\r
 // 246 SCI SCI1 TXI1\r
-void INT_SCI_SCI1_TXI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_TXI1(void){for( ;; ); /* sleep(); */}\r
 // 247 SCI SCI1 TEI1\r
-void INT_SCI_SCI1_TEI1(void){/* sleep(); */}\r
+void INT_SCI_SCI1_TEI1(void){for( ;; ); /* sleep(); */}\r
 // 248 SCI SCI2 ERI2\r
-void INT_SCI_SCI2_ERI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_ERI2(void){for( ;; ); /* sleep(); */}\r
 // 249 SCI SCI2 RXI2\r
-void INT_SCI_SCI2_RXI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_RXI2(void){for( ;; ); /* sleep(); */}\r
 // 250 SCI SCI2 TXI2\r
-void INT_SCI_SCI2_TXI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_TXI2(void){for( ;; ); /* sleep(); */}\r
 // 251 SCI SCI2 TEI2\r
-void INT_SCI_SCI2_TEI2(void){/* sleep(); */}\r
+void INT_SCI_SCI2_TEI2(void){for( ;; ); /* sleep(); */}\r
 // 252 SCIF SCIF3 BRI3\r
-void INT_SCIF_SCIF3_BRI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_BRI3(void){for( ;; ); /* sleep(); */}\r
 // 253 SCIF SCIF3 ERI3\r
-void INT_SCIF_SCIF3_ERI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_ERI3(void){for( ;; ); /* sleep(); */}\r
 // 254 SCIF SCIF3 RXI3\r
-void INT_SCIF_SCIF3_RXI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_RXI3(void){for( ;; ); /* sleep(); */}\r
 // 255 SCIF SCIF3 TXI3\r
-void INT_SCIF_SCIF3_TXI3(void){/* sleep(); */}\r
+void INT_SCIF_SCIF3_TXI3(void){for( ;; ); /* sleep(); */}\r
 // Dummy\r
-void Dummy(void){/* sleep(); */}\r
+void Dummy(void){ for( ;; ); sleep(); }\r
 \r
 /* End of File */\r