/*\r
- FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section \r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- See http://www.FreeRTOS.org for documentation, latest information, license \r
- and contact details. Please ensure to read the configuration and relevant \r
- port sections of the online documentation.\r
- ***************************************************************************\r
+ FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
*/\r
\r
/*\r
/*-----------------------------------------------------------*/\r
\r
/* Hardwired i2c address of the WIZNet device. */\r
-#define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )\r
+#define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )\r
\r
/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet\r
device. */\r
-#define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )\r
-#define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )\r
+#define tcp8K_RX ( ( unsigned char ) 0x03 )\r
+#define tcp8K_TX ( ( unsigned char ) 0x03 )\r
\r
/* Constants used to generate the WIZnet internal buffer addresses. */\r
-#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )\r
-#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )\r
+#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )\r
+#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )\r
\r
/* Bit definitions of the commands that can be sent to the command register. */\r
-#define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )\r
-#define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )\r
-#define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )\r
-#define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )\r
-#define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )\r
-#define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )\r
-#define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )\r
-#define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )\r
+#define tcpRESET_CMD ( ( unsigned char ) 0x80 )\r
+#define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )\r
+#define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )\r
+#define tcpSOCK_INIT ( ( unsigned char ) 0x02 )\r
+#define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )\r
+#define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )\r
+#define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )\r
+#define tcpSEND_CMD ( ( unsigned char ) 0x20 )\r
\r
/* Constants required to handle the interrupts. */\r
#define tcpCLEAR_EINT0 ( 1 )\r
-#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )\r
-#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )\r
-#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )\r
+#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )\r
+#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )\r
+#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )\r
#define tcpWAKE_ON_EINT0 ( 1 )\r
-#define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )\r
-#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )\r
-#define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )\r
-#define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+#define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )\r
+#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )\r
+#define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )\r
+#define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )\r
\r
/* Various delays used in the driver. */\r
#define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )\r
#define tcpNO_DELAY ( ( portTickType ) 0 )\r
\r
/* Length of the data to read for various register reads. */\r
-#define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )\r
-#define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )\r
+#define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )\r
+#define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )\r
\r
/* Register addresses within the WIZnet device. */\r
-#define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )\r
-#define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )\r
-#define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )\r
-#define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )\r
-#define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )\r
-#define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )\r
-#define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )\r
-#define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )\r
-#define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )\r
-#define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )\r
-#define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )\r
-#define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )\r
-#define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )\r
-#define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )\r
-#define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )\r
-#define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )\r
-#define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )\r
-#define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )\r
+#define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )\r
+#define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )\r
+#define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )\r
+#define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )\r
+#define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )\r
+#define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )\r
+#define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )\r
+#define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )\r
+#define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )\r
+#define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )\r
+#define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )\r
+#define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )\r
+#define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )\r
+#define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )\r
+#define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )\r
+#define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )\r
+#define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )\r
+#define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )\r
\r
/* Constants required for hardware setup. */\r
-#define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )\r
-#define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )\r
+#define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )\r
+#define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )\r
\r
/* Constants defining the source of the WIZnet ISR. */\r
-#define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )\r
-#define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )\r
-#define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )\r
-#define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )\r
-#define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )\r
-#define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )\r
-#define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )\r
+#define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )\r
+#define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )\r
+#define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )\r
+#define tcpISR_CLOSED ( ( unsigned char ) 0x08 )\r
+#define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )\r
+#define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )\r
+#define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )\r
\r
/* Constants defining the socket status bits. */\r
-#define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )\r
-#define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )\r
+#define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )\r
+#define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )\r
\r
/* Misc constants. */\r
-#define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )\r
-#define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )\r
+#define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )\r
+#define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )\r
#define i2cNO_DATA_REQUIRED ( 0x0000 )\r
#define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )\r
#define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )\r
\r
/* Message definitions. The IP address, MAC address, gateway address, etc.\r
is set here! */\r
-const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */\r
-const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */\r
-const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */\r
-const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */\r
+const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */\r
+const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */\r
+const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */\r
+const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */\r
\r
/* Other fixed messages. */\r
-const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD }; \r
-const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD }; \r
-const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };\r
-const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };\r
-const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };\r
-const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
-const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
-const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
-const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };\r
-const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };\r
-const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };\r
-const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };\r
-const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };\r
-const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };\r
-const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };\r
-const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };\r
-const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };\r
+const unsigned char const ucDataReset[] = { tcpRESET_CMD }; \r
+const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD }; \r
+const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };\r
+const unsigned char const ucDataPort[] = { 0xBA, 0xCC };\r
+const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };\r
+const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };\r
+const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };\r
+const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };\r
+const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };\r
+const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };\r
+const unsigned char const ucDataSend[] = { tcpSEND_CMD };\r
+const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };\r
+const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };\r
+const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };\r
+const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };\r
\r
static xSemaphoreHandle xMessageComplete = NULL;\r
xQueueHandle xTCPISRQueue = NULL;\r
static void prvSendSamplePage( void );\r
\r
/* Read a register from the WIZnet device via the i2c interface. */\r
-static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );\r
+static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );\r
\r
/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */\r
-static void prvFlushBuffer( unsigned portLONG ulTxAddress );\r
+static void prvFlushBuffer( unsigned long ulTxAddress );\r
\r
/* Write a string to the WIZnet Tx buffer. */\r
-static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );\r
+static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );\r
\r
/* Convert a number to a string. */\r
-void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );\r
+void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );\r
\r
/*-----------------------------------------------------------*/\r
\r
-void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )\r
+void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )\r
{\r
-unsigned portLONG lNibble;\r
-portLONG lIndex;\r
+unsigned long lNibble;\r
+long lIndex;\r
\r
/* Simple routine to convert an unsigned long value into a string in hex \r
format. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )\r
+static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )\r
{\r
-unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];\r
+unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];\r
\r
/* Read a register value from the WIZnet device. */\r
\r
i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );\r
\r
/* Then read back from that address. */\r
- i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );\r
+ i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );\r
\r
/* I2C messages are queued so use the semaphore to wait for the read to \r
complete - otherwise we will leave this function before the I2C \r
/* Install the ISR into the VIC - but don't enable it yet! */\r
portENTER_CRITICAL();\r
{\r
- extern void ( vEINT0_ISR )( void );\r
+ extern void ( vEINT0_ISR_Wrapper )( void );\r
\r
VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );\r
- VICVectAddr3 = ( portLONG ) vEINT0_ISR;\r
+ VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;\r
\r
VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portLONG lTCPSoftReset( void )\r
+long lTCPSoftReset( void )\r
{\r
-unsigned portCHAR ucStatus;\r
-extern volatile portLONG lTransactionCompleted;\r
+unsigned char ucStatus;\r
+extern volatile long lTransactionCompleted;\r
\r
/* Send a message to the WIZnet device to tell it set all it's registers\r
back to their default states. Then setup the WIZnet device as required. */\r
/* We should find that the sys init was successful. */\r
if( ucStatus != tcpISR_SYS_INIT )\r
{\r
- return ( portLONG ) pdFAIL;\r
+ return ( long ) pdFAIL;\r
}\r
\r
/* No i2c errors yet. */\r
lTransactionCompleted = pdTRUE;\r
portEXIT_CRITICAL();\r
\r
- return ( portLONG ) pdPASS;\r
+ return ( long ) pdPASS;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portLONG lTCPCreateSocket( void )\r
+long lTCPCreateSocket( void )\r
{\r
-unsigned portCHAR ucStatus;\r
+unsigned char ucStatus;\r
\r
/* Create and configure a socket. */\r
\r
{\r
/* For some reason the message was not transmitted within our block\r
period. */\r
- return ( portLONG ) pdFAIL;\r
+ return ( long ) pdFAIL;\r
}\r
\r
/* Allow the socket to initialise. */\r
/* We should find that the socket init was successful. */\r
if( ucStatus != tcpISR_SOCKET_INIT )\r
{\r
- return ( portLONG ) pdFAIL;\r
+ return ( long ) pdFAIL;\r
}\r
\r
\r
i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );\r
vTaskDelay( tcpSHORT_DELAY );\r
\r
- return ( portLONG ) pdPASS;\r
+ return ( long ) pdPASS;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vTCPListen( void )\r
{\r
-unsigned portCHAR ucISR;\r
+unsigned char ucISR;\r
\r
/* Start a passive listen on the socket. */\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-portLONG lProcessConnection( void )\r
+long lProcessConnection( void )\r
{\r
-unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;\r
-extern volatile portLONG lTransactionCompleted;\r
-portLONG lSameStateCount = 0, lDataSent = pdFALSE;\r
-unsigned portLONG ulWritePointer, ulAckPointer;\r
+unsigned char ucISR, ucState, ucLastState = 2, ucShadow;\r
+extern volatile long lTransactionCompleted;\r
+long lSameStateCount = 0, lDataSent = pdFALSE;\r
+unsigned long ulWritePointer, ulAckPointer;\r
\r
/* No I2C errors can yet have occurred. */\r
portENTER_CRITICAL();\r
vTaskDelay( tcpSHORT_DELAY );\r
\r
/* Then we can read the real register. */\r
- prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );\r
+ prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );\r
\r
/* We cannot do anything more here but need to remember that \r
this interrupt has occurred. */\r
register. */\r
prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );\r
vTaskDelay( tcpSHORT_DELAY );\r
- prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );\r
+ prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );\r
\r
if( ulAckPointer == ulWritePointer )\r
{\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )\r
+static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )\r
{\r
-unsigned portLONG ulSendAddress;\r
+unsigned long ulSendAddress;\r
\r
/* Send a string to the Tx buffer internal to the WIZnet device. */\r
\r
\r
/* Send the buffer to the calculated address. Use the semaphore so we\r
can wait until the entire message has been transferred. */\r
- i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
+ i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );\r
\r
/* Wait until the semaphore indicates that the message has been transferred. */\r
if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )\r
\r
/* Return the new address of the end of the buffer (within the WIZnet \r
device). */\r
- *pulTxAddress += ( unsigned portLONG ) lTxLen;\r
+ *pulTxAddress += ( unsigned long ) lTxLen;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvFlushBuffer( unsigned portLONG ulTxAddress )\r
+static void prvFlushBuffer( unsigned long ulTxAddress )\r
{\r
-unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];\r
+unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];\r
\r
/* We have written some data to the Tx buffer internal to the WIZnet\r
device. Now we update the Tx pointer inside the WIZnet then send a\r
ulTxAddress = htonl( ulTxAddress );\r
\r
/* Place the new Tx pointer in the string to be transmitted. */\r
- ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );\r
ulTxAddress >>= 8;\r
- ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );\r
ulTxAddress >>= 8;\r
- ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );\r
ulTxAddress >>= 8;\r
- ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );\r
+ ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );\r
ulTxAddress >>= 8;\r
\r
/* And send it to the WIZnet device. */\r
\r
static void prvSendSamplePage( void )\r
{\r
-extern portLONG lErrorInTask;\r
-unsigned portLONG ulTxAddress;\r
-unsigned portCHAR ucShadow;\r
-portLONG lIndex;\r
-static unsigned portLONG ulRefreshCount = 0x00;\r
-static portCHAR cPageBuffer[ tcpBUFFER_LEN ];\r
+extern long lErrorInTask;\r
+unsigned long ulTxAddress;\r
+unsigned char ucShadow;\r
+long lIndex;\r
+static unsigned long ulRefreshCount = 0x00;\r
+static char cPageBuffer[ tcpBUFFER_LEN ];\r
\r
\r
/* This function just generates a sample page of HTML which gets\r
vTaskDelay( tcpSHORT_DELAY );\r
\r
/* Now we can read the real pointer value. */\r
- prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );\r
+ prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );\r
\r
/* Make sure endieness is correct. */\r
ulTxAddress = htonl( ulTxAddress );\r
ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );\r
strcat( cPageBuffer, "<br>Number of tasks executing = ");\r
lIndex = strlen( cPageBuffer );\r
- ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );\r
+ ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );\r
strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );\r
lIndex = strlen( cPageBuffer );\r
- ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );\r
+ ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );\r
strcat( cPageBuffer, "<br>Refresh = 0x" );\r
lIndex = strlen( cPageBuffer );\r
- ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );\r
+ ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );\r
\r
if( lErrorInTask )\r
{\r
projects / freertos / blobdiff