/*\r
- FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section \r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
\r
***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
***************************************************************************\r
- * *\r
- * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
- * and even write all or part of your application on your behalf. *\r
- * See http://www.OpenRTOS.com for details of the services we provide to *\r
- * expedite your project. *\r
- * *\r
- ***************************************************************************\r
- ***************************************************************************\r
-\r
- Please ensure to read the configuration and relevant port sections of the\r
- online documentation.\r
\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
- contact details.\r
\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
- critical systems.\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
- licensing and training services.\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
*/\r
\r
\r
/*-----------------------------------------------------------*/\r
\r
/* Constants to setup the microcontroller IO. */\r
-#define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 )\r
-#define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 )\r
+#define mainSDA_ENABLE ( ( unsigned long ) 0x0040 )\r
+#define mainSCL_ENABLE ( ( unsigned long ) 0x0010 )\r
\r
/* Bit definitions within the I2CONCLR register. */\r
-#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )\r
-#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )\r
-#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )\r
+#define i2cSTA_BIT ( ( unsigned char ) 0x20 )\r
+#define i2cSI_BIT ( ( unsigned char ) 0x08 )\r
+#define i2cSTO_BIT ( ( unsigned char ) 0x10 )\r
\r
/* Constants required to setup the VIC. */\r
-#define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 )\r
-#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 )\r
-#define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+#define i2cI2C_VIC_CHANNEL ( ( unsigned long ) 0x0009 )\r
+#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0200 )\r
+#define i2cI2C_VIC_ENABLE ( ( unsigned long ) 0x0020 )\r
\r
/* Misc constants. */\r
#define i2cNO_BLOCK ( ( portTickType ) 0 )\r
-#define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 )\r
-#define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 )\r
-#define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 )\r
-#define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 )\r
+#define i2cQUEUE_LENGTH ( ( unsigned char ) 5 )\r
+#define i2cEXTRA_MESSAGES ( ( unsigned char ) 2 )\r
+#define i2cREAD_TX_LEN ( ( unsigned long ) 2 )\r
+#define i2cACTIVE_MASTER_MODE ( ( unsigned char ) 0x40 )\r
#define i2cTIMERL ( 200 )\r
#define i2cTIMERH ( 200 )\r
\r
static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];\r
\r
/* Function in the ARM part of the code used to create the queues. */\r
-extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree );\r
+extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned long **ppulBusFree );\r
\r
/* Index to the next free message in the xTxMessages array. */\r
-unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0;\r
+unsigned long ulNextFreeMessage = ( unsigned long ) 0;\r
\r
/* Queue of messages that are waiting transmission. */\r
static xQueueHandle xMessagesForTx;\r
\r
/* Flag to indicate the state of the I2C ISR state machine. */\r
-static unsigned portLONG *pulBusFree;\r
+static unsigned long *pulBusFree;\r
\r
/*-----------------------------------------------------------*/\r
-void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )\r
+void i2cMessage( const unsigned char * const pucMessage, long lMessageLength, unsigned char ucSlaveAddress, unsigned short usBufferAddress, unsigned long ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )\r
{\r
extern volatile xI2CMessage *pxCurrentMessage;\r
xI2CMessage *pxNextFreeMessage;\r
actual data is not copied, so the data being pointed to must still\r
be valid when the message eventually gets sent (it may be queued for\r
a while. */\r
- pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage; \r
+ pxNextFreeMessage->pucBuffer = ( unsigned char * ) pucMessage; \r
\r
/* This is the address of the I2C device we are going to transmit this\r
message to. */\r
- pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection;\r
+ pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned char ) ulDirection;\r
\r
/* A semaphore can be used to allow the I2C ISR to indicate that the\r
message has been sent. This can be NULL if you don't want to wait for\r
/* The address within the WIZnet device to which the data will be \r
written. This could be the address of a register, or alternatively\r
a location within the WIZnet Tx buffer. */\r
- pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );\r
+ pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned char ) ( usBufferAddress & 0xff );\r
\r
/* Second byte of the address. */\r
usBufferAddress >>= 8;\r
- pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );\r
+ pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned char ) ( usBufferAddress & 0xff );\r
\r
/* Increment to the next message in the array - with a wrap around check. */\r
ulNextFreeMessage++;\r
if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )\r
{\r
- ulNextFreeMessage = ( unsigned portLONG ) 0;\r
+ ulNextFreeMessage = ( unsigned long ) 0;\r
}\r
\r
/* Is the I2C interrupt in the middle of transmitting a message? */\r
- if( *pulBusFree == ( unsigned portLONG ) pdTRUE )\r
+ if( *pulBusFree == ( unsigned long ) pdTRUE )\r
{\r
/* No message is currently being sent or queued to be sent. We\r
can start the ISR sending this message immediately. */\r
I2C_I2CONCLR = i2cSI_BIT; \r
I2C_I2CONSET = i2cSTA_BIT;\r
\r
- *pulBusFree = ( unsigned portLONG ) pdFALSE;\r
+ *pulBusFree = ( unsigned long ) pdFALSE;\r
}\r
else\r
{\r
was the case then the interrupt would have been enabled and we may\r
now find that the I2C interrupt routine is no longer sending a\r
message. */\r
- if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )\r
+ if( ( *pulBusFree == ( unsigned long ) pdTRUE ) && ( xReturn == pdPASS ) )\r
{\r
/* Get the next message in the queue (this should be the \r
message we just posted) and start off the transmission\r
I2C_I2CONCLR = i2cSI_BIT; \r
I2C_I2CONSET = i2cSTA_BIT;\r
\r
- *pulBusFree = ( unsigned portLONG ) pdFALSE;\r
+ *pulBusFree = ( unsigned long ) pdFALSE;\r
}\r
}\r
}\r
/* Setup the VIC for the i2c interrupt. */\r
VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );\r
VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;\r
- VICVectAddr2 = ( portLONG ) vI2C_ISR_Wrapper;\r
+ VICVectAddr2 = ( long ) vI2C_ISR_Wrapper;\r
\r
VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;\r
}\r
projects / freertos / blobdiff